+1

drivers/gpu/drm/i915/display/intel_atomic.c

reviewed

··· 200 200 crtc_state->update_wm_pre = false; 201 201 crtc_state->update_wm_post = false; 202 202 crtc_state->fifo_changed = false; 203 203 + crtc_state->preload_luts = false; 203 204 crtc_state->wm.need_postvbl_update = false; 204 205 crtc_state->fb_bits = 0; 205 206 crtc_state->update_planes = 0;

+61

drivers/gpu/drm/i915/display/intel_color.c

reviewed

··· 1022 1022 dev_priv->display.color_commit(crtc_state); 1023 1023 } 1024 1024 1025 1025 + static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1026 1026 + { 1027 1027 + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); 1028 1028 + struct intel_atomic_state *state = 1029 1029 + to_intel_atomic_state(new_crtc_state->base.state); 1030 1030 + const struct intel_crtc_state *old_crtc_state = 1031 1031 + intel_atomic_get_old_crtc_state(state, crtc); 1032 1032 + 1033 1033 + return !old_crtc_state->base.gamma_lut && 1034 1034 + !old_crtc_state->base.degamma_lut; 1035 1035 + } 1036 1036 + 1037 1037 + static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1038 1038 + { 1039 1039 + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); 1040 1040 + struct intel_atomic_state *state = 1041 1041 + to_intel_atomic_state(new_crtc_state->base.state); 1042 1042 + const struct intel_crtc_state *old_crtc_state = 1043 1043 + intel_atomic_get_old_crtc_state(state, crtc); 1044 1044 + 1045 1045 + /* 1046 1046 + * CGM_PIPE_MODE is itself single buffered. We'd have to 1047 1047 + * somehow split it out from chv_load_luts() if we wanted 1048 1048 + * the ability to preload the CGM LUTs/CSC without tearing. 1049 1049 + */ 1050 1050 + if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode) 1051 1051 + return false; 1052 1052 + 1053 1053 + return !old_crtc_state->base.gamma_lut; 1054 1054 + } 1055 1055 + 1056 1056 + static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1057 1057 + { 1058 1058 + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); 1059 1059 + struct intel_atomic_state *state = 1060 1060 + to_intel_atomic_state(new_crtc_state->base.state); 1061 1061 + const struct intel_crtc_state *old_crtc_state = 1062 1062 + intel_atomic_get_old_crtc_state(state, crtc); 1063 1063 + 1064 1064 + /* 1065 1065 + * The hardware degamma is active whenever the pipe 1066 1066 + * CSC is active. Thus even if the old state has no 1067 1067 + * software degamma we need to avoid clobbering the 1068 1068 + * linear hardware degamma mid scanout. 1069 1069 + */ 1070 1070 + return !old_crtc_state->csc_enable && 1071 1071 + !old_crtc_state->base.gamma_lut; 1072 1072 + } 1073 1073 + 1025 1074 int intel_color_check(struct intel_crtc_state *crtc_state) 1026 1075 { 1027 1076 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); ··· 1214 1165 if (ret) 1215 1166 return ret; 1216 1167 1168 1168 + crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1169 1169 + 1217 1170 return 0; 1218 1171 } 1219 1172 ··· 1267 1216 ret = intel_color_add_affected_planes(crtc_state); 1268 1217 if (ret) 1269 1218 return ret; 1219 1219 + 1220 1220 + crtc_state->preload_luts = chv_can_preload_luts(crtc_state); 1270 1221 1271 1222 return 0; 1272 1223 } ··· 1323 1270 ret = intel_color_add_affected_planes(crtc_state); 1324 1271 if (ret) 1325 1272 return ret; 1273 1273 + 1274 1274 + crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1326 1275 1327 1276 return 0; 1328 1277 } ··· 1383 1328 if (ret) 1384 1329 return ret; 1385 1330 1331 1331 + crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1332 1332 + 1386 1333 return 0; 1387 1334 } 1388 1335 ··· 1422 1365 ret = intel_color_add_affected_planes(crtc_state); 1423 1366 if (ret) 1424 1367 return ret; 1368 1368 + 1369 1369 + crtc_state->preload_luts = glk_can_preload_luts(crtc_state); 1425 1370 1426 1371 return 0; 1427 1372 } ··· 1473 1414 crtc_state->gamma_mode = icl_gamma_mode(crtc_state); 1474 1415 1475 1416 crtc_state->csc_mode = icl_csc_mode(crtc_state); 1417 1417 + 1418 1418 + crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1476 1419 1477 1420 return 0; 1478 1421 }

+6 -4

drivers/gpu/drm/i915/display/intel_ddi.c

reviewed

··· 1794 1794 * of Color Encoding Format and Content Color Gamut] while sending 1795 1795 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 1796 1796 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1797 1797 - * 1798 1798 - * FIXME MST doesn't pass in the conn_state 1799 1797 */ 1800 1800 - if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1798 1798 + if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1801 1799 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 1802 1800 1803 1801 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); ··· 3603 3605 else 3604 3606 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3605 3607 3606 3606 - intel_ddi_set_dp_msa(crtc_state, conn_state); 3608 3608 + /* MST will call a setting of MSA after an allocating of Virtual Channel 3609 3609 + * from MST encoder pre_enable callback. 3610 3610 + */ 3611 3611 + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 3612 3612 + intel_ddi_set_dp_msa(crtc_state, conn_state); 3607 3613 } 3608 3614 3609 3615 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,

+10

drivers/gpu/drm/i915/display/intel_display.c

reviewed

··· 66 66 #include "intel_cdclk.h" 67 67 #include "intel_color.h" 68 68 #include "intel_display_types.h" 69 69 + #include "intel_dp_link_training.h" 69 70 #include "intel_fbc.h" 70 71 #include "intel_fbdev.h" 71 72 #include "intel_fifo_underrun.h" ··· 2529 2528 * the highest stride limits of them all. 2530 2529 */ 2531 2530 crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); 2531 2531 + if (!crtc) 2532 2532 + return 0; 2533 2533 + 2532 2534 plane = to_intel_plane(crtc->base.primary); 2533 2535 2534 2536 return plane->max_stride(plane, pixel_format, modifier, ··· 14205 14201 /* vblanks work again, re-enable pipe CRC. */ 14206 14202 intel_crtc_enable_pipe_crc(crtc); 14207 14203 } else { 14204 14204 + if (new_crtc_state->preload_luts && 14205 14205 + (new_crtc_state->base.color_mgmt_changed || 14206 14206 + new_crtc_state->update_pipe)) 14207 14207 + intel_color_load_luts(new_crtc_state); 14208 14208 + 14208 14209 intel_pre_plane_update(old_crtc_state, new_crtc_state); 14209 14210 14210 14211 if (new_crtc_state->update_pipe) ··· 14722 14713 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 14723 14714 if (new_crtc_state->base.active && 14724 14715 !needs_modeset(new_crtc_state) && 14716 14716 + !new_crtc_state->preload_luts && 14725 14717 (new_crtc_state->base.color_mgmt_changed || 14726 14718 new_crtc_state->update_pipe)) 14727 14719 intel_color_load_luts(new_crtc_state);

-1

drivers/gpu/drm/i915/display/intel_display.h

reviewed

··· 27 27 28 28 #include <drm/drm_util.h> 29 29 #include <drm/i915_drm.h> 30 30 - #include "intel_dp_link_training.h" 31 30 32 31 enum link_m_n_set; 33 32 struct dpll;

+1

drivers/gpu/drm/i915/display/intel_display_types.h

reviewed

··· 775 775 bool disable_cxsr; 776 776 bool update_wm_pre, update_wm_post; /* watermarks are updated */ 777 777 bool fifo_changed; /* FIFO split is changed */ 778 778 + bool preload_luts; 778 779 779 780 /* Pipe source size (ie. panel fitter input size) 780 781 * All planes will be positioned inside this space,

+2

drivers/gpu/drm/i915/display/intel_dp_mst.c

reviewed

··· 331 331 ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); 332 332 333 333 intel_ddi_enable_pipe_clock(pipe_config); 334 334 + 335 335 + intel_ddi_set_dp_msa(pipe_config, conn_state); 334 336 } 335 337 336 338 static void intel_mst_enable_dp(struct intel_encoder *encoder,

+1 -1

drivers/gpu/drm/i915/gem/i915_gem_context.c

reviewed

··· 1141 1141 1142 1142 if (i915_gem_context_is_closed(ctx)) { 1143 1143 err = -ENOENT; 1144 1144 - goto out; 1144 1144 + goto unlock; 1145 1145 } 1146 1146 1147 1147 if (vm == rcu_access_pointer(ctx->vm))

+21 -1

drivers/gpu/drm/i915/gem/i915_gem_userptr.c

reviewed

··· 646 646 obj->mm.dirty = false; 647 647 648 648 for_each_sgt_page(page, sgt_iter, pages) { 649 649 - if (obj->mm.dirty) 649 649 + if (obj->mm.dirty && trylock_page(page)) { 650 650 + /* 651 651 + * As this may not be anonymous memory (e.g. shmem) 652 652 + * but exist on a real mapping, we have to lock 653 653 + * the page in order to dirty it -- holding 654 654 + * the page reference is not sufficient to 655 655 + * prevent the inode from being truncated. 656 656 + * Play safe and take the lock. 657 657 + * 658 658 + * However...! 659 659 + * 660 660 + * The mmu-notifier can be invalidated for a 661 661 + * migrate_page, that is alreadying holding the lock 662 662 + * on the page. Such a try_to_unmap() will result 663 663 + * in us calling put_pages() and so recursively try 664 664 + * to lock the page. We avoid that deadlock with 665 665 + * a trylock_page() and in exchange we risk missing 666 666 + * some page dirtying. 667 667 + */ 650 668 set_page_dirty(page); 669 669 + unlock_page(page); 670 670 + } 651 671 652 672 mark_page_accessed(page); 653 673 put_page(page);

+2

drivers/gpu/drm/i915/gt/intel_engine_cs.c

reviewed

··· 1372 1372 } 1373 1373 1374 1374 execlists_active_lock_bh(execlists); 1375 1375 + rcu_read_lock(); 1375 1376 for (port = execlists->active; (rq = *port); port++) { 1376 1377 char hdr[80]; 1377 1378 int len; ··· 1410 1409 if (tl) 1411 1410 intel_timeline_put(tl); 1412 1411 } 1412 1412 + rcu_read_unlock(); 1413 1413 execlists_active_unlock_bh(execlists); 1414 1414 } else if (INTEL_GEN(dev_priv) > 6) { 1415 1415 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",

+2 -2

drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c

reviewed

··· 141 141 142 142 void intel_engine_park_heartbeat(struct intel_engine_cs *engine) 143 143 { 144 144 - cancel_delayed_work(&engine->heartbeat.work); 145 145 - i915_request_put(fetch_and_zero(&engine->heartbeat.systole)); 144 144 + if (cancel_delayed_work(&engine->heartbeat.work)) 145 145 + i915_request_put(fetch_and_zero(&engine->heartbeat.systole)); 146 146 } 147 147 148 148 void intel_engine_init_heartbeat(struct intel_engine_cs *engine)

+66 -60

drivers/gpu/drm/i915/gt/intel_lrc.c

reviewed

··· 990 990 write_sequnlock_irqrestore(&engine->stats.lock, flags); 991 991 } 992 992 993 993 - static inline struct intel_engine_cs * 994 994 - __execlists_schedule_in(struct i915_request *rq) 995 995 - { 996 996 - struct intel_engine_cs * const engine = rq->engine; 997 997 - struct intel_context * const ce = rq->hw_context; 998 998 - 999 999 - intel_context_get(ce); 1000 1000 - 1001 1001 - if (ce->tag) { 1002 1002 - /* Use a fixed tag for OA and friends */ 1003 1003 - ce->lrc_desc |= (u64)ce->tag << 32; 1004 1004 - } else { 1005 1005 - /* We don't need a strict matching tag, just different values */ 1006 1006 - ce->lrc_desc &= ~GENMASK_ULL(47, 37); 1007 1007 - ce->lrc_desc |= 1008 1008 - (u64)(engine->context_tag++ % NUM_CONTEXT_TAG) << 1009 1009 - GEN11_SW_CTX_ID_SHIFT; 1010 1010 - BUILD_BUG_ON(NUM_CONTEXT_TAG > GEN12_MAX_CONTEXT_HW_ID); 1011 1011 - } 1012 1012 - 1013 1013 - intel_gt_pm_get(engine->gt); 1014 1014 - execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); 1015 1015 - intel_engine_context_in(engine); 1016 1016 - 1017 1017 - return engine; 1018 1018 - } 1019 1019 - 1020 1020 - static inline struct i915_request * 1021 1021 - execlists_schedule_in(struct i915_request *rq, int idx) 1022 1022 - { 1023 1023 - struct intel_context * const ce = rq->hw_context; 1024 1024 - struct intel_engine_cs *old; 1025 1025 - 1026 1026 - GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine)); 1027 1027 - trace_i915_request_in(rq, idx); 1028 1028 - 1029 1029 - old = READ_ONCE(ce->inflight); 1030 1030 - do { 1031 1031 - if (!old) { 1032 1032 - WRITE_ONCE(ce->inflight, __execlists_schedule_in(rq)); 1033 1033 - break; 1034 1034 - } 1035 1035 - } while (!try_cmpxchg(&ce->inflight, &old, ptr_inc(old))); 1036 1036 - 1037 1037 - GEM_BUG_ON(intel_context_inflight(ce) != rq->engine); 1038 1038 - return i915_request_get(rq); 1039 1039 - } 1040 1040 - 1041 1041 - static void kick_siblings(struct i915_request *rq, struct intel_context *ce) 1042 1042 - { 1043 1043 - struct virtual_engine *ve = container_of(ce, typeof(*ve), context); 1044 1044 - struct i915_request *next = READ_ONCE(ve->request); 1045 1045 - 1046 1046 - if (next && next->execution_mask & ~rq->execution_mask) 1047 1047 - tasklet_schedule(&ve->base.execlists.tasklet); 1048 1048 - } 1049 1049 - 1050 993 static void restore_default_state(struct intel_context *ce, 1051 994 struct intel_engine_cs *engine) 1052 995 { ··· 1043 1100 ce->lrc_desc |= CTX_DESC_FORCE_RESTORE; 1044 1101 } 1045 1102 1103 1103 + static inline struct intel_engine_cs * 1104 1104 + __execlists_schedule_in(struct i915_request *rq) 1105 1105 + { 1106 1106 + struct intel_engine_cs * const engine = rq->engine; 1107 1107 + struct intel_context * const ce = rq->hw_context; 1108 1108 + 1109 1109 + intel_context_get(ce); 1110 1110 + 1111 1111 + if (unlikely(i915_gem_context_is_banned(ce->gem_context))) 1112 1112 + reset_active(rq, engine); 1113 1113 + 1114 1114 + if (ce->tag) { 1115 1115 + /* Use a fixed tag for OA and friends */ 1116 1116 + ce->lrc_desc |= (u64)ce->tag << 32; 1117 1117 + } else { 1118 1118 + /* We don't need a strict matching tag, just different values */ 1119 1119 + ce->lrc_desc &= ~GENMASK_ULL(47, 37); 1120 1120 + ce->lrc_desc |= 1121 1121 + (u64)(engine->context_tag++ % NUM_CONTEXT_TAG) << 1122 1122 + GEN11_SW_CTX_ID_SHIFT; 1123 1123 + BUILD_BUG_ON(NUM_CONTEXT_TAG > GEN12_MAX_CONTEXT_HW_ID); 1124 1124 + } 1125 1125 + 1126 1126 + intel_gt_pm_get(engine->gt); 1127 1127 + execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); 1128 1128 + intel_engine_context_in(engine); 1129 1129 + 1130 1130 + return engine; 1131 1131 + } 1132 1132 + 1133 1133 + static inline struct i915_request * 1134 1134 + execlists_schedule_in(struct i915_request *rq, int idx) 1135 1135 + { 1136 1136 + struct intel_context * const ce = rq->hw_context; 1137 1137 + struct intel_engine_cs *old; 1138 1138 + 1139 1139 + GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine)); 1140 1140 + trace_i915_request_in(rq, idx); 1141 1141 + 1142 1142 + old = READ_ONCE(ce->inflight); 1143 1143 + do { 1144 1144 + if (!old) { 1145 1145 + WRITE_ONCE(ce->inflight, __execlists_schedule_in(rq)); 1146 1146 + break; 1147 1147 + } 1148 1148 + } while (!try_cmpxchg(&ce->inflight, &old, ptr_inc(old))); 1149 1149 + 1150 1150 + GEM_BUG_ON(intel_context_inflight(ce) != rq->engine); 1151 1151 + return i915_request_get(rq); 1152 1152 + } 1153 1153 + 1154 1154 + static void kick_siblings(struct i915_request *rq, struct intel_context *ce) 1155 1155 + { 1156 1156 + struct virtual_engine *ve = container_of(ce, typeof(*ve), context); 1157 1157 + struct i915_request *next = READ_ONCE(ve->request); 1158 1158 + 1159 1159 + if (next && next->execution_mask & ~rq->execution_mask) 1160 1160 + tasklet_schedule(&ve->base.execlists.tasklet); 1161 1161 + } 1162 1162 + 1046 1163 static inline void 1047 1164 __execlists_schedule_out(struct i915_request *rq, 1048 1165 struct intel_engine_cs * const engine) 1049 1166 { 1050 1167 struct intel_context * const ce = rq->hw_context; 1051 1168 1169 1169 + /* 1170 1170 + * NB process_csb() is not under the engine->active.lock and hence 1171 1171 + * schedule_out can race with schedule_in meaning that we should 1172 1172 + * refrain from doing non-trivial work here. 1173 1173 + */ 1174 1174 + 1052 1175 intel_engine_context_out(engine); 1053 1176 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); 1054 1177 intel_gt_pm_put(engine->gt); 1055 1055 - 1056 1056 - if (unlikely(i915_gem_context_is_banned(ce->gem_context))) 1057 1057 - reset_active(rq, engine); 1058 1178 1059 1179 /* 1060 1180 * If this is part of a virtual engine, its next request may

-2

drivers/gpu/drm/i915/i915_gem_gtt.c

reviewed

··· 2609 2609 GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != ggtt_unbind_vma); 2610 2610 ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma; 2611 2611 2612 2612 - ppgtt->vm.total = ggtt->vm.total; 2613 2613 - 2614 2612 return 0; 2615 2613 2616 2614 err_ppgtt:

+10 -10

drivers/gpu/drm/i915/i915_perf.c

reviewed

··· 3307 3307 } 3308 3308 } 3309 3309 3310 3310 - if (props->hold_preemption) { 3311 3311 - if (!props->single_context) { 3312 3312 - DRM_DEBUG("preemption disable with no context\n"); 3313 3313 - ret = -EINVAL; 3314 3314 - goto err; 3315 3315 - } 3316 3316 - privileged_op = true; 3317 3317 - } 3318 3318 - 3319 3310 /* 3320 3311 * On Haswell the OA unit supports clock gating off for a specific 3321 3312 * context and in this mode there's no visibility of metrics for the ··· 3326 3335 * doesn't request global stream access (i.e. query based sampling 3327 3336 * using MI_RECORD_PERF_COUNT. 3328 3337 */ 3329 3329 - if (IS_HASWELL(perf->i915) && specific_ctx && !props->hold_preemption) 3338 3338 + if (IS_HASWELL(perf->i915) && specific_ctx) 3330 3339 privileged_op = false; 3331 3340 else if (IS_GEN(perf->i915, 12) && specific_ctx && 3332 3341 (props->sample_flags & SAMPLE_OA_REPORT) == 0) 3333 3342 privileged_op = false; 3343 3343 + 3344 3344 + if (props->hold_preemption) { 3345 3345 + if (!props->single_context) { 3346 3346 + DRM_DEBUG("preemption disable with no context\n"); 3347 3347 + ret = -EINVAL; 3348 3348 + goto err; 3349 3349 + } 3350 3350 + privileged_op = true; 3351 3351 + } 3334 3352 3335 3353 /* Similar to perf's kernel.perf_paranoid_cpu sysctl option 3336 3354 * we check a dev.i915.perf_stream_paranoid sysctl option

+2 -2

drivers/gpu/drm/i915/i915_pmu.c

reviewed

··· 878 878 const char *name; 879 879 const char *unit; 880 880 } events[] = { 881 881 - __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "MHz"), 882 882 - __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency", "MHz"), 881 881 + __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"), 882 882 + __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency", "M"), 883 883 __event(I915_PMU_INTERRUPTS, "interrupts", NULL), 884 884 __event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"), 885 885 };