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phy: qcom: edp: Fix the DP_PHY_AUX_CFG registers count

On all platforms supported by this driver, there are 13 DP_PHY_AUX_CFGx
registers. This hasn't been an issue so far on currently supported
platforms, because the init sequence never spanned beyond DP_PHY_AUX_CFG9.

However, on the new upcoming Glymur platform, these are updated along
with the rest of the init sequence.

So update the size of the array holding the config to 13.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-glymur-support-v6-2-4fcba75a6fa9@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Abel Vesa and committed by
Vinod Koul 2d472a67 8f97b9b3

+1 -1
+1 -1
drivers/phy/qualcomm/phy-qcom-edp.c
··· 32 32 #define DP_PHY_PD_CTL 0x001c 33 33 #define DP_PHY_MODE 0x0020 34 34 35 - #define DP_AUX_CFG_SIZE 10 35 + #define DP_AUX_CFG_SIZE 13 36 36 #define DP_PHY_AUX_CFG(n) (0x24 + (0x04 * (n))) 37 37 38 38 #define DP_PHY_AUX_INTERRUPT_MASK 0x0058