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Merge tag 'perf-urgent-2023-05-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf fixes from Thomas Gleixner:
"A small set of perf fixes:

- Make the MSR-readout based CHA discovery work around broken
discovery tables in some SPR firmwares.

- Prevent saving PEBS configuration which has software bits set that
cause a crash when restored into the relevant MSR"

* tag 'perf-urgent-2023-05-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/uncore: Correct the number of CHAs on SPR
perf/x86/intel: Save/restore cpuc->active_pebs_data_cfg when using guest PEBS

+12 -1
+1 -1
arch/x86/events/intel/core.c
··· 4074 4074 if (x86_pmu.intel_cap.pebs_baseline) { 4075 4075 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4076 4076 .msr = MSR_PEBS_DATA_CFG, 4077 - .host = cpuc->pebs_data_cfg, 4077 + .host = cpuc->active_pebs_data_cfg, 4078 4078 .guest = kvm_pmu->pebs_data_cfg, 4079 4079 }; 4080 4080 }
+11
arch/x86/events/intel/uncore_snbep.c
··· 6150 6150 }; 6151 6151 6152 6152 #define UNCORE_SPR_NUM_UNCORE_TYPES 12 6153 + #define UNCORE_SPR_CHA 0 6153 6154 #define UNCORE_SPR_IIO 1 6154 6155 #define UNCORE_SPR_IMC 6 6155 6156 #define UNCORE_SPR_UPI 8 ··· 6461 6460 return max + 1; 6462 6461 } 6463 6462 6463 + #define SPR_MSR_UNC_CBO_CONFIG 0x2FFE 6464 + 6464 6465 void spr_uncore_cpu_init(void) 6465 6466 { 6467 + struct intel_uncore_type *type; 6468 + u64 num_cbo; 6469 + 6466 6470 uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR, 6467 6471 UNCORE_SPR_MSR_EXTRA_UNCORES, 6468 6472 spr_msr_uncores); 6469 6473 6474 + type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA); 6475 + if (type) { 6476 + rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo); 6477 + type->num_boxes = num_cbo; 6478 + } 6470 6479 spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO); 6471 6480 } 6472 6481