Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: dma: xlnx,axi-dma: Convert to DT schema
Convert the bindings document for Xilinx DMA.
No changes to existing binding description.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260309033444.3472359-1-abin.joseph@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Abin Joseph
and committed by
Vinod Koul
2d5c2952
dece5b91
+299
-111
-111
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
-111
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
···
1
-
Xilinx AXI VDMA engine, it does transfers between memory and video devices.
2
-
It can be configured to have one channel or two channels. If configured
3
-
as two channels, one is to transmit to the video device and another is
4
-
to receive from the video device.
5
-
6
-
Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
7
-
target devices. It can be configured to have one channel or two channels.
8
-
If configured as two channels, one is to transmit to the device and another
9
-
is to receive from the device.
10
-
11
-
Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12
-
address and a memory-mapped destination address.
13
-
14
-
Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
15
-
target devices. It can be configured to have up to 16 independent transmit
16
-
and receive channels.
17
-
18
-
Required properties:
19
-
- compatible: Should be one of-
20
-
"xlnx,axi-vdma-1.00.a"
21
-
"xlnx,axi-dma-1.00.a"
22
-
"xlnx,axi-cdma-1.00.a"
23
-
"xlnx,axi-mcdma-1.00.a"
24
-
- #dma-cells: Should be <1>, see "dmas" property below
25
-
- reg: Should contain VDMA registers location and length.
26
-
- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
27
-
- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
28
-
- dma-channel child node: Should have at least one channel and can have up to
29
-
two channels per device. This node specifies the properties of each
30
-
DMA channel (see child node properties below).
31
-
- clocks: Input clock specifier. Refer to common clock bindings.
32
-
- clock-names: List of input clocks
33
-
For VDMA:
34
-
Required elements: "s_axi_lite_aclk"
35
-
Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
36
-
"m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
37
-
For CDMA:
38
-
Required elements: "s_axi_lite_aclk", "m_axi_aclk"
39
-
For AXIDMA and MCDMA:
40
-
Required elements: "s_axi_lite_aclk"
41
-
Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
42
-
"m_axi_sg_aclk"
43
-
44
-
Required properties for VDMA:
45
-
- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
46
-
47
-
Optional properties for AXI DMA and MCDMA:
48
-
- xlnx,sg-length-width: Should be set to the width in bits of the length
49
-
register as configured in h/w. Takes values {8...26}. If the property
50
-
is missing or invalid then the default value 23 is used. This is the
51
-
maximum value that is supported by all IP versions.
52
-
53
-
Optional properties for AXI DMA:
54
-
- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
55
-
- xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from
56
-
0-255. Setting this value to zero disables the delay timer interrupt.
57
-
1 timeout interval = 125 * clock period of SG clock.
58
-
Optional properties for VDMA:
59
-
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
60
-
It takes following values:
61
-
{1}, flush both channels
62
-
{2}, flush mm2s channel
63
-
{3}, flush s2mm channel
64
-
65
-
Required child node properties:
66
-
- compatible:
67
-
For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
68
-
"xlnx,axi-vdma-s2mm-channel".
69
-
For CDMA: It should be "xlnx,axi-cdma-channel".
70
-
For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel"
71
-
or "xlnx,axi-dma-s2mm-channel".
72
-
- interrupts: Should contain per channel VDMA interrupts.
73
-
- xlnx,datawidth: Should contain the stream data width, take values
74
-
{32,64...1024}.
75
-
76
-
Optional child node properties:
77
-
- xlnx,include-dre: Tells hardware is configured for Data
78
-
Realignment Engine.
79
-
Optional child node properties for VDMA:
80
-
- xlnx,genlock-mode: Tells Genlock synchronization is
81
-
enabled/disabled in hardware.
82
-
- xlnx,enable-vert-flip: Tells vertical flip is
83
-
enabled/disabled in hardware(S2MM path).
84
-
Optional child node properties for MCDMA:
85
-
- dma-channels: Number of dma channels in child node.
86
-
87
-
Example:
88
-
++++++++
89
-
90
-
axi_vdma_0: axivdma@40030000 {
91
-
compatible = "xlnx,axi-vdma-1.00.a";
92
-
#dma_cells = <1>;
93
-
reg = < 0x40030000 0x10000 >;
94
-
dma-ranges = <0x00000000 0x00000000 0x40000000>;
95
-
xlnx,num-fstores = <0x8>;
96
-
xlnx,flush-fsync = <0x1>;
97
-
xlnx,addrwidth = <0x20>;
98
-
clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
99
-
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
100
-
"m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
101
-
dma-channel@40030000 {
102
-
compatible = "xlnx,axi-vdma-mm2s-channel";
103
-
interrupts = < 0 54 4 >;
104
-
xlnx,datawidth = <0x40>;
105
-
} ;
106
-
dma-channel@40030030 {
107
-
compatible = "xlnx,axi-vdma-s2mm-channel";
108
-
interrupts = < 0 53 4 >;
109
-
xlnx,datawidth = <0x40>;
110
-
} ;
111
-
} ;
+299
Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml
+299
Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/xilinx/xlnx,axi-dma.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Xilinx AXI VDMA, DMA, CDMA and MCDMA IP
8
+
9
+
maintainers:
10
+
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
11
+
- Abin Joseph <abin.joseph@amd.com>
12
+
13
+
description: >
14
+
Xilinx AXI VDMA engine, it does transfers between memory and video devices.
15
+
It can be configured to have one channel or two channels. If configured
16
+
as two channels, one is to transmit to the video device and another is
17
+
to receive from the video device.
18
+
19
+
Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
20
+
target devices. It can be configured to have one channel or two channels.
21
+
If configured as two channels, one is to transmit to the device and another
22
+
is to receive from the device.
23
+
24
+
Xilinx AXI CDMA engine, it does transfers between memory-mapped source
25
+
address and a memory-mapped destination address.
26
+
27
+
Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
28
+
target devices. It can be configured to have up to 16 independent transmit
29
+
and receive channels.
30
+
31
+
properties:
32
+
compatible:
33
+
enum:
34
+
- xlnx,axi-cdma-1.00.a
35
+
- xlnx,axi-dma-1.00.a
36
+
- xlnx,axi-mcdma-1.00.a
37
+
- xlnx,axi-vdma-1.00.a
38
+
39
+
reg:
40
+
maxItems: 1
41
+
42
+
"#dma-cells":
43
+
const: 1
44
+
45
+
"#address-cells":
46
+
const: 1
47
+
48
+
"#size-cells":
49
+
const: 1
50
+
51
+
interrupts:
52
+
items:
53
+
- description: Interrupt for single channel (MM2S or S2MM)
54
+
- description: Interrupt for dual channel configuration
55
+
minItems: 1
56
+
description:
57
+
Interrupt lines for the DMA controller. Only used when
58
+
xlnx,axistream-connected is present (DMA connected to AXI Stream
59
+
IP). When child dma-channel nodes are present, interrupts are
60
+
specified in the child nodes instead.
61
+
62
+
clocks:
63
+
minItems: 1
64
+
maxItems: 5
65
+
66
+
clock-names:
67
+
minItems: 1
68
+
maxItems: 5
69
+
70
+
dma-ranges: true
71
+
72
+
xlnx,addrwidth:
73
+
$ref: /schemas/types.yaml#/definitions/uint32
74
+
enum: [32, 64]
75
+
description: The DMA addressing size in bits.
76
+
77
+
xlnx,num-fstores:
78
+
$ref: /schemas/types.yaml#/definitions/uint32
79
+
minimum: 1
80
+
maximum: 32
81
+
description: Should be the number of framebuffers as configured in h/w.
82
+
83
+
xlnx,flush-fsync:
84
+
type: boolean
85
+
description: Tells which channel to Flush on Frame sync.
86
+
87
+
xlnx,sg-length-width:
88
+
$ref: /schemas/types.yaml#/definitions/uint32
89
+
minimum: 8
90
+
maximum: 26
91
+
default: 23
92
+
description:
93
+
Width in bits of the length register as configured in hardware.
94
+
95
+
xlnx,irq-delay:
96
+
$ref: /schemas/types.yaml#/definitions/uint32
97
+
minimum: 0
98
+
maximum: 255
99
+
description:
100
+
Tells the interrupt delay timeout value. Valid range is from 0-255.
101
+
Setting this value to zero disables the delay timer interrupt.
102
+
1 timeout interval = 125 * clock period of SG clock.
103
+
104
+
xlnx,axistream-connected:
105
+
type: boolean
106
+
description: Tells whether DMA is connected to AXI stream IP.
107
+
108
+
patternProperties:
109
+
"^dma-channel(-mm2s|-s2mm)?$":
110
+
type: object
111
+
description:
112
+
Should have at least one channel and can have up to two channels per
113
+
device. This node specifies the properties of each DMA channel.
114
+
115
+
properties:
116
+
compatible:
117
+
enum:
118
+
- xlnx,axi-vdma-mm2s-channel
119
+
- xlnx,axi-vdma-s2mm-channel
120
+
- xlnx,axi-cdma-channel
121
+
- xlnx,axi-dma-mm2s-channel
122
+
- xlnx,axi-dma-s2mm-channel
123
+
124
+
interrupts:
125
+
maxItems: 1
126
+
127
+
xlnx,datawidth:
128
+
$ref: /schemas/types.yaml#/definitions/uint32
129
+
enum: [32, 64, 128, 256, 512, 1024]
130
+
description: Should contain the stream data width, take values {32,64...1024}.
131
+
132
+
xlnx,include-dre:
133
+
type: boolean
134
+
description: Tells hardware is configured for Data Realignment Engine.
135
+
136
+
xlnx,genlock-mode:
137
+
type: boolean
138
+
description: Tells Genlock synchronization is enabled/disabled in hardware.
139
+
140
+
xlnx,enable-vert-flip:
141
+
type: boolean
142
+
description:
143
+
Tells vertical flip is enabled/disabled in hardware(S2MM path).
144
+
145
+
dma-channels:
146
+
$ref: /schemas/types.yaml#/definitions/uint32
147
+
description: Number of dma channels in child node.
148
+
149
+
required:
150
+
- compatible
151
+
- interrupts
152
+
- xlnx,datawidth
153
+
154
+
additionalProperties: false
155
+
156
+
allOf:
157
+
- $ref: ../dma-controller.yaml#
158
+
159
+
- if:
160
+
properties:
161
+
compatible:
162
+
contains:
163
+
const: xlnx,axi-vdma-1.00.a
164
+
then:
165
+
properties:
166
+
clock-names:
167
+
items:
168
+
- const: s_axi_lite_aclk
169
+
- const: m_axi_mm2s_aclk
170
+
- const: m_axi_s2mm_aclk
171
+
- const: m_axis_mm2s_aclk
172
+
- const: s_axis_s2mm_aclk
173
+
minItems: 1
174
+
interrupts: false
175
+
patternProperties:
176
+
"^dma-channel(-mm2s|-s2mm)?$":
177
+
properties:
178
+
compatible:
179
+
enum:
180
+
- xlnx,axi-vdma-mm2s-channel
181
+
- xlnx,axi-vdma-s2mm-channel
182
+
required:
183
+
- xlnx,num-fstores
184
+
185
+
- if:
186
+
properties:
187
+
compatible:
188
+
contains:
189
+
const: xlnx,axi-cdma-1.00.a
190
+
then:
191
+
properties:
192
+
clock-names:
193
+
items:
194
+
- const: s_axi_lite_aclk
195
+
- const: m_axi_aclk
196
+
interrupts: false
197
+
patternProperties:
198
+
"^dma-channel(-mm2s|-s2mm)?$":
199
+
properties:
200
+
compatible:
201
+
enum:
202
+
- xlnx,axi-cdma-channel
203
+
204
+
- if:
205
+
properties:
206
+
compatible:
207
+
contains:
208
+
enum:
209
+
- xlnx,axi-dma-1.00.a
210
+
- xlnx,axi-mcdma-1.00.a
211
+
then:
212
+
properties:
213
+
clock-names:
214
+
items:
215
+
- const: s_axi_lite_aclk
216
+
- const: m_axi_mm2s_aclk
217
+
- const: m_axi_s2mm_aclk
218
+
- const: m_axi_sg_aclk
219
+
minItems: 1
220
+
patternProperties:
221
+
"^dma-channel(-mm2s|-s2mm)?(@[0-9a-f]+)?$":
222
+
properties:
223
+
compatible:
224
+
enum:
225
+
- xlnx,axi-dma-mm2s-channel
226
+
- xlnx,axi-dma-s2mm-channel
227
+
228
+
required:
229
+
- "#dma-cells"
230
+
- reg
231
+
- xlnx,addrwidth
232
+
- dma-ranges
233
+
- clocks
234
+
- clock-names
235
+
236
+
unevaluatedProperties: false
237
+
238
+
examples:
239
+
- |
240
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
241
+
242
+
dma-controller@40030000 {
243
+
compatible = "xlnx,axi-vdma-1.00.a";
244
+
reg = <0x40030000 0x10000>;
245
+
#dma-cells = <1>;
246
+
#address-cells = <1>;
247
+
#size-cells = <1>;
248
+
dma-ranges = <0x0 0x0 0x40000000>;
249
+
clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
250
+
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk",
251
+
"m_axi_s2mm_aclk", "m_axis_mm2s_aclk",
252
+
"s_axis_s2mm_aclk";
253
+
xlnx,num-fstores = <8>;
254
+
xlnx,flush-fsync;
255
+
xlnx,addrwidth = <32>;
256
+
257
+
dma-channel-mm2s {
258
+
compatible = "xlnx,axi-vdma-mm2s-channel";
259
+
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
260
+
xlnx,datawidth = <64>;
261
+
};
262
+
263
+
dma-channel-s2mm {
264
+
compatible = "xlnx,axi-vdma-s2mm-channel";
265
+
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
266
+
xlnx,datawidth = <64>;
267
+
};
268
+
};
269
+
270
+
- |
271
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
272
+
273
+
dma-controller@a4030000 {
274
+
compatible = "xlnx,axi-dma-1.00.a";
275
+
reg = <0xa4030000 0x10000>;
276
+
#dma-cells = <1>;
277
+
#address-cells = <1>;
278
+
#size-cells = <1>;
279
+
dma-ranges = <0x0 0x0 0x40000000>;
280
+
clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>;
281
+
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk",
282
+
"m_axi_s2mm_aclk", "m_axi_sg_aclk";
283
+
xlnx,addrwidth = <32>;
284
+
xlnx,sg-length-width = <14>;
285
+
286
+
dma-channel-mm2s {
287
+
compatible = "xlnx,axi-dma-mm2s-channel";
288
+
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
289
+
xlnx,datawidth = <64>;
290
+
xlnx,include-dre;
291
+
};
292
+
293
+
dma-channel-s2mm {
294
+
compatible = "xlnx,axi-dma-s2mm-channel";
295
+
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
296
+
xlnx,datawidth = <64>;
297
+
xlnx,include-dre;
298
+
};
299
+
};