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Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq updates from Thomas Gleixner:
"A small set of updates mostly for irq chip drivers:

- MIPS GIC fix for spurious, masked interrupts

- fix for a subtle IPI bug in GICv3

- do not probe GICv3 ITSs that are marked as disabled

- multi-MSI support for GICv2m

- various small cleanups"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqdomain: Re-use DEFINE_SHOW_ATTRIBUTE() macro
irqchip/bcm: Remove hashed address printing
irqchip/gic-v2m: Add PCI Multi-MSI support
irqchip/gic-v3: Ignore disabled ITS nodes
irqchip/gic-v3: Use wmb() instead of smb_wmb() in gic_raise_softirq()
irqchip/gic-v3: Change pr_debug message to pr_devel
irqchip/mips-gic: Avoid spuriously handling masked interrupts

+36 -51
-3
drivers/irqchip/irq-bcm7038-l1.c
··· 339 339 goto out_unmap; 340 340 } 341 341 342 - pr_info("registered BCM7038 L1 intc (mem: 0x%p, IRQs: %d)\n", 343 - intc->cpus[0]->map_base, IRQS_PER_WORD * intc->n_words); 344 - 345 342 return 0; 346 343 347 344 out_unmap:
-3
drivers/irqchip/irq-bcm7120-l2.c
··· 318 318 } 319 319 } 320 320 321 - pr_info("registered %s intc (mem: 0x%p, parent IRQ(s): %d)\n", 322 - intc_name, data->map_base[0], data->num_parent_irqs); 323 - 324 321 return 0; 325 322 326 323 out_free_domain:
-3
drivers/irqchip/irq-brcmstb-l2.c
··· 262 262 ct->chip.irq_set_wake = irq_gc_set_wake; 263 263 } 264 264 265 - pr_info("registered L2 intc (mem: 0x%p, parent irq: %d)\n", 266 - base, parent_irq); 267 - 268 265 return 0; 269 266 270 267 out_free_domain:
+22 -24
drivers/irqchip/irq-gic-v2m.c
··· 94 94 95 95 static struct msi_domain_info gicv2m_msi_domain_info = { 96 96 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 97 - MSI_FLAG_PCI_MSIX), 97 + MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), 98 98 .chip = &gicv2m_msi_irq_chip, 99 99 }; 100 100 ··· 155 155 return 0; 156 156 } 157 157 158 - static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq) 158 + static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq, 159 + int nr_irqs) 159 160 { 160 - int pos; 161 - 162 - pos = hwirq - v2m->spi_start; 163 - if (pos < 0 || pos >= v2m->nr_spis) { 164 - pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq); 165 - return; 166 - } 167 - 168 161 spin_lock(&v2m_lock); 169 - __clear_bit(pos, v2m->bm); 162 + bitmap_release_region(v2m->bm, hwirq - v2m->spi_start, 163 + get_count_order(nr_irqs)); 170 164 spin_unlock(&v2m_lock); 171 165 } 172 166 ··· 168 174 unsigned int nr_irqs, void *args) 169 175 { 170 176 struct v2m_data *v2m = NULL, *tmp; 171 - int hwirq, offset, err = 0; 177 + int hwirq, offset, i, err = 0; 172 178 173 179 spin_lock(&v2m_lock); 174 180 list_for_each_entry(tmp, &v2m_nodes, entry) { 175 - offset = find_first_zero_bit(tmp->bm, tmp->nr_spis); 176 - if (offset < tmp->nr_spis) { 177 - __set_bit(offset, tmp->bm); 181 + offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis, 182 + get_count_order(nr_irqs)); 183 + if (offset >= 0) { 178 184 v2m = tmp; 179 185 break; 180 186 } ··· 186 192 187 193 hwirq = v2m->spi_start + offset; 188 194 189 - err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq); 190 - if (err) { 191 - gicv2m_unalloc_msi(v2m, hwirq); 192 - return err; 195 + for (i = 0; i < nr_irqs; i++) { 196 + err = gicv2m_irq_gic_domain_alloc(domain, virq + i, hwirq + i); 197 + if (err) 198 + goto fail; 199 + 200 + irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 201 + &gicv2m_irq_chip, v2m); 193 202 } 194 203 195 - irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 196 - &gicv2m_irq_chip, v2m); 197 - 198 204 return 0; 205 + 206 + fail: 207 + irq_domain_free_irqs_parent(domain, virq, nr_irqs); 208 + gicv2m_unalloc_msi(v2m, hwirq, get_count_order(nr_irqs)); 209 + return err; 199 210 } 200 211 201 212 static void gicv2m_irq_domain_free(struct irq_domain *domain, ··· 209 210 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 210 211 struct v2m_data *v2m = irq_data_get_irq_chip_data(d); 211 212 212 - BUG_ON(nr_irqs != 1); 213 - gicv2m_unalloc_msi(v2m, d->hwirq); 213 + gicv2m_unalloc_msi(v2m, d->hwirq, nr_irqs); 214 214 irq_domain_free_irqs_parent(domain, virq, nr_irqs); 215 215 } 216 216
+2
drivers/irqchip/irq-gic-v3-its-pci-msi.c
··· 132 132 133 133 for (np = of_find_matching_node(NULL, its_device_id); np; 134 134 np = of_find_matching_node(np, its_device_id)) { 135 + if (!of_device_is_available(np)) 136 + continue; 135 137 if (!of_property_read_bool(np, "msi-controller")) 136 138 continue; 137 139
+2
drivers/irqchip/irq-gic-v3-its-platform-msi.c
··· 154 154 155 155 for (np = of_find_matching_node(NULL, its_device_id); np; 156 156 np = of_find_matching_node(np, its_device_id)) { 157 + if (!of_device_is_available(np)) 158 + continue; 157 159 if (!of_property_read_bool(np, "msi-controller")) 158 160 continue; 159 161
+2
drivers/irqchip/irq-gic-v3-its.c
··· 3314 3314 3315 3315 for (np = of_find_matching_node(node, its_device_id); np; 3316 3316 np = of_find_matching_node(np, its_device_id)) { 3317 + if (!of_device_is_available(np)) 3318 + continue; 3317 3319 if (!of_property_read_bool(np, "msi-controller")) { 3318 3320 pr_warn("%pOF: no msi-controller property, ITS ignored\n", 3319 3321 np);
+2 -2
drivers/irqchip/irq-gic-v3.c
··· 673 673 MPIDR_TO_SGI_RS(cluster_id) | 674 674 tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 675 675 676 - pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 676 + pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 677 677 gic_write_sgi1r(val); 678 678 } 679 679 ··· 688 688 * Ensure that stores to Normal memory are visible to the 689 689 * other CPUs before issuing the IPI. 690 690 */ 691 - smp_wmb(); 691 + wmb(); 692 692 693 693 for_each_cpu(cpu, mask) { 694 694 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
-2
drivers/irqchip/irq-mips-gic.c
··· 424 424 spin_lock_irqsave(&gic_lock, flags); 425 425 write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); 426 426 write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); 427 - gic_clear_pcpu_masks(intr); 428 - set_bit(intr, per_cpu_ptr(pcpu_masks, cpu)); 429 427 irq_data_update_effective_affinity(data, cpumask_of(cpu)); 430 428 spin_unlock_irqrestore(&gic_lock, flags); 431 429
+2
drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
··· 73 73 74 74 for (np = of_find_matching_node(NULL, its_device_id); np; 75 75 np = of_find_matching_node(np, its_device_id)) { 76 + if (!of_device_is_available(np)) 77 + continue; 76 78 if (!of_property_read_bool(np, "msi-controller")) 77 79 continue; 78 80
+4 -14
kernel/irq/irqdomain.c
··· 1726 1726 irq_domain_debug_show_one(m, d, 0); 1727 1727 return 0; 1728 1728 } 1729 - 1730 - static int irq_domain_debug_open(struct inode *inode, struct file *file) 1731 - { 1732 - return single_open(file, irq_domain_debug_show, inode->i_private); 1733 - } 1734 - 1735 - static const struct file_operations dfs_domain_ops = { 1736 - .open = irq_domain_debug_open, 1737 - .read = seq_read, 1738 - .llseek = seq_lseek, 1739 - .release = single_release, 1740 - }; 1729 + DEFINE_SHOW_ATTRIBUTE(irq_domain_debug); 1741 1730 1742 1731 static void debugfs_add_domain_dir(struct irq_domain *d) 1743 1732 { 1744 1733 if (!d->name || !domain_dir || d->debugfs_file) 1745 1734 return; 1746 1735 d->debugfs_file = debugfs_create_file(d->name, 0444, domain_dir, d, 1747 - &dfs_domain_ops); 1736 + &irq_domain_debug_fops); 1748 1737 } 1749 1738 1750 1739 static void debugfs_remove_domain_dir(struct irq_domain *d) ··· 1749 1760 if (!domain_dir) 1750 1761 return; 1751 1762 1752 - debugfs_create_file("default", 0444, domain_dir, NULL, &dfs_domain_ops); 1763 + debugfs_create_file("default", 0444, domain_dir, NULL, 1764 + &irq_domain_debug_fops); 1753 1765 mutex_lock(&irq_domain_mutex); 1754 1766 list_for_each_entry(d, &irq_domain_list, link) 1755 1767 debugfs_add_domain_dir(d);