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ASoC: dt-bindings: fsl,ssi: Convert to YAML

Convert the fsl,ssi binding to YAML.

Add below compatible strings which were not listed
in document:

fsl,imx50-ssi
fsl,imx53-ssi
fsl,imx25-ssi
fsl,imx27-ssi
fsl,imx6q-ssi
fsl,imx6sl-ssi
fsl,imx6sx-ssi

Add below fsl,mode strings which were not listed.

i2s-slave
i2s-master
lj-slave
lj-master
rj-slave
rj-master

Add 'ac97-gpios' property which were not listed.
Then dtbs_check can pass.

And remove the 'codec' description which should be
in the 'codec' binding doc.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/1714026906-16723-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Shengjiu Wang and committed by
Mark Brown
2da01ca3 466c8c46

+194 -87
-87
Documentation/devicetree/bindings/sound/fsl,ssi.txt
··· 1 - Freescale Synchronous Serial Interface 2 - 3 - The SSI is a serial device that communicates with audio codecs. It can 4 - be programmed in AC97, I2S, left-justified, or right-justified modes. 5 - 6 - Required properties: 7 - - compatible: Compatible list, should contain one of the following 8 - compatibles: 9 - fsl,mpc8610-ssi 10 - fsl,imx51-ssi 11 - fsl,imx35-ssi 12 - fsl,imx21-ssi 13 - - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on. 14 - - reg: Offset and length of the register set for the device. 15 - - interrupts: <a b> where a is the interrupt number and b is a 16 - field that represents an encoding of the sense and 17 - level information for the interrupt. This should be 18 - encoded based on the information in section 2) 19 - depending on the type of interrupt controller you 20 - have. 21 - - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs. 22 - This number is the maximum allowed value for SFCSR[TFWM0]. 23 - - clocks: "ipg" - Required clock for the SSI unit 24 - "baud" - Required clock for SSI master mode. Otherwise this 25 - clock is not used 26 - 27 - Required are also ac97 link bindings if ac97 is used. See 28 - Documentation/devicetree/bindings/sound/soc-ac97link.txt for the necessary 29 - bindings. 30 - 31 - Optional properties: 32 - - codec-handle: Phandle to a 'codec' node that defines an audio 33 - codec connected to this SSI. This node is typically 34 - a child of an I2C or other control node. 35 - - fsl,fiq-stream-filter: Bool property. Disabled DMA and use FIQ instead to 36 - filter the codec stream. This is necessary for some boards 37 - where an incompatible codec is connected to this SSI, e.g. 38 - on pca100 and pcm043. 39 - - dmas: Generic dma devicetree binding as described in 40 - Documentation/devicetree/bindings/dma/dma.txt. 41 - - dma-names: Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq 42 - is not defined. 43 - - fsl,mode: The operating mode for the AC97 interface only. 44 - "ac97-slave" - AC97 mode, SSI is clock slave 45 - "ac97-master" - AC97 mode, SSI is clock master 46 - - fsl,ssi-asynchronous: 47 - If specified, the SSI is to be programmed in asynchronous 48 - mode. In this mode, pins SRCK, STCK, SRFS, and STFS must 49 - all be connected to valid signals. In synchronous mode, 50 - SRCK and SRFS are ignored. Asynchronous mode allows 51 - playback and capture to use different sample sizes and 52 - sample rates. Some drivers may require that SRCK and STCK 53 - be connected together, and SRFS and STFS be connected 54 - together. This would still allow different sample sizes, 55 - but not different sample rates. 56 - - fsl,playback-dma: Phandle to a node for the DMA channel to use for 57 - playback of audio. This is typically dictated by SOC 58 - design. See the notes below. 59 - Only used on Power Architecture. 60 - - fsl,capture-dma: Phandle to a node for the DMA channel to use for 61 - capture (recording) of audio. This is typically dictated 62 - by SOC design. See the notes below. 63 - Only used on Power Architecture. 64 - 65 - Child 'codec' node required properties: 66 - - compatible: Compatible list, contains the name of the codec 67 - 68 - Child 'codec' node optional properties: 69 - - clock-frequency: The frequency of the input clock, which typically comes 70 - from an on-board dedicated oscillator. 71 - 72 - Notes on fsl,playback-dma and fsl,capture-dma: 73 - 74 - On SOCs that have an SSI, specific DMA channels are hard-wired for playback 75 - and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for 76 - playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for 77 - playback and DMA channel 3 for capture. The developer can choose which 78 - DMA controller to use, but the channels themselves are hard-wired. The 79 - purpose of these two properties is to represent this hardware design. 80 - 81 - The device tree nodes for the DMA channels that are referenced by 82 - "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with 83 - "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g. 84 - "fsl,mpc8610-dma-channel") can remain. If these nodes are left as 85 - "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA 86 - drivers (fsldma) will attempt to use them, and it will conflict with the 87 - sound drivers.
+194
Documentation/devicetree/bindings/sound/fsl,ssi.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/sound/fsl,ssi.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale Synchronous Serial Interface 8 + 9 + maintainers: 10 + - Shengjiu Wang <shengjiu.wang@nxp.com> 11 + 12 + description: 13 + Notes on fsl,playback-dma and fsl,capture-dma 14 + On SOCs that have an SSI, specific DMA channels are hard-wired for playback 15 + and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for 16 + playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for 17 + playback and DMA channel 3 for capture. The developer can choose which 18 + DMA controller to use, but the channels themselves are hard-wired. The 19 + purpose of these two properties is to represent this hardware design. 20 + 21 + The device tree nodes for the DMA channels that are referenced by 22 + "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with 23 + "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g. 24 + "fsl,mpc8610-dma-channel") can remain. If these nodes are left as 25 + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA 26 + drivers (fsldma) will attempt to use them, and it will conflict with the 27 + sound drivers. 28 + 29 + properties: 30 + compatible: 31 + oneOf: 32 + - items: 33 + - enum: 34 + - fsl,imx50-ssi 35 + - fsl,imx53-ssi 36 + - const: fsl,imx51-ssi 37 + - const: fsl,imx21-ssi 38 + - items: 39 + - enum: 40 + - fsl,imx25-ssi 41 + - fsl,imx27-ssi 42 + - fsl,imx35-ssi 43 + - fsl,imx51-ssi 44 + - const: fsl,imx21-ssi 45 + - items: 46 + - enum: 47 + - fsl,imx6q-ssi 48 + - fsl,imx6sl-ssi 49 + - fsl,imx6sx-ssi 50 + - const: fsl,imx51-ssi 51 + - items: 52 + - const: fsl,imx21-ssi 53 + - items: 54 + - const: fsl,mpc8610-ssi 55 + 56 + reg: 57 + maxItems: 1 58 + 59 + interrupts: 60 + maxItems: 1 61 + 62 + clocks: 63 + items: 64 + - description: The ipg clock for register access 65 + - description: clock for SSI master mode 66 + minItems: 1 67 + 68 + clock-names: 69 + items: 70 + - const: ipg 71 + - const: baud 72 + minItems: 1 73 + 74 + dmas: 75 + oneOf: 76 + - items: 77 + - description: DMA controller phandle and request line for RX 78 + - description: DMA controller phandle and request line for TX 79 + - items: 80 + - description: DMA controller phandle and request line for RX0 81 + - description: DMA controller phandle and request line for TX0 82 + - description: DMA controller phandle and request line for RX1 83 + - description: DMA controller phandle and request line for TX1 84 + 85 + dma-names: 86 + oneOf: 87 + - items: 88 + - const: rx 89 + - const: tx 90 + - items: 91 + - const: rx0 92 + - const: tx0 93 + - const: rx1 94 + - const: tx1 95 + 96 + "#sound-dai-cells": 97 + const: 0 98 + description: optional, some dts node didn't add it. 99 + 100 + cell-index: 101 + $ref: /schemas/types.yaml#/definitions/uint32 102 + enum: [0, 1, 2] 103 + description: The SSI index 104 + 105 + ac97-gpios: 106 + $ref: /schemas/types.yaml#/definitions/phandle-array 107 + description: Please refer to soc-ac97link.txt 108 + 109 + codec-handle: 110 + $ref: /schemas/types.yaml#/definitions/phandle 111 + description: 112 + Phandle to a 'codec' node that defines an audio 113 + codec connected to this SSI. This node is typically 114 + a child of an I2C or other control node. 115 + 116 + fsl,fifo-depth: 117 + $ref: /schemas/types.yaml#/definitions/uint32 118 + description: 119 + The number of elements in the transmit and receive FIFOs. 120 + This number is the maximum allowed value for SFCSR[TFWM0]. 121 + enum: [8, 15] 122 + 123 + fsl,fiq-stream-filter: 124 + type: boolean 125 + description: 126 + Disabled DMA and use FIQ instead to filter the codec stream. 127 + This is necessary for some boards where an incompatible codec 128 + is connected to this SSI, e.g. on pca100 and pcm043. 129 + 130 + fsl,mode: 131 + $ref: /schemas/types.yaml#/definitions/string 132 + enum: [ ac97-slave, ac97-master, i2s-slave, i2s-master, 133 + lj-slave, lj-master, rj-slave, rj-master ] 134 + description: | 135 + "ac97-slave" - AC97 mode, SSI is clock slave 136 + "ac97-master" - AC97 mode, SSI is clock master 137 + "i2s-slave" - I2S mode, SSI is clock slave 138 + "i2s-master" - I2S mode, SSI is clock master 139 + "lj-slave" - Left justified mode, SSI is clock slave 140 + "lj-master" - Left justified mode, SSI is clock master 141 + "rj-slave" - Right justified mode, SSI is clock slave 142 + "rj-master" - Right justified mode, SSI is clock master 143 + 144 + fsl,ssi-asynchronous: 145 + type: boolean 146 + description: If specified, the SSI is to be programmed in asynchronous 147 + mode. In this mode, pins SRCK, STCK, SRFS, and STFS must 148 + all be connected to valid signals. In synchronous mode, 149 + SRCK and SRFS are ignored. Asynchronous mode allows 150 + playback and capture to use different sample sizes and 151 + sample rates. Some drivers may require that SRCK and STCK 152 + be connected together, and SRFS and STFS be connected 153 + together. This would still allow different sample sizes, 154 + but not different sample rates. 155 + 156 + fsl,playback-dma: 157 + $ref: /schemas/types.yaml#/definitions/phandle 158 + description: Phandle to a node for the DMA channel to use for 159 + playback of audio. This is typically dictated by SOC 160 + design. Only used on Power Architecture. 161 + 162 + fsl,capture-dma: 163 + $ref: /schemas/types.yaml#/definitions/phandle 164 + description: Phandle to a node for the DMA channel to use for 165 + capture (recording) of audio. This is typically dictated 166 + by SOC design. Only used on Power Architecture. 167 + 168 + required: 169 + - compatible 170 + - reg 171 + - interrupts 172 + - fsl,fifo-depth 173 + 174 + allOf: 175 + - $ref: dai-common.yaml# 176 + 177 + unevaluatedProperties: false 178 + 179 + examples: 180 + - | 181 + #include <dt-bindings/interrupt-controller/arm-gic.h> 182 + #include <dt-bindings/clock/imx6qdl-clock.h> 183 + ssi@2028000 { 184 + compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi"; 185 + reg = <0x02028000 0x4000>; 186 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 187 + clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, 188 + <&clks IMX6QDL_CLK_SSI1>; 189 + clock-names = "ipg", "baud"; 190 + dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; 191 + dma-names = "rx", "tx"; 192 + #sound-dai-cells = <0>; 193 + fsl,fifo-depth = <15>; 194 + };