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drm/i915: move DDI_CLK_VALFREQ next to other Cx0 PHY registers

Relocate DDI_CLK_VALFREQ register definition next to other Cx0 PHY
register macros.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241213115111.335474-3-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

+5 -5
+5
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
··· 9 9 #include "i915_reg_defs.h" 10 10 #include "intel_display_limits.h" 11 11 12 + /* DDI Buffer Control */ 13 + #define _DDI_CLK_VALFREQ_A 0x64030 14 + #define _DDI_CLK_VALFREQ_B 0x64130 15 + #define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B) 16 + 12 17 /* 13 18 * Wrapper macro to convert from port number to the index used in some of the 14 19 * registers. For Display version 20 and above it converts the port number to a
-5
drivers/gpu/drm/i915/i915_reg.h
··· 1067 1067 #define CLKGATE_DIS_PSL_EXT(pipe) \ 1068 1068 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B) 1069 1069 1070 - /* DDI Buffer Control */ 1071 - #define _DDI_CLK_VALFREQ_A 0x64030 1072 - #define _DDI_CLK_VALFREQ_B 0x64130 1073 - #define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B) 1074 - 1075 1070 /* 1076 1071 * Display engine regs 1077 1072 */