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clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150

Add the PCIe0 and PCIe1 GDSC defines & driver structures for SM8150.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220302203045.184500-4-bhupesh.sharma@linaro.org

authored by

Bhupesh Sharma and committed by
Bjorn Andersson
2dc63e76 b527358c

+22
+20
drivers/clk/qcom/gcc-sm8150.c
··· 3448 3448 }, 3449 3449 }; 3450 3450 3451 + static struct gdsc pcie_0_gdsc = { 3452 + .gdscr = 0x6b004, 3453 + .pd = { 3454 + .name = "pcie_0_gdsc", 3455 + }, 3456 + .pwrsts = PWRSTS_OFF_ON, 3457 + .flags = POLL_CFG_GDSCR, 3458 + }; 3459 + 3460 + static struct gdsc pcie_1_gdsc = { 3461 + .gdscr = 0x8d004, 3462 + .pd = { 3463 + .name = "pcie_1_gdsc", 3464 + }, 3465 + .pwrsts = PWRSTS_OFF_ON, 3466 + .flags = POLL_CFG_GDSCR, 3467 + }; 3468 + 3451 3469 static struct gdsc usb30_prim_gdsc = { 3452 3470 .gdscr = 0xf004, 3453 3471 .pd = { ··· 3732 3714 }; 3733 3715 3734 3716 static struct gdsc *gcc_sm8150_gdscs[] = { 3717 + [PCIE_0_GDSC] = &pcie_0_gdsc, 3718 + [PCIE_1_GDSC] = &pcie_1_gdsc, 3735 3719 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3736 3720 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 3737 3721 };
+2
include/dt-bindings/clock/qcom,gcc-sm8150.h
··· 241 241 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 242 242 243 243 /* GCC GDSCRs */ 244 + #define PCIE_0_GDSC 0 245 + #define PCIE_1_GDSC 1 244 246 #define USB30_PRIM_GDSC 4 245 247 #define USB30_SEC_GDSC 5 246 248