Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/cx0: Add MTL+ .dump_hw_state hook
Add .dump_hw_state function pointer for MTL+ platforms
to support dpll framework. While at it, switch to use
drm_printer structure to print hw state information.
v2: Keep debug messages on one line if they not
necessarily needed to split into two or more
lines (Suraj)
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-24-mika.kahola@intel.com
+45
-40
+34
-36
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+34
-36
drivers/gpu/drm/i915/display/intel_cx0_phy.c
···
2297
2297
intel_c10_msgbus_access_commit(encoder, INTEL_CX0_LANE0, true);
2298
2298
}
2299
2299
2300
-
static void intel_c10pll_dump_hw_state(struct intel_display *display,
2300
+
static void intel_c10pll_dump_hw_state(struct drm_printer *p,
2301
2301
const struct intel_c10pll_state *hw_state)
2302
2302
{
2303
2303
bool fracen;
···
2306
2306
unsigned int multiplier, tx_clk_div;
2307
2307
2308
2308
fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
2309
-
drm_dbg_kms(display->drm, "c10pll_hw_state: clock: %d, fracen: %s, ",
2310
-
hw_state->clock, str_yes_no(fracen));
2309
+
drm_printf(p, "c10pll_hw_state: clock: %d, fracen: %s, ",
2310
+
hw_state->clock, str_yes_no(fracen));
2311
2311
2312
2312
if (fracen) {
2313
2313
frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
2314
2314
frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13];
2315
2315
frac_den = hw_state->pll[10] << 8 | hw_state->pll[9];
2316
-
drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n",
2317
-
frac_quot, frac_rem, frac_den);
2316
+
drm_printf(p, "quot: %u, rem: %u, den: %u,\n",
2317
+
frac_quot, frac_rem, frac_den);
2318
2318
}
2319
2319
2320
2320
multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |
2321
2321
hw_state->pll[2]) / 2 + 16;
2322
2322
tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);
2323
-
drm_dbg_kms(display->drm,
2324
-
"multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
2323
+
drm_printf(p,
2324
+
"multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
2325
2325
2326
-
drm_dbg_kms(display->drm, "c10pll_rawhw_state:");
2327
-
drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,
2328
-
hw_state->cmn);
2326
+
drm_printf(p, "c10pll_rawhw_state:");
2327
+
drm_printf(p, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn);
2329
2328
2330
2329
BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4);
2331
2330
for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
2332
-
drm_dbg_kms(display->drm,
2333
-
"pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
2334
-
i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
2335
-
i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
2331
+
drm_printf(p,
2332
+
"pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
2333
+
i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
2334
+
i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
2336
2335
}
2337
2336
2338
2337
/*
···
2812
2813
cx0pll_state->ssc_enabled = readout_ssc_state(encoder, intel_c20phy_use_mpllb(pll_state));
2813
2814
}
2814
2815
2815
-
static void intel_c20pll_dump_hw_state(struct intel_display *display,
2816
+
static void intel_c20pll_dump_hw_state(struct drm_printer *p,
2816
2817
const struct intel_c20pll_state *hw_state)
2817
2818
{
2818
2819
int i;
2819
2820
2820
-
drm_dbg_kms(display->drm, "c20pll_hw_state clock: %d:\n", hw_state->clock);
2821
-
drm_dbg_kms(display->drm,
2822
-
"tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
2823
-
hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
2824
-
drm_dbg_kms(display->drm,
2825
-
"cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
2826
-
hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
2821
+
drm_printf(p, "c20pll_hw_state: clock: %d\n", hw_state->clock);
2822
+
drm_printf(p,
2823
+
"tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
2824
+
hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
2825
+
drm_printf(p,
2826
+
"cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
2827
+
hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
2827
2828
2828
2829
if (intel_c20phy_use_mpllb(hw_state)) {
2829
2830
for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
2830
-
drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i,
2831
-
hw_state->mpllb[i]);
2831
+
drm_printf(p, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
2832
2832
} else {
2833
2833
for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
2834
-
drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
2835
-
hw_state->mplla[i]);
2834
+
drm_printf(p, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]);
2836
2835
2837
2836
/* For full coverage, also print the additional PLL B entry. */
2838
2837
BUILD_BUG_ON(ARRAY_SIZE(hw_state->mplla) + 1 != ARRAY_SIZE(hw_state->mpllb));
2839
-
drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
2838
+
drm_printf(p, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
2840
2839
}
2841
2840
2842
-
drm_dbg_kms(display->drm, "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n",
2843
-
hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate);
2841
+
drm_printf(p,
2842
+
"vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n",
2843
+
hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate);
2844
2844
}
2845
2845
2846
-
void intel_cx0pll_dump_hw_state(struct intel_display *display,
2846
+
void intel_cx0pll_dump_hw_state(struct drm_printer *p,
2847
2847
const struct intel_cx0pll_state *hw_state)
2848
2848
{
2849
-
drm_dbg_kms(display->drm,
2850
-
"cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n",
2851
-
hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
2852
-
str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode));
2849
+
drm_printf(p,
2850
+
"cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n",
2851
+
hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
2852
+
str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode));
2853
2853
2854
2854
if (hw_state->use_c10)
2855
-
intel_c10pll_dump_hw_state(display, &hw_state->c10);
2855
+
intel_c10pll_dump_hw_state(p, &hw_state->c10);
2856
2856
else
2857
-
intel_c20pll_dump_hw_state(display, &hw_state->c20);
2857
+
intel_c20pll_dump_hw_state(p, &hw_state->c20);
2858
2858
}
2859
2859
2860
2860
static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
+2
-1
drivers/gpu/drm/i915/display/intel_cx0_phy.h
+2
-1
drivers/gpu/drm/i915/display/intel_cx0_phy.h
···
11
11
#define MB_WRITE_COMMITTED true
12
12
#define MB_WRITE_UNCOMMITTED false
13
13
14
+
struct drm_printer;
14
15
enum icl_port_dpll_id;
15
16
struct intel_atomic_state;
16
17
struct intel_c10pll_state;
···
42
41
int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
43
42
const struct intel_cx0pll_state *pll_state);
44
43
45
-
void intel_cx0pll_dump_hw_state(struct intel_display *display,
44
+
void intel_cx0pll_dump_hw_state(struct drm_printer *p,
46
45
const struct intel_cx0pll_state *hw_state);
47
46
bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
48
47
const struct intel_cx0pll_state *b);
+2
-3
drivers/gpu/drm/i915/display/intel_display.c
+2
-3
drivers/gpu/drm/i915/display/intel_display.c
···
4984
4984
const struct intel_cx0pll_state *a,
4985
4985
const struct intel_cx0pll_state *b)
4986
4986
{
4987
-
struct intel_display *display = to_intel_display(crtc);
4988
4987
char *chipname = a->use_c10 ? "C10" : "C20";
4989
4988
4990
4989
pipe_config_mismatch(p, fastset, crtc, name, chipname);
4991
4990
4992
4991
drm_printf(p, "expected:\n");
4993
-
intel_cx0pll_dump_hw_state(display, a);
4992
+
intel_cx0pll_dump_hw_state(p, a);
4994
4993
drm_printf(p, "found:\n");
4995
-
intel_cx0pll_dump_hw_state(display, b);
4994
+
intel_cx0pll_dump_hw_state(p, b);
4996
4995
}
4997
4996
4998
4997
static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state)
+7
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+7
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
···
4443
4443
return mtl_get_non_tc_phy_dpll(state, crtc, encoder);
4444
4444
}
4445
4445
4446
+
static void mtl_dump_hw_state(struct drm_printer *p,
4447
+
const struct intel_dpll_hw_state *dpll_hw_state)
4448
+
{
4449
+
intel_cx0pll_dump_hw_state(p, &dpll_hw_state->cx0pll);
4450
+
}
4451
+
4446
4452
__maybe_unused
4447
4453
static const struct intel_dpll_mgr mtl_pll_mgr = {
4448
4454
.dpll_info = mtl_plls,
···
4457
4451
.put_dplls = icl_put_dplls,
4458
4452
.update_active_dpll = icl_update_active_dpll,
4459
4453
.update_ref_clks = icl_update_dpll_ref_clks,
4454
+
.dump_hw_state = mtl_dump_hw_state,
4460
4455
};
4461
4456
4462
4457
/**