Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-for-linus-5.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Palmer Dabbelt:
"A smattering of fixes and cleanups:
- Dead code removal.
- Exporting riscv_cpuid_to_hartid_mask for modules.
- Per-CPU tracking of ISA features.
- Setting max_pfn correctly when probing memory.
- Adding a note to the VDSO so glibc can check the kernel's version
without a uname().
- A fix to force the bootloader to initialize the boot spin tables,
which still get used as a fallback when SBI-0.1 is enabled"
* tag 'riscv-for-linus-5.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
RISC-V: Remove unused code from STRICT_KERNEL_RWX
riscv: force __cpu_up_ variables to put in data section
riscv: add Linux note to vdso
riscv: set max_pfn to the PFN of the last page
RISC-V: Remove N-extension related defines
RISC-V: Add bitmap reprensenting ISA features common across CPUs
RISC-V: Export riscv_cpuid_to_hartid_mask() API
+121
-34
-3
arch/riscv/include/asm/csr.h
-3
arch/riscv/include/asm/csr.h
···
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#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
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/* Interrupt causes (minus the high bit) */
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-
#define IRQ_U_SOFT 0
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#define IRQ_S_SOFT 1
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#define IRQ_M_SOFT 3
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-
#define IRQ_U_TIMER 4
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#define IRQ_S_TIMER 5
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#define IRQ_M_TIMER 7
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-
#define IRQ_U_EXT 8
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#define IRQ_S_EXT 9
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#define IRQ_M_EXT 11
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+22
arch/riscv/include/asm/hwcap.h
+22
arch/riscv/include/asm/hwcap.h
···
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#ifndef _ASM_RISCV_HWCAP_H
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#define _ASM_RISCV_HWCAP_H
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#include <linux/bits.h>
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#include <uapi/asm/hwcap.h>
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#ifndef __ASSEMBLY__
···
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};
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extern unsigned long elf_hwcap;
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+
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#define RISCV_ISA_EXT_a ('a' - 'a')
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#define RISCV_ISA_EXT_c ('c' - 'a')
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#define RISCV_ISA_EXT_d ('d' - 'a')
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#define RISCV_ISA_EXT_f ('f' - 'a')
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#define RISCV_ISA_EXT_h ('h' - 'a')
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#define RISCV_ISA_EXT_i ('i' - 'a')
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#define RISCV_ISA_EXT_m ('m' - 'a')
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#define RISCV_ISA_EXT_s ('s' - 'a')
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#define RISCV_ISA_EXT_u ('u' - 'a')
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+
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#define RISCV_ISA_EXT_MAX 64
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+
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unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
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+
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#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
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bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
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#define riscv_isa_extension_available(isa_bitmap, ext) \
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__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
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#endif
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#endif /* _ASM_RISCV_HWCAP_H */
-8
arch/riscv/include/asm/set_memory.h
-8
arch/riscv/include/asm/set_memory.h
···
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static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; }
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#endif
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-
#ifdef CONFIG_STRICT_KERNEL_RWX
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void set_kernel_text_ro(void);
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void set_kernel_text_rw(void);
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#else
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static inline void set_kernel_text_ro(void) { }
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static inline void set_kernel_text_rw(void) { }
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-
#endif
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-
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int set_direct_map_invalid_noflush(struct page *page);
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int set_direct_map_default_noflush(struct page *page);
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+2
-2
arch/riscv/kernel/cpu_ops.c
+2
-2
arch/riscv/kernel/cpu_ops.c
···
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const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init;
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void *__cpu_up_stack_pointer[NR_CPUS];
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void *__cpu_up_task_pointer[NR_CPUS];
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void *__cpu_up_stack_pointer[NR_CPUS] __section(.data);
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void *__cpu_up_task_pointer[NR_CPUS] __section(.data);
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extern const struct cpu_operations cpu_ops_sbi;
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extern const struct cpu_operations cpu_ops_spinwait;
+80
-3
arch/riscv/kernel/cpufeature.c
+80
-3
arch/riscv/kernel/cpufeature.c
···
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/bitmap.h>
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#include <linux/of.h>
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#include <asm/processor.h>
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#include <asm/hwcap.h>
···
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#include <asm/switch_to.h>
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unsigned long elf_hwcap __read_mostly;
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/* Host ISA bitmap */
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static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
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#ifdef CONFIG_FPU
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bool has_fpu __read_mostly;
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#endif
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/**
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* riscv_isa_extension_base() - Get base extension word
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*
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* @isa_bitmap: ISA bitmap to use
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* Return: base extension word as unsigned long value
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*
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* NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
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*/
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unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
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{
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+
if (!isa_bitmap)
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return riscv_isa[0];
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return isa_bitmap[0];
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}
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EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
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+
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/**
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* __riscv_isa_extension_available() - Check whether given extension
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* is available or not
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*
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* @isa_bitmap: ISA bitmap to use
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* @bit: bit position of the desired extension
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* Return: true or false
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*
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* NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
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*/
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bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
51
+
{
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const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
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+
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if (bit >= RISCV_ISA_EXT_MAX)
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return false;
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+
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return test_bit(bit, bmap) ? true : false;
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}
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EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
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void riscv_fill_hwcap(void)
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{
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struct device_node *node;
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const char *isa;
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-
size_t i;
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char print_str[BITS_PER_LONG + 1];
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size_t i, j, isa_len;
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static unsigned long isa2hwcap[256] = {0};
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68
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isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
···
76
33
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elf_hwcap = 0;
78
35
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+
bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
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+
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for_each_of_cpu_node(node) {
80
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unsigned long this_hwcap = 0;
40
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unsigned long this_isa = 0;
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41
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if (riscv_of_processor_hartid(node) < 0)
83
43
continue;
···
90
44
continue;
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45
}
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46
93
-
for (i = 0; i < strlen(isa); ++i)
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+
i = 0;
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+
isa_len = strlen(isa);
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+
#if IS_ENABLED(CONFIG_32BIT)
50
+
if (!strncmp(isa, "rv32", 4))
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+
i += 4;
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+
#elif IS_ENABLED(CONFIG_64BIT)
53
+
if (!strncmp(isa, "rv64", 4))
54
+
i += 4;
55
+
#endif
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+
for (; i < isa_len; ++i) {
94
57
this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
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/*
59
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* TODO: X, Y and Z extension parsing for Host ISA
60
+
* bitmap will be added in-future.
61
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*/
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if ('a' <= isa[i] && isa[i] < 'x')
63
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this_isa |= (1UL << (isa[i] - 'a'));
64
+
}
95
65
96
66
/*
97
67
* All "okay" hart should have same isa. Set HWCAP based on
···
118
56
elf_hwcap &= this_hwcap;
119
57
else
120
58
elf_hwcap = this_hwcap;
59
+
60
+
if (riscv_isa[0])
61
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riscv_isa[0] &= this_isa;
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+
else
63
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riscv_isa[0] = this_isa;
121
64
}
122
65
123
66
/* We don't support systems with F but without D, so mask those out
···
132
65
elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
133
66
}
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67
135
-
pr_info("elf_hwcap is 0x%lx\n", elf_hwcap);
68
+
memset(print_str, 0, sizeof(print_str));
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+
for (i = 0, j = 0; i < BITS_PER_LONG; i++)
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if (riscv_isa[0] & BIT_MASK(i))
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print_str[j++] = (char)('a' + i);
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pr_info("riscv: ISA extensions %s\n", print_str);
73
+
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memset(print_str, 0, sizeof(print_str));
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+
for (i = 0, j = 0; i < BITS_PER_LONG; i++)
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+
if (elf_hwcap & BIT_MASK(i))
77
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print_str[j++] = (char)('a' + i);
78
+
pr_info("riscv: ELF capabilities %s\n", print_str);
136
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#ifdef CONFIG_FPU
138
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if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
+2
arch/riscv/kernel/smp.c
+2
arch/riscv/kernel/smp.c
···
10
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
13
+
#include <linux/module.h>
13
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#include <linux/profile.h>
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#include <linux/smp.h>
15
16
#include <linux/sched.h>
···
64
63
for_each_cpu(cpu, in)
65
64
cpumask_set_cpu(cpuid_to_hartid_map(cpu), out);
66
65
}
66
+
EXPORT_SYMBOL_GPL(riscv_cpuid_to_hartid_mask);
67
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bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
69
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{
+1
-1
arch/riscv/kernel/vdso/Makefile
+1
-1
arch/riscv/kernel/vdso/Makefile
+12
arch/riscv/kernel/vdso/note.S
+12
arch/riscv/kernel/vdso/note.S
···
1
+
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
+
/*
3
+
* This supplies .note.* sections to go into the PT_NOTE inside the vDSO text.
4
+
* Here we can supply some information useful to userland.
5
+
*/
6
+
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#include <linux/elfnote.h>
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+
#include <linux/version.h>
9
+
10
+
ELFNOTE_START(Linux, 0, "a")
11
+
.long LINUX_VERSION_CODE
12
+
ELFNOTE_END
+2
-17
arch/riscv/mm/init.c
+2
-17
arch/riscv/mm/init.c
···
150
150
memblock_reserve(vmlinux_start, vmlinux_end - vmlinux_start);
151
151
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152
set_max_mapnr(PFN_DOWN(mem_size));
153
-
max_low_pfn = PFN_DOWN(memblock_end_of_DRAM());
153
+
max_pfn = PFN_DOWN(memblock_end_of_DRAM());
154
+
max_low_pfn = max_pfn;
154
155
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156
#ifdef CONFIG_BLK_DEV_INITRD
156
157
setup_initrd();
···
502
501
#endif /* CONFIG_MMU */
503
502
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503
#ifdef CONFIG_STRICT_KERNEL_RWX
505
-
void set_kernel_text_rw(void)
506
-
{
507
-
unsigned long text_start = (unsigned long)_text;
508
-
unsigned long text_end = (unsigned long)_etext;
509
-
510
-
set_memory_rw(text_start, (text_end - text_start) >> PAGE_SHIFT);
511
-
}
512
-
513
-
void set_kernel_text_ro(void)
514
-
{
515
-
unsigned long text_start = (unsigned long)_text;
516
-
unsigned long text_end = (unsigned long)_etext;
517
-
518
-
set_memory_ro(text_start, (text_end - text_start) >> PAGE_SHIFT);
519
-
}
520
-
521
504
void mark_rodata_ro(void)
522
505
{
523
506
unsigned long text_start = (unsigned long)_text;