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drm/amdgpu: compatible with specific RAS old eeprom format

Handle RAS eeprom record when UMC_CHANNEL_IDX_V2 is set.

v2: get UMC_CHANNEL_IDX_V2 flag before the clear of it.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Tao Zhou and committed by
Alex Deucher 2e36bc6a c561d232

+12 -5
+12 -5
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
··· 3130 3130 enum amdgpu_memory_partition nps) 3131 3131 { 3132 3132 int i = 0; 3133 + uint64_t chan_idx_v2; 3133 3134 enum amdgpu_memory_partition save_nps; 3134 3135 3135 3136 save_nps = (bps[0].retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; 3137 + chan_idx_v2 = bps[0].retired_page & UMC_CHANNEL_IDX_V2; 3136 3138 3137 3139 /*old asics just have pa in eeprom*/ 3138 3140 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) { ··· 3146 3144 for (i = 0; i < adev->umc.retire_unit; i++) 3147 3145 bps[i].retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); 3148 3146 3149 - if (save_nps) { 3147 + if (save_nps || chan_idx_v2) { 3150 3148 if (save_nps == nps) { 3151 3149 if (amdgpu_umc_pages_in_a_row(adev, err_data, 3152 3150 bps[0].retired_page << AMDGPU_GPU_PAGE_SHIFT)) ··· 3190 3188 enum amdgpu_memory_partition nps) 3191 3189 { 3192 3190 int i = 0; 3191 + uint64_t chan_idx_v2; 3193 3192 enum amdgpu_memory_partition save_nps; 3194 3193 3195 3194 if (!amdgpu_ras_smu_eeprom_supported(adev)) { 3196 3195 save_nps = (bps->retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; 3196 + chan_idx_v2 = bps->retired_page & UMC_CHANNEL_IDX_V2; 3197 3197 bps->retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); 3198 3198 } else { 3199 3199 /* if pmfw manages eeprom, save_nps is not stored on eeprom, ··· 3217 3213 err_data->err_addr[i].mcumc_id = bps->mcumc_id; 3218 3214 } 3219 3215 } else { 3220 - if (bps->address) { 3216 + if (save_nps || chan_idx_v2) { 3221 3217 if (amdgpu_ras_mca2pa_by_idx(adev, bps, err_data)) 3222 3218 return -EINVAL; 3223 3219 } else { 3224 3220 /* for specific old eeprom data, mca address is not stored, 3225 3221 * calc it from pa 3226 3222 */ 3227 - if (amdgpu_umc_pa2mca(adev, bps->retired_page << AMDGPU_GPU_PAGE_SHIFT, 3228 - &(bps->address), AMDGPU_NPS1_PARTITION_MODE)) 3229 - return -EINVAL; 3223 + if (bps->address == 0) 3224 + if (amdgpu_umc_pa2mca(adev, 3225 + bps->retired_page << AMDGPU_GPU_PAGE_SHIFT, 3226 + &(bps->address), 3227 + AMDGPU_NPS1_PARTITION_MODE)) 3228 + return -EINVAL; 3230 3229 3231 3230 if (amdgpu_ras_mca2pa(adev, bps, err_data)) 3232 3231 return -EOPNOTSUPP;