tjh.dev / kernel
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memory: tegra: Group SoC specific fields

Introduce new SoC specific fields in tegra_mc_soc struct for high
address mask and error status type mask because Tegra264 has different
values for these than the existing devices. Error status registers
e.g. MC_ERR_STATUS_0 has few bits which indicate the type of the
error. In order to obtain such type of error from error status
register, we use error status type mask. Similarly, these error status
registers have bits which indicate the higher address bits of the
address responsible for mc error. In order to obtain such higher
address, we use high address mask. Make this change to prepare for
adding MC interrupt support for Tegra264.

Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260226163115.1152181-5-ketanp@nvidia.com
[krzk: Fix checkpatch warning]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

authored by

Ketan Patil and committed by
Krzysztof Kozlowski 2e4cfaa7 4d865a23

+24 -6
+7 -4
drivers/memory/tegra/mc.c
··· 658 658 addr = mc_ch_readl(mc, channel, addr_hi_reg); 659 659 else 660 660 addr = mc_readl(mc, addr_hi_reg); 661 - } else { 661 + } else if (mc->soc->mc_addr_hi_mask) { 662 662 addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & 663 - MC_ERR_STATUS_ADR_HI_MASK); 663 + mc->soc->mc_addr_hi_mask); 664 + } else { 665 + dev_err_ratelimited(mc->dev, "Unable to determine high address!"); 666 + return IRQ_NONE; 664 667 } 665 668 addr <<= 32; 666 669 } ··· 688 685 } 689 686 } 690 687 691 - type = (value & MC_ERR_STATUS_TYPE_MASK) >> 688 + type = (value & mc->soc->mc_err_status_type_mask) >> 692 689 MC_ERR_STATUS_TYPE_SHIFT; 693 690 desc = tegra_mc_error_names[type]; 694 691 695 - switch (value & MC_ERR_STATUS_TYPE_MASK) { 692 + switch (value & mc->soc->mc_err_status_type_mask) { 696 693 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: 697 694 perm[0] = ' '; 698 695 perm[1] = '[';
-2
drivers/memory/tegra/mc.h
··· 78 78 79 79 #define MC_ERR_STATUS_TYPE_SHIFT 28 80 80 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (0x6 << 28) 81 - #define MC_ERR_STATUS_TYPE_MASK (0x7 << 28) 82 81 83 82 #define MC_ERR_STATUS_ADR_HI_SHIFT 20 84 - #define MC_ERR_STATUS_ADR_HI_MASK 0x3 85 83 86 84 #define MC_BROADCAST_CHANNEL ~0 87 85
+1
drivers/memory/tegra/tegra114.c
··· 1117 1117 .regs = &tegra20_mc_regs, 1118 1118 .handle_irq = tegra30_mc_irq_handlers, 1119 1119 .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers), 1120 + .mc_err_status_type_mask = (0x7 << 28), 1120 1121 };
+4
drivers/memory/tegra/tegra124.c
··· 1278 1278 .regs = &tegra20_mc_regs, 1279 1279 .handle_irq = tegra30_mc_irq_handlers, 1280 1280 .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers), 1281 + .mc_addr_hi_mask = 0x3, 1282 + .mc_err_status_type_mask = (0x7 << 28), 1281 1283 }; 1282 1284 #endif /* CONFIG_ARCH_TEGRA_124_SOC */ 1283 1285 ··· 1315 1313 .regs = &tegra20_mc_regs, 1316 1314 .handle_irq = tegra30_mc_irq_handlers, 1317 1315 .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers), 1316 + .mc_addr_hi_mask = 0x3, 1317 + .mc_err_status_type_mask = (0x7 << 28), 1318 1318 }; 1319 1319 #endif /* CONFIG_ARCH_TEGRA_132_SOC */
+2
drivers/memory/tegra/tegra186.c
··· 916 916 .regs = &tegra20_mc_regs, 917 917 .handle_irq = tegra30_mc_irq_handlers, 918 918 .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers), 919 + .mc_addr_hi_mask = 0x3, 920 + .mc_err_status_type_mask = (0x7 << 28), 919 921 }; 920 922 #endif
+2
drivers/memory/tegra/tegra194.c
··· 1361 1361 .regs = &tegra20_mc_regs, 1362 1362 .handle_irq = tegra30_mc_irq_handlers, 1363 1363 .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers), 1364 + .mc_addr_hi_mask = 0x3, 1365 + .mc_err_status_type_mask = (0x7 << 28), 1364 1366 };
+1
drivers/memory/tegra/tegra20.c
··· 784 784 .regs = &tegra20_mc_regs, 785 785 .handle_irq = tegra20_mc_irq_handlers, 786 786 .num_interrupts = ARRAY_SIZE(tegra20_mc_irq_handlers), 787 + .mc_err_status_type_mask = (0x7 << 28), 787 788 };
+2
drivers/memory/tegra/tegra210.c
··· 1290 1290 .regs = &tegra20_mc_regs, 1291 1291 .handle_irq = tegra30_mc_irq_handlers, 1292 1292 .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers), 1293 + .mc_addr_hi_mask = 0x3, 1294 + .mc_err_status_type_mask = (0x7 << 28), 1293 1295 };
+2
drivers/memory/tegra/tegra234.c
··· 1155 1155 .regs = &tegra20_mc_regs, 1156 1156 .handle_irq = tegra30_mc_irq_handlers, 1157 1157 .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers), 1158 + .mc_addr_hi_mask = 0x3, 1159 + .mc_err_status_type_mask = (0x7 << 28), 1158 1160 };
+1
drivers/memory/tegra/tegra30.c
··· 1403 1403 .regs = &tegra20_mc_regs, 1404 1404 .handle_irq = tegra30_mc_irq_handlers, 1405 1405 .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers), 1406 + .mc_err_status_type_mask = (0x7 << 28), 1406 1407 };
+2
include/soc/tegra/mc.h
··· 217 217 218 218 const irq_handler_t *handle_irq; 219 219 unsigned int num_interrupts; 220 + unsigned int mc_addr_hi_mask; 221 + unsigned int mc_err_status_type_mask; 220 222 }; 221 223 222 224 struct tegra_mc {