Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-for-linus-6.1-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
- Improvements to the CPU topology subsystem, which fix some issues
where RISC-V would report bad topology information.
- The default NR_CPUS has increased to XLEN, and the maximum
configurable value is 512.
- The CD-ROM filesystems have been enabled in the defconfig.
- Support for THP_SWAP has been added for rv64 systems.
There are also a handful of cleanups and fixes throughout the tree.
* tag 'riscv-for-linus-6.1-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: enable THP_SWAP for RV64
RISC-V: Print SSTC in canonical order
riscv: compat: s/failed/unsupported if compat mode isn't supported
RISC-V: Increase range and default value of NR_CPUS
cpuidle: riscv-sbi: Fix CPU_PM_CPU_IDLE_ENTER_xyz() macro usage
perf: RISC-V: throttle perf events
perf: RISC-V: exclude invalid pmu counters from SBI calls
riscv: enable CD-ROM file systems in defconfig
riscv: topology: fix default topology reporting
arm64: topology: move store_cpu_topology() to shared code
+63
-62
-40
arch/arm64/kernel/topology.c
-40
arch/arm64/kernel/topology.c
···
22
22
#include <asm/cputype.h>
23
23
#include <asm/topology.h>
24
24
25
-
void store_cpu_topology(unsigned int cpuid)
26
-
{
27
-
struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
28
-
u64 mpidr;
29
-
30
-
if (cpuid_topo->package_id != -1)
31
-
goto topology_populated;
32
-
33
-
mpidr = read_cpuid_mpidr();
34
-
35
-
/* Uniprocessor systems can rely on default topology values */
36
-
if (mpidr & MPIDR_UP_BITMASK)
37
-
return;
38
-
39
-
/*
40
-
* This would be the place to create cpu topology based on MPIDR.
41
-
*
42
-
* However, it cannot be trusted to depict the actual topology; some
43
-
* pieces of the architecture enforce an artificial cap on Aff0 values
44
-
* (e.g. GICv3's ICC_SGI1R_EL1 limits it to 15), leading to an
45
-
* artificial cycling of Aff1, Aff2 and Aff3 values. IOW, these end up
46
-
* having absolutely no relationship to the actual underlying system
47
-
* topology, and cannot be reasonably used as core / package ID.
48
-
*
49
-
* If the MT bit is set, Aff0 *could* be used to define a thread ID, but
50
-
* we still wouldn't be able to obtain a sane core ID. This means we
51
-
* need to entirely ignore MPIDR for any topology deduction.
52
-
*/
53
-
cpuid_topo->thread_id = -1;
54
-
cpuid_topo->core_id = cpuid;
55
-
cpuid_topo->package_id = cpu_to_node(cpuid);
56
-
57
-
pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n",
58
-
cpuid, cpuid_topo->package_id, cpuid_topo->core_id,
59
-
cpuid_topo->thread_id, mpidr);
60
-
61
-
topology_populated:
62
-
update_siblings_masks(cpuid);
63
-
}
64
-
65
25
#ifdef CONFIG_ACPI
66
26
static bool __init acpi_cpu_is_threaded(int cpu)
67
27
{
+8
-4
arch/riscv/Kconfig
+8
-4
arch/riscv/Kconfig
···
45
45
select ARCH_WANT_FRAME_POINTERS
46
46
select ARCH_WANT_GENERAL_HUGETLB
47
47
select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
48
+
select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
48
49
select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU
49
50
select BUILDTIME_TABLE_SORT if MMU
50
51
select CLONE_BACKWARDS
···
53
52
select COMMON_CLK
54
53
select CPU_PM if CPU_IDLE
55
54
select EDAC_SUPPORT
56
-
select GENERIC_ARCH_TOPOLOGY if SMP
55
+
select GENERIC_ARCH_TOPOLOGY
57
56
select GENERIC_ATOMIC64 if !64BIT
58
57
select GENERIC_CLOCKEVENTS_BROADCAST if SMP
59
58
select GENERIC_EARLY_IOREMAP
···
310
309
If you don't know what to do here, say N.
311
310
312
311
config NR_CPUS
313
-
int "Maximum number of CPUs (2-32)"
314
-
range 2 32
312
+
int "Maximum number of CPUs (2-512)"
315
313
depends on SMP
316
-
default "8"
314
+
range 2 512 if !SBI_V01
315
+
range 2 32 if SBI_V01 && 32BIT
316
+
range 2 64 if SBI_V01 && 64BIT
317
+
default "32" if 32BIT
318
+
default "64" if 64BIT
317
319
318
320
config HOTPLUG_CPU
319
321
bool "Support for hot-pluggable CPUs"
+3
arch/riscv/configs/defconfig
+3
arch/riscv/configs/defconfig
+1
-1
arch/riscv/kernel/cpu.c
+1
-1
arch/riscv/kernel/cpu.c
···
92
92
*/
93
93
static struct riscv_isa_ext_data isa_ext_arr[] = {
94
94
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
95
+
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
95
96
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
96
97
__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
97
98
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
98
-
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
99
99
__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
100
100
};
101
101
+1
-1
arch/riscv/kernel/process.c
+1
-1
arch/riscv/kernel/process.c
+2
-1
arch/riscv/kernel/smpboot.c
+2
-1
arch/riscv/kernel/smpboot.c
···
49
49
unsigned int curr_cpuid;
50
50
51
51
curr_cpuid = smp_processor_id();
52
+
store_cpu_topology(curr_cpuid);
52
53
numa_store_cpu_info(curr_cpuid);
53
54
numa_add_cpu(curr_cpuid);
54
55
···
163
162
mmgrab(mm);
164
163
current->active_mm = mm;
165
164
165
+
store_cpu_topology(curr_cpuid);
166
166
notify_cpu_starting(curr_cpuid);
167
167
numa_add_cpu(curr_cpuid);
168
-
update_siblings_masks(curr_cpuid);
169
168
set_cpu_online(curr_cpuid, 1);
170
169
171
170
/*
+19
drivers/base/arch_topology.c
+19
drivers/base/arch_topology.c
···
841
841
return;
842
842
}
843
843
}
844
+
845
+
void store_cpu_topology(unsigned int cpuid)
846
+
{
847
+
struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
848
+
849
+
if (cpuid_topo->package_id != -1)
850
+
goto topology_populated;
851
+
852
+
cpuid_topo->thread_id = -1;
853
+
cpuid_topo->core_id = cpuid;
854
+
cpuid_topo->package_id = cpu_to_node(cpuid);
855
+
856
+
pr_debug("CPU%u: package %d core %d thread %d\n",
857
+
cpuid, cpuid_topo->package_id, cpuid_topo->core_id,
858
+
cpuid_topo->thread_id);
859
+
860
+
topology_populated:
861
+
update_siblings_masks(cpuid);
862
+
}
844
863
#endif
+6
-1
drivers/cpuidle/cpuidle-riscv-sbi.c
+6
-1
drivers/cpuidle/cpuidle-riscv-sbi.c
···
97
97
struct cpuidle_driver *drv, int idx)
98
98
{
99
99
u32 *states = __this_cpu_read(sbi_cpuidle_data.states);
100
+
u32 state = states[idx];
100
101
101
-
return CPU_PM_CPU_IDLE_ENTER_PARAM(sbi_suspend, idx, states[idx]);
102
+
if (state & SBI_HSM_SUSP_NON_RET_BIT)
103
+
return CPU_PM_CPU_IDLE_ENTER_PARAM(sbi_suspend, idx, state);
104
+
else
105
+
return CPU_PM_CPU_IDLE_ENTER_RETENTION_PARAM(sbi_suspend,
106
+
idx, state);
102
107
}
103
108
104
109
static int __sbi_enter_domain_idle_state(struct cpuidle_device *dev,
+2
-2
drivers/perf/riscv_pmu_legacy.c
+2
-2
drivers/perf/riscv_pmu_legacy.c
···
14
14
15
15
#define RISCV_PMU_LEGACY_CYCLE 0
16
16
#define RISCV_PMU_LEGACY_INSTRET 1
17
-
#define RISCV_PMU_LEGACY_NUM_CTR 2
18
17
19
18
static bool pmu_init_done;
20
19
···
82
83
{
83
84
pr_info("Legacy PMU implementation is available\n");
84
85
85
-
pmu->num_counters = RISCV_PMU_LEGACY_NUM_CTR;
86
+
pmu->cmask = BIT(RISCV_PMU_LEGACY_CYCLE) |
87
+
BIT(RISCV_PMU_LEGACY_INSTRET);
86
88
pmu->ctr_start = pmu_legacy_ctr_start;
87
89
pmu->ctr_stop = NULL;
88
90
pmu->event_map = pmu_legacy_event_map;
+20
-11
drivers/perf/riscv_pmu_sbi.c
+20
-11
drivers/perf/riscv_pmu_sbi.c
···
18
18
#include <linux/of_irq.h>
19
19
#include <linux/of.h>
20
20
#include <linux/cpu_pm.h>
21
+
#include <linux/sched/clock.h>
21
22
22
23
#include <asm/sbi.h>
23
24
#include <asm/hwcap.h>
···
272
271
struct sbiret ret;
273
272
int idx;
274
273
uint64_t cbase = 0;
275
-
uint64_t cmask = GENMASK_ULL(rvpmu->num_counters - 1, 0);
276
274
unsigned long cflags = 0;
277
275
278
276
if (event->attr.exclude_kernel)
···
281
281
282
282
/* retrieve the available counter index */
283
283
#if defined(CONFIG_32BIT)
284
-
ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask,
285
-
cflags, hwc->event_base, hwc->config, hwc->config >> 32);
284
+
ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase,
285
+
rvpmu->cmask, cflags, hwc->event_base, hwc->config,
286
+
hwc->config >> 32);
286
287
#else
287
-
ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask,
288
-
cflags, hwc->event_base, hwc->config, 0);
288
+
ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase,
289
+
rvpmu->cmask, cflags, hwc->event_base, hwc->config, 0);
289
290
#endif
290
291
if (ret.error) {
291
292
pr_debug("Not able to find a counter for event %lx config %llx\n",
···
295
294
}
296
295
297
296
idx = ret.value;
298
-
if (idx >= rvpmu->num_counters || !pmu_ctr_list[idx].value)
297
+
if (!test_bit(idx, &rvpmu->cmask) || !pmu_ctr_list[idx].value)
299
298
return -ENOENT;
300
299
301
300
/* Additional sanity check for the counter id */
···
464
463
return sbi_err_map_linux_errno(ret.error);
465
464
}
466
465
467
-
static int pmu_sbi_get_ctrinfo(int nctr)
466
+
static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask)
468
467
{
469
468
struct sbiret ret;
470
469
int i, num_hw_ctr = 0, num_fw_ctr = 0;
···
479
478
if (ret.error)
480
479
/* The logical counter ids are not expected to be contiguous */
481
480
continue;
481
+
482
+
*mask |= BIT(i);
483
+
482
484
cinfo.value = ret.value;
483
485
if (cinfo.type == SBI_PMU_CTR_TYPE_FW)
484
486
num_fw_ctr++;
···
502
498
* which may include counters that are not enabled yet.
503
499
*/
504
500
sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
505
-
0, GENMASK_ULL(pmu->num_counters - 1, 0), 0, 0, 0, 0);
501
+
0, pmu->cmask, 0, 0, 0, 0);
506
502
}
507
503
508
504
static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu)
···
571
567
unsigned long overflow;
572
568
unsigned long overflowed_ctrs = 0;
573
569
struct cpu_hw_events *cpu_hw_evt = dev;
570
+
u64 start_clock = sched_clock();
574
571
575
572
if (WARN_ON_ONCE(!cpu_hw_evt))
576
573
return IRQ_NONE;
···
640
635
perf_event_overflow(event, &data, regs);
641
636
}
642
637
}
638
+
643
639
pmu_sbi_start_overflow_mask(pmu, overflowed_ctrs);
640
+
perf_sample_event_took(sched_clock() - start_clock);
644
641
645
642
return IRQ_HANDLED;
646
643
}
···
795
788
static int pmu_sbi_device_probe(struct platform_device *pdev)
796
789
{
797
790
struct riscv_pmu *pmu = NULL;
798
-
int num_counters;
791
+
unsigned long cmask = 0;
799
792
int ret = -ENODEV;
793
+
int num_counters;
800
794
801
795
pr_info("SBI PMU extension is available\n");
802
796
pmu = riscv_pmu_alloc();
···
811
803
}
812
804
813
805
/* cache all the information about counters now */
814
-
if (pmu_sbi_get_ctrinfo(num_counters))
806
+
if (pmu_sbi_get_ctrinfo(num_counters, &cmask))
815
807
goto out_free;
816
808
817
809
ret = pmu_sbi_setup_irqs(pmu, pdev);
···
820
812
pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
821
813
pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
822
814
}
815
+
823
816
pmu->pmu.attr_groups = riscv_pmu_attr_groups;
824
-
pmu->num_counters = num_counters;
817
+
pmu->cmask = cmask;
825
818
pmu->ctr_start = pmu_sbi_ctr_start;
826
819
pmu->ctr_stop = pmu_sbi_ctr_stop;
827
820
pmu->event_map = pmu_sbi_event_map;