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EDAC/i10nm: Skip DIMM enumeration on a disabled memory controller

When loading the i10nm_edac driver on some Intel Granite Rapids servers,
a call trace may appear as follows:

UBSAN: shift-out-of-bounds in drivers/edac/skx_common.c:453:16
shift exponent -66 is negative
...
__ubsan_handle_shift_out_of_bounds+0x1e3/0x390
skx_get_dimm_info.cold+0x47/0xd40 [skx_edac_common]
i10nm_get_dimm_config+0x23e/0x390 [i10nm_edac]
skx_register_mci+0x159/0x220 [skx_edac_common]
i10nm_init+0xcb0/0x1ff0 [i10nm_edac]
...

This occurs because some BIOS may disable a memory controller if there
aren't any memory DIMMs populated on this memory controller. The DIMMMTR
register of this disabled memory controller contains the invalid value
~0, resulting in the call trace above.

Fix this call trace by skipping DIMM enumeration on a disabled memory
controller.

Fixes: ba987eaaabf9 ("EDAC/i10nm: Add Intel Granite Rapids server support")
Reported-by: Jose Jesus Ambriz Meza <jose.jesus.ambriz.meza@intel.com>
Reported-by: Chia-Lin Kao (AceLan) <acelan.kao@canonical.com>
Closes: https://lore.kernel.org/all/20250730063155.2612379-1-acelan.kao@canonical.com/
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Tested-by: Chia-Lin Kao (AceLan) <acelan.kao@canonical.com>
Link: https://lore.kernel.org/r/20250806065707.3533345-1-qiuxu.zhuo@intel.com

authored by

Qiuxu Zhuo and committed by
Tony Luck
2e6fe1bb 71b69f81

+14
+14
drivers/edac/i10nm_base.c
··· 1057 1057 return !!GET_BITFIELD(mcmtr, 2, 2); 1058 1058 } 1059 1059 1060 + static bool i10nm_channel_disabled(struct skx_imc *imc, int chan) 1061 + { 1062 + u32 mcmtr = I10NM_GET_MCMTR(imc, chan); 1063 + 1064 + edac_dbg(1, "mc%d ch%d mcmtr reg %x\n", imc->mc, chan, mcmtr); 1065 + 1066 + return (mcmtr == ~0 || GET_BITFIELD(mcmtr, 18, 18)); 1067 + } 1068 + 1060 1069 static int i10nm_get_dimm_config(struct mem_ctl_info *mci, 1061 1070 struct res_config *cfg) 1062 1071 { ··· 1078 1069 for (i = 0; i < imc->num_channels; i++) { 1079 1070 if (!imc->mbase) 1080 1071 continue; 1072 + 1073 + if (i10nm_channel_disabled(imc, i)) { 1074 + edac_dbg(1, "mc%d ch%d is disabled.\n", imc->mc, i); 1075 + continue; 1076 + } 1081 1077 1082 1078 ndimms = 0; 1083 1079