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spi: dt-bindings: adi,axi-spi-engine: add multi-lane support

Extend the ADI AXI SPI engine binding for multiple data lanes. This SPI
controller has a capability to read multiple data words at the same
time (e.g. for use with simultaneous sampling ADCs). The current FPGA
implementation can support up to 8 data lanes at a time (depending on a
compile-time configuration option).

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-6-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

David Lechner and committed by
Mark Brown 2e706f86 05c3bd74

+15
+15
Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml
··· 70 70 71 71 unevaluatedProperties: false 72 72 73 + patternProperties: 74 + "^.*@[0-9a-f]+": 75 + type: object 76 + 77 + properties: 78 + spi-rx-bus-width: 79 + maxItems: 8 80 + items: 81 + enum: [0, 1] 82 + 83 + spi-tx-bus-width: 84 + maxItems: 8 85 + items: 86 + enum: [0, 1] 87 + 73 88 examples: 74 89 - | 75 90 spi@44a00000 {