Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Add VCN_5_0_2 codecs capabilities support
Support VCN_5_0_2 codec query
Signed-off-by: Sonny Jiang <sonjiang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Sonny Jiang
and committed by
Alex Deucher
2eb660e6
8433398c
+34
+34
drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
+34
drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
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#define NORMALIZE_MID_REG_OFFSET(offset) \
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(offset & 0x3FFFF)
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static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_encode_vcn0 = {
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.codec_count = 0,
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.codec_array = NULL,
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};
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static const struct amdgpu_video_codec_info vcn_5_0_2_video_codecs_decode_array_vcn0[] = {
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
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};
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static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_decode_vcn0 = {
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.codec_count = ARRAY_SIZE(vcn_5_0_2_video_codecs_decode_array_vcn0),
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.codec_array = vcn_5_0_2_video_codecs_decode_array_vcn0,
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};
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static int soc_v1_0_query_video_codecs(struct amdgpu_device *adev, bool encode,
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const struct amdgpu_video_codecs **codecs)
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{
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switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
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case IP_VERSION(5, 0, 2):
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if (encode)
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*codecs = &vcn_5_0_2_video_codecs_encode_vcn0;
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else
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*codecs = &vcn_5_0_2_video_codecs_decode_vcn0;
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return 0;
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default:
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return -EINVAL;
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}
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}
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/* Initialized doorbells for amdgpu including multimedia
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* KFD can use all the rest in 2M doorbell bar */
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static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev)
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.encode_ext_smn_addressing = &soc_v1_0_encode_ext_smn_addressing,
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.reset = soc_v1_0_asic_reset,
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.reset_method = &soc_v1_0_asic_reset_method,
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.query_video_codecs = &soc_v1_0_query_video_codecs,
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};
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static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block)