Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Nothing major in here, one radeon SI fix for tiling, and one uninit
var fix, two minor header file fixes."
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm: drop comment about this header being autogenerated.
drm/edid: don't return stack garbage from supports_rb
vga_switcheroo: Add include guard
drm/radeon: SI tiling fixes for display
+86
-6
+1
-1
drivers/gpu/drm/drm_edid.c
+1
-1
drivers/gpu/drm/drm_edid.c
+9
-1
drivers/gpu/drm/radeon/atombios_crtc.c
+9
-1
drivers/gpu/drm/radeon/atombios_crtc.c
···
1149
1149
}
1150
1150
1151
1151
if (tiling_flags & RADEON_TILING_MACRO) {
1152
-
if (rdev->family >= CHIP_CAYMAN)
1152
+
if (rdev->family >= CHIP_TAHITI)
1153
+
tmp = rdev->config.si.tile_config;
1154
+
else if (rdev->family >= CHIP_CAYMAN)
1153
1155
tmp = rdev->config.cayman.tile_config;
1154
1156
else
1155
1157
tmp = rdev->config.evergreen.tile_config;
···
1178
1176
fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1179
1177
} else if (tiling_flags & RADEON_TILING_MICRO)
1180
1178
fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1179
+
1180
+
if ((rdev->family == CHIP_TAHITI) ||
1181
+
(rdev->family == CHIP_PITCAIRN))
1182
+
fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1183
+
else if (rdev->family == CHIP_VERDE)
1184
+
fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1181
1185
1182
1186
switch (radeon_crtc->crtc_id) {
1183
1187
case 0:
+72
drivers/gpu/drm/radeon/si_reg.h
+72
drivers/gpu/drm/radeon/si_reg.h
···
30
30
#define SI_DC_GPIO_HPD_EN 0x65b8
31
31
#define SI_DC_GPIO_HPD_Y 0x65bc
32
32
33
+
#define SI_GRPH_CONTROL 0x6804
34
+
# define SI_GRPH_DEPTH(x) (((x) & 0x3) << 0)
35
+
# define SI_GRPH_DEPTH_8BPP 0
36
+
# define SI_GRPH_DEPTH_16BPP 1
37
+
# define SI_GRPH_DEPTH_32BPP 2
38
+
# define SI_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
39
+
# define SI_ADDR_SURF_2_BANK 0
40
+
# define SI_ADDR_SURF_4_BANK 1
41
+
# define SI_ADDR_SURF_8_BANK 2
42
+
# define SI_ADDR_SURF_16_BANK 3
43
+
# define SI_GRPH_Z(x) (((x) & 0x3) << 4)
44
+
# define SI_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
45
+
# define SI_ADDR_SURF_BANK_WIDTH_1 0
46
+
# define SI_ADDR_SURF_BANK_WIDTH_2 1
47
+
# define SI_ADDR_SURF_BANK_WIDTH_4 2
48
+
# define SI_ADDR_SURF_BANK_WIDTH_8 3
49
+
# define SI_GRPH_FORMAT(x) (((x) & 0x7) << 8)
50
+
/* 8 BPP */
51
+
# define SI_GRPH_FORMAT_INDEXED 0
52
+
/* 16 BPP */
53
+
# define SI_GRPH_FORMAT_ARGB1555 0
54
+
# define SI_GRPH_FORMAT_ARGB565 1
55
+
# define SI_GRPH_FORMAT_ARGB4444 2
56
+
# define SI_GRPH_FORMAT_AI88 3
57
+
# define SI_GRPH_FORMAT_MONO16 4
58
+
# define SI_GRPH_FORMAT_BGRA5551 5
59
+
/* 32 BPP */
60
+
# define SI_GRPH_FORMAT_ARGB8888 0
61
+
# define SI_GRPH_FORMAT_ARGB2101010 1
62
+
# define SI_GRPH_FORMAT_32BPP_DIG 2
63
+
# define SI_GRPH_FORMAT_8B_ARGB2101010 3
64
+
# define SI_GRPH_FORMAT_BGRA1010102 4
65
+
# define SI_GRPH_FORMAT_8B_BGRA1010102 5
66
+
# define SI_GRPH_FORMAT_RGB111110 6
67
+
# define SI_GRPH_FORMAT_BGR101111 7
68
+
# define SI_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
69
+
# define SI_ADDR_SURF_BANK_HEIGHT_1 0
70
+
# define SI_ADDR_SURF_BANK_HEIGHT_2 1
71
+
# define SI_ADDR_SURF_BANK_HEIGHT_4 2
72
+
# define SI_ADDR_SURF_BANK_HEIGHT_8 3
73
+
# define SI_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
74
+
# define SI_ADDR_SURF_TILE_SPLIT_64B 0
75
+
# define SI_ADDR_SURF_TILE_SPLIT_128B 1
76
+
# define SI_ADDR_SURF_TILE_SPLIT_256B 2
77
+
# define SI_ADDR_SURF_TILE_SPLIT_512B 3
78
+
# define SI_ADDR_SURF_TILE_SPLIT_1KB 4
79
+
# define SI_ADDR_SURF_TILE_SPLIT_2KB 5
80
+
# define SI_ADDR_SURF_TILE_SPLIT_4KB 6
81
+
# define SI_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
82
+
# define SI_ADDR_SURF_MACRO_TILE_ASPECT_1 0
83
+
# define SI_ADDR_SURF_MACRO_TILE_ASPECT_2 1
84
+
# define SI_ADDR_SURF_MACRO_TILE_ASPECT_4 2
85
+
# define SI_ADDR_SURF_MACRO_TILE_ASPECT_8 3
86
+
# define SI_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
87
+
# define SI_GRPH_ARRAY_LINEAR_GENERAL 0
88
+
# define SI_GRPH_ARRAY_LINEAR_ALIGNED 1
89
+
# define SI_GRPH_ARRAY_1D_TILED_THIN1 2
90
+
# define SI_GRPH_ARRAY_2D_TILED_THIN1 4
91
+
# define SI_GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
92
+
# define SI_ADDR_SURF_P2 0
93
+
# define SI_ADDR_SURF_P4_8x16 4
94
+
# define SI_ADDR_SURF_P4_16x16 5
95
+
# define SI_ADDR_SURF_P4_16x32 6
96
+
# define SI_ADDR_SURF_P4_32x32 7
97
+
# define SI_ADDR_SURF_P8_16x16_8x16 8
98
+
# define SI_ADDR_SURF_P8_16x32_8x16 9
99
+
# define SI_ADDR_SURF_P8_32x32_8x16 10
100
+
# define SI_ADDR_SURF_P8_16x32_16x16 11
101
+
# define SI_ADDR_SURF_P8_32x32_16x16 12
102
+
# define SI_ADDR_SURF_P8_32x32_16x32 13
103
+
# define SI_ADDR_SURF_P8_32x64_32x32 14
104
+
33
105
#endif
-4
include/drm/drm_pciids.h
-4
include/drm/drm_pciids.h
···
1
-
/*
2
-
This file is auto-generated from the drm_pciids.txt in the DRM CVS
3
-
Please contact dri-devel@lists.sf.net to add new cards to this list
4
-
*/
5
1
#define radeon_PCI_IDS \
6
2
{0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
7
3
{0x1002, 0x3151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+4
include/linux/vga_switcheroo.h
+4
include/linux/vga_switcheroo.h
···
7
7
* vga_switcheroo.h - Support for laptop with dual GPU using one set of outputs
8
8
*/
9
9
10
+
#ifndef _LINUX_VGA_SWITCHEROO_H_
11
+
#define _LINUX_VGA_SWITCHEROO_H_
12
+
10
13
#include <linux/fb.h>
11
14
12
15
struct pci_dev;
···
76
73
77
74
78
75
#endif
76
+
#endif /* _LINUX_VGA_SWITCHEROO_H_ */