tjh.dev / kernel
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drm/amd/pm: Add debug message callback

Add callback in message control to send message through debug mailbox.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Lijo Lazar and committed by
Alex Deucher 2f0d5eca b9b393c6

+32
+12
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
··· 557 557 #define SMU_MSG_FLAG_ASYNC BIT(0) /* Async send - skip post-poll */ 558 558 #define SMU_MSG_FLAG_LOCK_HELD BIT(1) /* Caller holds ctl->lock */ 559 559 560 + /* smu_msg_ctl flags */ 561 + #define SMU_MSG_CTL_DEBUG_MAILBOX BIT(0) /* Debug mailbox supported */ 562 + 560 563 struct smu_msg_ctl; 561 564 /** 562 565 * struct smu_msg_config - IP-level register configuration ··· 567 564 * @resp_reg: Response register offset 568 565 * @arg_regs: Argument register offsets (up to SMU_MSG_MAX_ARGS) 569 566 * @num_arg_regs: Number of argument registers available 567 + * @debug_msg_reg: Debug message register offset 568 + * @debug_resp_reg: Debug response register offset 569 + * @debug_param_reg: Debug parameter register offset 570 570 */ 571 571 struct smu_msg_config { 572 572 u32 msg_reg; 573 573 u32 resp_reg; 574 574 u32 arg_regs[SMU_MSG_MAX_ARGS]; 575 575 int num_arg_regs; 576 + u32 debug_msg_reg; 577 + u32 debug_resp_reg; 578 + u32 debug_param_reg; 576 579 }; 577 580 578 581 /** ··· 606 597 * @send_msg: send message protocol 607 598 * @wait_response: wait for response (for split send/wait cases) 608 599 * @decode_response: Convert response register value to errno 600 + * @send_debug_msg: send debug message 609 601 */ 610 602 struct smu_msg_ops { 611 603 int (*send_msg)(struct smu_msg_ctl *ctl, struct smu_msg_args *args); 612 604 int (*wait_response)(struct smu_msg_ctl *ctl, u32 timeout_us); 613 605 int (*decode_response)(u32 resp); 606 + int (*send_debug_msg)(struct smu_msg_ctl *ctl, u32 msg, u32 param); 614 607 }; 615 608 616 609 /** ··· 628 617 const struct smu_msg_ops *ops; 629 618 const struct cmn2asic_msg_mapping *message_map; 630 619 u32 default_timeout; 620 + u32 flags; 631 621 }; 632 622 633 623 struct stb_context {
+20
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
··· 83 83 84 84 #define SMU_RESP_UNEXP (~0U) 85 85 86 + static int smu_msg_v1_send_debug_msg(struct smu_msg_ctl *ctl, u32 msg, u32 param) 87 + { 88 + struct amdgpu_device *adev = ctl->smu->adev; 89 + struct smu_msg_config *cfg = &ctl->config; 90 + 91 + if (!(ctl->flags & SMU_MSG_CTL_DEBUG_MAILBOX)) 92 + return -EOPNOTSUPP; 93 + 94 + mutex_lock(&ctl->lock); 95 + 96 + WREG32(cfg->debug_param_reg, param); 97 + WREG32(cfg->debug_msg_reg, msg); 98 + WREG32(cfg->debug_resp_reg, 0); 99 + 100 + mutex_unlock(&ctl->lock); 101 + 102 + return 0; 103 + } 104 + 86 105 static int __smu_cmn_send_debug_msg(struct smu_context *smu, 87 106 u32 msg, 88 107 u32 param) ··· 560 541 .send_msg = smu_msg_v1_send_msg, 561 542 .wait_response = smu_msg_v1_wait_response, 562 543 .decode_response = smu_msg_v1_decode_response, 544 + .send_debug_msg = smu_msg_v1_send_debug_msg, 563 545 }; 564 546 565 547 int smu_msg_wait_response(struct smu_msg_ctl *ctl, u32 timeout_us)