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serial: sh-sci: Add support for RZ/V2H(P) SoC

Add serial support for RZ/V2H(P) SoC with earlycon.

The SCIF interface in the Renesas RZ/V2H(P) is similar to that available
in the RZ/G2L (R9A07G044) SoC, with the following differences:

- RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready
and two for Rx and Tx buffer full, all of which are edge-triggered.
- RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both
synchronous and asynchronous modes.
- There are differences in the configuration of certain registers such
as SCSMR, SCFCR, and SCSPTR between the two SoCs.

To handle these differences on RZ/V2H(P) SoC SCIx_RZV2H_SCIF_REGTYPE
is added.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240604170513.522631-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Lad Prabhakar and committed by
Greg Kroah-Hartman 2f50304e 964a80cf

+51 -5
+50 -5
drivers/tty/serial/sh-sci.c
··· 318 318 }, 319 319 320 320 /* 321 + * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC 322 + * with below differences, 323 + * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI, 324 + * TEI-DRI, RXI-EDGE and TXI-EDGE. 325 + * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode. 326 + * - SCFCR register does not have SCFCR_MCE bit. 327 + * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO. 328 + */ 329 + [SCIx_RZV2H_SCIF_REGTYPE] = { 330 + .regs = { 331 + [SCSMR] = { 0x00, 16 }, 332 + [SCBRR] = { 0x02, 8 }, 333 + [SCSCR] = { 0x04, 16 }, 334 + [SCxTDR] = { 0x06, 8 }, 335 + [SCxSR] = { 0x08, 16 }, 336 + [SCxRDR] = { 0x0a, 8 }, 337 + [SCFCR] = { 0x0c, 16 }, 338 + [SCFDR] = { 0x0e, 16 }, 339 + [SCSPTR] = { 0x10, 16 }, 340 + [SCLSR] = { 0x12, 16 }, 341 + [SEMR] = { 0x14, 8 }, 342 + }, 343 + .fifosize = 16, 344 + .overrun_reg = SCLSR, 345 + .overrun_mask = SCLSR_ORER, 346 + .sampling_rate_mask = SCI_SR(32), 347 + .error_mask = SCIF_DEFAULT_ERROR_MASK, 348 + .error_clear = SCIF_ERROR_CLEAR, 349 + }, 350 + 351 + /* 321 352 * Common SH-3 SCIF definitions. 322 353 */ 323 354 [SCIx_SH3_SCIF_REGTYPE] = { ··· 788 757 } 789 758 sci_serial_out(port, SCPDR, data); 790 759 sci_serial_out(port, SCPCR, ctrl); 791 - } else if (sci_getreg(port, SCSPTR)->size) { 760 + } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) { 792 761 u16 status = sci_serial_in(port, SCSPTR); 793 762 794 763 /* RTS# is always output; and active low, unless autorts */ ··· 2155 2124 2156 2125 if (!(mctrl & TIOCM_RTS)) { 2157 2126 /* Disable Auto RTS */ 2158 - sci_serial_out(port, SCFCR, 2159 - sci_serial_in(port, SCFCR) & ~SCFCR_MCE); 2127 + if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) 2128 + sci_serial_out(port, SCFCR, 2129 + sci_serial_in(port, SCFCR) & ~SCFCR_MCE); 2160 2130 2161 2131 /* Clear RTS */ 2162 2132 sci_set_rts(port, 0); ··· 2169 2137 } 2170 2138 2171 2139 /* Enable Auto RTS */ 2172 - sci_serial_out(port, SCFCR, 2173 - sci_serial_in(port, SCFCR) | SCFCR_MCE); 2140 + if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) 2141 + sci_serial_out(port, SCFCR, 2142 + sci_serial_in(port, SCFCR) | SCFCR_MCE); 2174 2143 } else { 2175 2144 /* Set RTS */ 2176 2145 sci_set_rts(port, 1); ··· 3258 3225 .compatible = "renesas,scif-r9a07g044", 3259 3226 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3260 3227 }, 3228 + { 3229 + .compatible = "renesas,scif-r9a09g057", 3230 + .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE), 3231 + }, 3261 3232 /* Family-specific types */ 3262 3233 { 3263 3234 .compatible = "renesas,rcar-gen1-scif", ··· 3570 3533 return early_console_setup(device, PORT_SCIF); 3571 3534 } 3572 3535 3536 + static int __init rzv2hscif_early_console_setup(struct earlycon_device *device, 3537 + const char *opt) 3538 + { 3539 + port_cfg.regtype = SCIx_RZV2H_SCIF_REGTYPE; 3540 + return early_console_setup(device, PORT_SCIF); 3541 + } 3542 + 3573 3543 static int __init scifa_early_console_setup(struct earlycon_device *device, 3574 3544 const char *opt) 3575 3545 { ··· 3597 3553 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3598 3554 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3599 3555 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3556 + OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup); 3600 3557 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3601 3558 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3602 3559 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
+1
include/linux/serial_sci.h
··· 37 37 SCIx_SH7705_SCIF_REGTYPE, 38 38 SCIx_HSCIF_REGTYPE, 39 39 SCIx_RZ_SCIFA_REGTYPE, 40 + SCIx_RZV2H_SCIF_REGTYPE, 40 41 41 42 SCIx_NR_REGTYPES, 42 43 };