Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'dsa-mxl-gsw1xx-support-r-g-mii-slew-rate-configuration'
Alexander Sverdlin says:
====================
dsa: mxl-gsw1xx: Support R(G)MII slew rate configuration
Maxlinear GSW1xx switches offer slew rate configuration bits for R(G)MII
interface. The default state of the configuration bits is "normal", while
"slow" can be used to reduce the radiated emissions. Add the support for
the latter option into the driver as well as the new DT bindings.
====================
Link: https://patch.msgid.link/20260114104509.618984-1-alexander.sverdlin@siemens.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+71
+22
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
+22
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
···
106
106
unevaluatedProperties: false
107
107
108
108
properties:
109
+
maxlinear,slew-rate-txc:
110
+
$ref: /schemas/types.yaml#/definitions/uint32
111
+
enum: [0, 1]
112
+
description: |
113
+
RMII/RGMII TX Clock Slew Rate:
114
+
115
+
0: Normal
116
+
1: Slow
117
+
118
+
If not present, the configuration made by the switch bootloader is
119
+
preserved.
120
+
maxlinear,slew-rate-txd:
121
+
$ref: /schemas/types.yaml#/definitions/uint32
122
+
enum: [0, 1]
123
+
description: |
124
+
RMII/RGMII TX Non-Clock PAD Slew Rate:
125
+
126
+
0: Normal
127
+
1: Slow
128
+
129
+
If not present, the configuration made by the switch bootloader is
130
+
preserved.
109
131
maxlinear,rmii-refclk-out:
110
132
type: boolean
111
133
description:
+1
drivers/net/dsa/lantiq/lantiq_gswip.h
+1
drivers/net/dsa/lantiq/lantiq_gswip.h
+6
drivers/net/dsa/lantiq/lantiq_gswip_common.c
+6
drivers/net/dsa/lantiq/lantiq_gswip_common.c
···
425
425
struct gswip_priv *priv = ds->priv;
426
426
int err;
427
427
428
+
if (priv->hw_info->port_setup) {
429
+
err = priv->hw_info->port_setup(ds, port);
430
+
if (err)
431
+
return err;
432
+
}
433
+
428
434
if (!dsa_is_cpu_port(ds, port)) {
429
435
err = gswip_add_single_port_br(priv, port, true);
430
436
if (err)
+40
drivers/net/dsa/lantiq/mxl-gsw1xx.c
+40
drivers/net/dsa/lantiq/mxl-gsw1xx.c
···
559
559
}
560
560
}
561
561
562
+
static int gsw1xx_rmii_slew_rate(const struct device_node *np, struct gsw1xx_priv *priv,
563
+
const char *prop, u16 mask)
564
+
{
565
+
u32 rate;
566
+
int ret;
567
+
568
+
ret = of_property_read_u32(np, prop, &rate);
569
+
/* Optional property */
570
+
if (ret == -EINVAL)
571
+
return 0;
572
+
if (ret < 0 || rate > 1) {
573
+
dev_err(&priv->mdio_dev->dev, "Invalid %s value\n", prop);
574
+
return (ret < 0) ? ret : -EINVAL;
575
+
}
576
+
577
+
return regmap_update_bits(priv->shell, GSW1XX_SHELL_RGMII_SLEW_CFG, mask, mask * rate);
578
+
}
579
+
580
+
static int gsw1xx_port_setup(struct dsa_switch *ds, int port)
581
+
{
582
+
struct dsa_port *dp = dsa_to_port(ds, port);
583
+
struct device_node *np = dp->dn;
584
+
struct gsw1xx_priv *gsw1xx_priv;
585
+
struct gswip_priv *gswip_priv;
586
+
587
+
if (dp->index != GSW1XX_MII_PORT)
588
+
return 0;
589
+
590
+
gswip_priv = ds->priv;
591
+
gsw1xx_priv = container_of(gswip_priv, struct gsw1xx_priv, gswip);
592
+
593
+
return gsw1xx_rmii_slew_rate(np, gsw1xx_priv,
594
+
"maxlinear,slew-rate-txc", RGMII_SLEW_CFG_DRV_TXC) ?:
595
+
gsw1xx_rmii_slew_rate(np, gsw1xx_priv,
596
+
"maxlinear,slew-rate-txd", RGMII_SLEW_CFG_DRV_TXD);
597
+
}
598
+
562
599
static struct regmap *gsw1xx_regmap_init(struct gsw1xx_priv *priv,
563
600
const char *name,
564
601
unsigned int reg_base,
···
744
707
.mac_select_pcs = gsw1xx_phylink_mac_select_pcs,
745
708
.phylink_get_caps = &gsw1xx_phylink_get_caps,
746
709
.supports_2500m = true,
710
+
.port_setup = gsw1xx_port_setup,
747
711
.pce_microcode = &gsw1xx_pce_microcode,
748
712
.pce_microcode_size = ARRAY_SIZE(gsw1xx_pce_microcode),
749
713
.tag_protocol = DSA_TAG_PROTO_MXL_GSW1XX,
···
758
720
.mac_select_pcs = gsw1xx_phylink_mac_select_pcs,
759
721
.phylink_get_caps = &gsw1xx_phylink_get_caps,
760
722
.supports_2500m = true,
723
+
.port_setup = gsw1xx_port_setup,
761
724
.pce_microcode = &gsw1xx_pce_microcode,
762
725
.pce_microcode_size = ARRAY_SIZE(gsw1xx_pce_microcode),
763
726
.tag_protocol = DSA_TAG_PROTO_MXL_GSW1XX,
···
771
732
.mii_port_reg_offset = -GSW1XX_MII_PORT,
772
733
.mac_select_pcs = gsw1xx_phylink_mac_select_pcs,
773
734
.phylink_get_caps = gsw1xx_phylink_get_caps,
735
+
.port_setup = gsw1xx_port_setup,
774
736
.pce_microcode = &gsw1xx_pce_microcode,
775
737
.pce_microcode_size = ARRAY_SIZE(gsw1xx_pce_microcode),
776
738
.tag_protocol = DSA_TAG_PROTO_MXL_GSW1XX,
+2
drivers/net/dsa/lantiq/mxl-gsw1xx.h
+2
drivers/net/dsa/lantiq/mxl-gsw1xx.h
···
110
110
#define GSW1XX_RST_REQ_SGMII_SHELL BIT(5)
111
111
/* RGMII PAD Slew Control Register */
112
112
#define GSW1XX_SHELL_RGMII_SLEW_CFG 0x78
113
+
#define RGMII_SLEW_CFG_DRV_TXC BIT(2)
114
+
#define RGMII_SLEW_CFG_DRV_TXD BIT(3)
113
115
#define RGMII_SLEW_CFG_RX_2_5_V BIT(4)
114
116
#define RGMII_SLEW_CFG_TX_2_5_V BIT(5)
115
117