Merge tag 'i3c/for-6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux

+11

Documentation/ABI/testing/sysfs-bus-i3c

··· 161 161 Description: 162 162 These directories are just symbolic links to 163 163 /sys/bus/i3c/devices/i3c-<bus-id>/<bus-id>-<device-pid>. 164 + 165 + What: /sys/bus/i3c/devices/i3c-<bus-id>/<bus-id>-<device-pid>/dev_nack_retry_count 166 + KernelVersion: 6.18 167 + Contact: linux-i3c@vger.kernel.org 168 + Description: 169 + Expose the dev_nak_retry_count which controls the number of 170 + automatic retries that will be performed by the controller when 171 + the target device returns a NACK response. A value of 0 disables 172 + the automatic retries. Exist only when I3C constroller supports 173 + this retry on nack feature. 174 +

+43 -3

drivers/i3c/device.c

··· 46 46 return -EINVAL; 47 47 } 48 48 49 + ret = i3c_bus_rpm_get(dev->bus); 50 + if (ret) 51 + return ret; 52 + 49 53 i3c_bus_normaluse_lock(dev->bus); 50 54 ret = i3c_dev_do_xfers_locked(dev->desc, xfers, nxfers, mode); 51 55 i3c_bus_normaluse_unlock(dev->bus); 56 + 57 + i3c_bus_rpm_put(dev->bus); 52 58 53 59 return ret; 54 60 } ··· 72 66 { 73 67 int ret; 74 68 69 + ret = i3c_bus_rpm_get(dev->bus); 70 + if (ret) 71 + return ret; 72 + 75 73 i3c_bus_normaluse_lock(dev->bus); 76 74 ret = i3c_dev_setdasa_locked(dev->desc); 77 75 i3c_bus_normaluse_unlock(dev->bus); 76 + 77 + i3c_bus_rpm_put(dev->bus); 78 78 79 79 return ret; 80 80 } ··· 118 106 */ 119 107 int i3c_device_disable_ibi(struct i3c_device *dev) 120 108 { 121 - int ret = -ENOENT; 109 + int ret; 110 + 111 + if (i3c_bus_rpm_ibi_allowed(dev->bus)) { 112 + ret = i3c_bus_rpm_get(dev->bus); 113 + if (ret) 114 + return ret; 115 + } 122 116 123 117 i3c_bus_normaluse_lock(dev->bus); 124 118 if (dev->desc) { 125 119 mutex_lock(&dev->desc->ibi_lock); 126 120 ret = i3c_dev_disable_ibi_locked(dev->desc); 127 121 mutex_unlock(&dev->desc->ibi_lock); 122 + } else { 123 + ret = -ENOENT; 128 124 } 129 125 i3c_bus_normaluse_unlock(dev->bus); 126 + 127 + if (!ret || i3c_bus_rpm_ibi_allowed(dev->bus)) 128 + i3c_bus_rpm_put(dev->bus); 130 129 131 130 return ret; 132 131 } ··· 158 135 */ 159 136 int i3c_device_enable_ibi(struct i3c_device *dev) 160 137 { 161 - int ret = -ENOENT; 138 + int ret; 139 + 140 + ret = i3c_bus_rpm_get(dev->bus); 141 + if (ret) 142 + return ret; 162 143 163 144 i3c_bus_normaluse_lock(dev->bus); 164 145 if (dev->desc) { 165 146 mutex_lock(&dev->desc->ibi_lock); 166 147 ret = i3c_dev_enable_ibi_locked(dev->desc); 167 148 mutex_unlock(&dev->desc->ibi_lock); 149 + } else { 150 + ret = -ENOENT; 168 151 } 169 152 i3c_bus_normaluse_unlock(dev->bus); 153 + 154 + if (ret || i3c_bus_rpm_ibi_allowed(dev->bus)) 155 + i3c_bus_rpm_put(dev->bus); 170 156 171 157 return ret; 172 158 } ··· 195 163 int i3c_device_request_ibi(struct i3c_device *dev, 196 164 const struct i3c_ibi_setup *req) 197 165 { 198 - int ret = -ENOENT; 166 + int ret; 199 167 200 168 if (!req->handler || !req->num_slots) 201 169 return -EINVAL; 170 + 171 + ret = i3c_bus_rpm_get(dev->bus); 172 + if (ret) 173 + return ret; 202 174 203 175 i3c_bus_normaluse_lock(dev->bus); 204 176 if (dev->desc) { 205 177 mutex_lock(&dev->desc->ibi_lock); 206 178 ret = i3c_dev_request_ibi_locked(dev->desc, req); 207 179 mutex_unlock(&dev->desc->ibi_lock); 180 + } else { 181 + ret = -ENOENT; 208 182 } 209 183 i3c_bus_normaluse_unlock(dev->bus); 184 + 185 + i3c_bus_rpm_put(dev->bus); 210 186 211 187 return ret; 212 188 }

+4

drivers/i3c/internals.h

··· 11 11 #include <linux/i3c/master.h> 12 12 #include <linux/io.h> 13 13 14 + int __must_check i3c_bus_rpm_get(struct i3c_bus *bus); 15 + void i3c_bus_rpm_put(struct i3c_bus *bus); 16 + bool i3c_bus_rpm_ibi_allowed(struct i3c_bus *bus); 17 + 14 18 void i3c_bus_normaluse_lock(struct i3c_bus *bus); 15 19 void i3c_bus_normaluse_unlock(struct i3c_bus *bus); 16 20

+181 -32

drivers/i3c/master.c

··· 106 106 return container_of(dev, struct i3c_master_controller, dev); 107 107 } 108 108 109 + static int __must_check i3c_master_rpm_get(struct i3c_master_controller *master) 110 + { 111 + int ret = master->rpm_allowed ? pm_runtime_resume_and_get(master->dev.parent) : 0; 112 + 113 + if (ret < 0) { 114 + dev_err(master->dev.parent, "runtime resume failed, error %d\n", ret); 115 + return ret; 116 + } 117 + return 0; 118 + } 119 + 120 + static void i3c_master_rpm_put(struct i3c_master_controller *master) 121 + { 122 + if (master->rpm_allowed) 123 + pm_runtime_put_autosuspend(master->dev.parent); 124 + } 125 + 126 + int i3c_bus_rpm_get(struct i3c_bus *bus) 127 + { 128 + return i3c_master_rpm_get(i3c_bus_to_i3c_master(bus)); 129 + } 130 + 131 + void i3c_bus_rpm_put(struct i3c_bus *bus) 132 + { 133 + i3c_master_rpm_put(i3c_bus_to_i3c_master(bus)); 134 + } 135 + 136 + bool i3c_bus_rpm_ibi_allowed(struct i3c_bus *bus) 137 + { 138 + return i3c_bus_to_i3c_master(bus)->rpm_ibi_allowed; 139 + } 140 + 109 141 static const struct device_type i3c_device_type; 110 142 111 143 static struct i3c_bus *dev_to_i3cbus(struct device *dev) ··· 643 611 if (!master->ops->enable_hotjoin || !master->ops->disable_hotjoin) 644 612 return -EINVAL; 645 613 614 + if (enable || master->rpm_ibi_allowed) { 615 + ret = i3c_master_rpm_get(master); 616 + if (ret) 617 + return ret; 618 + } 619 + 646 620 i3c_bus_normaluse_lock(&master->bus); 647 621 648 622 if (enable) ··· 656 618 else 657 619 ret = master->ops->disable_hotjoin(master); 658 620 659 - master->hotjoin = enable; 621 + if (!ret) 622 + master->hotjoin = enable; 660 623 661 624 i3c_bus_normaluse_unlock(&master->bus); 625 + 626 + if ((enable && ret) || (!enable && !ret) || master->rpm_ibi_allowed) 627 + i3c_master_rpm_put(master); 662 628 663 629 return ret; 664 630 } ··· 724 682 } 725 683 726 684 static DEVICE_ATTR_RW(hotjoin); 685 + 686 + static ssize_t dev_nack_retry_count_show(struct device *dev, 687 + struct device_attribute *attr, char *buf) 688 + { 689 + return sysfs_emit(buf, "%u\n", dev_to_i3cmaster(dev)->dev_nack_retry_count); 690 + } 691 + 692 + static ssize_t dev_nack_retry_count_store(struct device *dev, 693 + struct device_attribute *attr, 694 + const char *buf, size_t count) 695 + { 696 + struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 697 + struct i3c_master_controller *master = dev_to_i3cmaster(dev); 698 + unsigned long val; 699 + int ret; 700 + 701 + ret = kstrtoul(buf, 0, &val); 702 + if (ret) 703 + return ret; 704 + 705 + i3c_bus_maintenance_lock(i3cbus); 706 + ret = master->ops->set_dev_nack_retry(master, val); 707 + i3c_bus_maintenance_unlock(i3cbus); 708 + 709 + if (ret) 710 + return ret; 711 + 712 + master->dev_nack_retry_count = val; 713 + 714 + return count; 715 + } 716 + 717 + static DEVICE_ATTR_RW(dev_nack_retry_count); 727 718 728 719 static struct attribute *i3c_masterdev_attrs[] = { 729 720 &dev_attr_mode.attr, ··· 1768 1693 } 1769 1694 1770 1695 /** 1696 + * i3c_master_do_daa_ext() - Dynamic Address Assignment (extended version) 1697 + * @master: controller 1698 + * @rstdaa: whether to first perform Reset of Dynamic Addresses (RSTDAA) 1699 + * 1700 + * Perform Dynamic Address Assignment with optional support for System 1701 + * Hibernation (@rstdaa is true). 1702 + * 1703 + * After System Hibernation, Dynamic Addresses can have been reassigned at boot 1704 + * time to different values. A simple strategy is followed to handle that. 1705 + * Perform a Reset of Dynamic Addresses (RSTDAA) followed by the normal DAA 1706 + * procedure which has provision for reassigning addresses that differ from the 1707 + * previously recorded addresses. 1708 + * 1709 + * Return: a 0 in case of success, an negative error code otherwise. 1710 + */ 1711 + int i3c_master_do_daa_ext(struct i3c_master_controller *master, bool rstdaa) 1712 + { 1713 + int rstret = 0; 1714 + int ret; 1715 + 1716 + ret = i3c_master_rpm_get(master); 1717 + if (ret) 1718 + return ret; 1719 + 1720 + i3c_bus_maintenance_lock(&master->bus); 1721 + 1722 + if (rstdaa) { 1723 + rstret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR); 1724 + if (rstret == I3C_ERROR_M2) 1725 + rstret = 0; 1726 + } 1727 + 1728 + ret = master->ops->do_daa(master); 1729 + 1730 + i3c_bus_maintenance_unlock(&master->bus); 1731 + 1732 + if (ret) 1733 + goto out; 1734 + 1735 + i3c_bus_normaluse_lock(&master->bus); 1736 + i3c_master_register_new_i3c_devs(master); 1737 + i3c_bus_normaluse_unlock(&master->bus); 1738 + out: 1739 + i3c_master_rpm_put(master); 1740 + 1741 + return rstret ?: ret; 1742 + } 1743 + EXPORT_SYMBOL_GPL(i3c_master_do_daa_ext); 1744 + 1745 + /** 1771 1746 * i3c_master_do_daa() - do a DAA (Dynamic Address Assignment) 1772 1747 * @master: master doing the DAA 1773 1748 * 1774 - * This function is instantiating an I3C device object and adding it to the 1775 - * I3C device list. All device information are automatically retrieved using 1749 + * This function instantiates I3C device objects and adds them to the 1750 + * I3C device list. All device information is automatically retrieved using 1776 1751 * standard CCC commands. 1777 - * 1778 - * The I3C device object is returned in case the master wants to attach 1779 - * private data to it using i3c_dev_set_master_data(). 1780 - * 1781 - * This function must be called with the bus lock held in write mode. 1782 1752 * 1783 1753 * Return: a 0 in case of success, an negative error code otherwise. 1784 1754 */ 1785 1755 int i3c_master_do_daa(struct i3c_master_controller *master) 1786 1756 { 1787 - int ret; 1788 - 1789 - i3c_bus_maintenance_lock(&master->bus); 1790 - ret = master->ops->do_daa(master); 1791 - i3c_bus_maintenance_unlock(&master->bus); 1792 - 1793 - if (ret) 1794 - return ret; 1795 - 1796 - i3c_bus_normaluse_lock(&master->bus); 1797 - i3c_master_register_new_i3c_devs(master); 1798 - i3c_bus_normaluse_unlock(&master->bus); 1799 - 1800 - return 0; 1757 + return i3c_master_do_daa_ext(master, false); 1801 1758 } 1802 1759 EXPORT_SYMBOL_GPL(i3c_master_do_daa); 1803 1760 ··· 2171 2064 2172 2065 static void i3c_master_bus_cleanup(struct i3c_master_controller *master) 2173 2066 { 2174 - if (master->ops->bus_cleanup) 2175 - master->ops->bus_cleanup(master); 2067 + if (master->ops->bus_cleanup) { 2068 + int ret = i3c_master_rpm_get(master); 2069 + 2070 + if (ret) { 2071 + dev_err(&master->dev, 2072 + "runtime resume error: master bus_cleanup() not done\n"); 2073 + } else { 2074 + master->ops->bus_cleanup(master); 2075 + i3c_master_rpm_put(master); 2076 + } 2077 + } 2176 2078 2177 2079 i3c_master_detach_free_devs(master); 2178 2080 } ··· 2486 2370 { 2487 2371 struct device *dev = &master->dev; 2488 2372 struct device_node *i3cbus_np = dev->of_node; 2489 - struct device_node *node; 2490 2373 int ret; 2491 2374 u32 val; 2492 2375 2493 2376 if (!i3cbus_np) 2494 2377 return 0; 2495 2378 2496 - for_each_available_child_of_node(i3cbus_np, node) { 2379 + for_each_available_child_of_node_scoped(i3cbus_np, node) { 2497 2380 ret = of_i3c_master_add_dev(master, node); 2498 - if (ret) { 2499 - of_node_put(node); 2381 + if (ret) 2500 2382 return ret; 2501 - } 2502 2383 } 2503 2384 2504 2385 /* ··· 2533 2420 return -EOPNOTSUPP; 2534 2421 } 2535 2422 2423 + ret = i3c_master_rpm_get(master); 2424 + if (ret) 2425 + return ret; 2426 + 2536 2427 i3c_bus_normaluse_lock(&master->bus); 2537 2428 dev = i3c_master_find_i2c_dev_by_addr(master, addr); 2538 2429 if (!dev) ··· 2544 2427 else 2545 2428 ret = master->ops->i2c_xfers(dev, xfers, nxfers); 2546 2429 i3c_bus_normaluse_unlock(&master->bus); 2430 + 2431 + i3c_master_rpm_put(master); 2547 2432 2548 2433 return ret ? ret : nxfers; 2549 2434 } ··· 2649 2530 2650 2531 master = i2c_adapter_to_i3c_master(adap); 2651 2532 2533 + ret = i3c_master_rpm_get(master); 2534 + if (ret) 2535 + return ret; 2536 + 2652 2537 i3c_bus_maintenance_lock(&master->bus); 2653 2538 switch (action) { 2654 2539 case BUS_NOTIFY_ADD_DEVICE: ··· 2665 2542 ret = -EINVAL; 2666 2543 } 2667 2544 i3c_bus_maintenance_unlock(&master->bus); 2545 + 2546 + i3c_master_rpm_put(master); 2668 2547 2669 2548 return ret; 2670 2549 } ··· 3005 2880 INIT_LIST_HEAD(&master->boardinfo.i2c); 3006 2881 INIT_LIST_HEAD(&master->boardinfo.i3c); 3007 2882 2883 + ret = i3c_master_rpm_get(master); 2884 + if (ret) 2885 + return ret; 2886 + 3008 2887 device_initialize(&master->dev); 3009 - dev_set_name(&master->dev, "i3c-%d", i3cbus->id); 3010 2888 3011 2889 master->dev.dma_mask = parent->dma_mask; 3012 2890 master->dev.coherent_dma_mask = parent->coherent_dma_mask; ··· 3018 2890 ret = i3c_bus_init(i3cbus, master->dev.of_node); 3019 2891 if (ret) 3020 2892 goto err_put_dev; 2893 + 2894 + dev_set_name(&master->dev, "i3c-%d", i3cbus->id); 3021 2895 3022 2896 ret = of_populate_i3c_bus(master); 3023 2897 if (ret) ··· 3089 2959 i3c_master_register_new_i3c_devs(master); 3090 2960 i3c_bus_normaluse_unlock(&master->bus); 3091 2961 2962 + if (master->ops->set_dev_nack_retry) 2963 + device_create_file(&master->dev, &dev_attr_dev_nack_retry_count); 2964 + 2965 + i3c_master_rpm_put(master); 2966 + 3092 2967 return 0; 3093 2968 3094 2969 err_del_dev: ··· 3103 2968 i3c_master_bus_cleanup(master); 3104 2969 3105 2970 err_put_dev: 2971 + i3c_master_rpm_put(master); 3106 2972 put_device(&master->dev); 3107 2973 3108 2974 return ret; ··· 3119 2983 void i3c_master_unregister(struct i3c_master_controller *master) 3120 2984 { 3121 2985 i3c_bus_notify(&master->bus, I3C_NOTIFY_BUS_REMOVE); 2986 + 2987 + if (master->ops->set_dev_nack_retry) 2988 + device_remove_file(&master->dev, &dev_attr_dev_nack_retry_count); 3122 2989 3123 2990 i3c_master_i2c_adapter_cleanup(master); 3124 2991 i3c_master_unregister_i3c_devs(master); ··· 3251 3112 if (!dev->ibi) 3252 3113 return; 3253 3114 3254 - if (WARN_ON(dev->ibi->enabled)) 3255 - WARN_ON(i3c_dev_disable_ibi_locked(dev)); 3115 + if (dev->ibi->enabled) { 3116 + int ret; 3117 + 3118 + dev_err(&master->dev, "Freeing IBI that is still enabled\n"); 3119 + ret = i3c_master_rpm_get(master); 3120 + if (!ret) { 3121 + ret = i3c_dev_disable_ibi_locked(dev); 3122 + i3c_master_rpm_put(master); 3123 + } 3124 + if (ret) 3125 + dev_err(&master->dev, "Failed to disable IBI before freeing\n"); 3126 + } 3256 3127 3257 3128 master->ops->free_ibi(dev); 3258 3129

+1

drivers/i3c/master/Kconfig

··· 69 69 tristate "MIPI I3C Host Controller Interface PCI support" 70 70 depends on MIPI_I3C_HCI 71 71 depends on PCI 72 + select MFD_CORE 72 73 help 73 74 Support for MIPI I3C Host Controller Interface compatible hardware 74 75 on the PCI bus.

+87 -34

drivers/i3c/master/dw-i3c-master.c

··· 5 5 * Author: Vitor Soares <vitor.soares@synopsys.com> 6 6 */ 7 7 8 + #include <linux/bitfield.h> 8 9 #include <linux/bitops.h> 9 10 #include <linux/clk.h> 10 11 #include <linux/completion.h> ··· 205 204 #define EXTENDED_CAPABILITY 0xe8 206 205 #define SLAVE_CONFIG 0xec 207 206 207 + #define DYN_ADDR_LO_MASK GENMASK(4, 0) 208 + #define DYN_ADDR_HI_MASK GENMASK(6, 5) 209 + #define IBI_SIR_BIT_MOD 32 /* 32-bit vector */ 210 + 211 + #define DW_I3C_DEV_NACK_RETRY_CNT_MAX 0x3 212 + #define DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK GENMASK(30, 29) 213 + #define DEV_ADDR_TABLE_DYNAMIC_MASK GENMASK(23, 16) 214 + #define DEV_ADDR_TABLE_STATIC_MASK GENMASK(6, 0) 208 215 #define DEV_ADDR_TABLE_IBI_MDB BIT(12) 209 216 #define DEV_ADDR_TABLE_SIR_REJECT BIT(13) 217 + #define DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(x) \ 218 + FIELD_PREP(DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK, (x)) 210 219 #define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31) 211 - #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) (((x) << 16) & GENMASK(23, 16)) 212 - #define DEV_ADDR_TABLE_STATIC_ADDR(x) ((x) & GENMASK(6, 0)) 220 + #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) FIELD_PREP(DEV_ADDR_TABLE_DYNAMIC_MASK, x) 221 + #define DEV_ADDR_TABLE_STATIC_ADDR(x) FIELD_PREP(DEV_ADDR_TABLE_STATIC_MASK, x) 213 222 #define DEV_ADDR_TABLE_LOC(start, idx) ((start) + ((idx) << 2)) 223 + #define DEV_ADDR_TABLE_GET_DYNAMIC_ADDR(x) FIELD_GET(DEV_ADDR_TABLE_DYNAMIC_MASK, x) 214 224 215 225 #define I3C_BUS_SDR1_SCL_RATE 8000000 216 226 #define I3C_BUS_SDR2_SCL_RATE 6000000 ··· 268 256 struct dw_i3c_drvdata { 269 257 u32 flags; 270 258 }; 259 + 260 + static inline u32 get_ibi_sir_bit_index(u8 addr) 261 + { 262 + u32 lo = FIELD_GET(DYN_ADDR_LO_MASK, addr); 263 + u32 hi = FIELD_GET(DYN_ADDR_HI_MASK, addr); 264 + 265 + return (lo + hi) % IBI_SIR_BIT_MOD; 266 + } 271 267 272 268 static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m, 273 269 const struct i3c_ccc_cmd *cmd) ··· 429 409 static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master, 430 410 struct dw_i3c_xfer *xfer) 431 411 { 432 - unsigned long flags; 433 - 434 412 init_completion(&xfer->comp); 435 - spin_lock_irqsave(&master->xferqueue.lock, flags); 413 + guard(spinlock_irqsave)(&master->xferqueue.lock); 436 414 if (master->xferqueue.cur) { 437 415 list_add_tail(&xfer->node, &master->xferqueue.list); 438 416 } else { 439 417 master->xferqueue.cur = xfer; 440 418 dw_i3c_master_start_xfer_locked(master); 441 419 } 442 - spin_unlock_irqrestore(&master->xferqueue.lock, flags); 443 420 } 444 421 445 422 static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master, ··· 461 444 static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master, 462 445 struct dw_i3c_xfer *xfer) 463 446 { 464 - unsigned long flags; 465 - 466 - spin_lock_irqsave(&master->xferqueue.lock, flags); 447 + guard(spinlock_irqsave)(&master->xferqueue.lock); 467 448 dw_i3c_master_dequeue_xfer_locked(master, xfer); 468 - spin_unlock_irqrestore(&master->xferqueue.lock, flags); 469 449 } 470 450 471 451 static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr) ··· 1113 1099 dev_err(master->dev, 1114 1100 "<%s> cannot resume i3c bus master, err: %d\n", 1115 1101 __func__, ret); 1102 + dw_i3c_master_free_xfer(xfer); 1116 1103 return ret; 1117 1104 } 1118 1105 ··· 1202 1187 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1203 1188 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1204 1189 struct dw_i3c_master *master = to_dw_i3c_master(m); 1205 - unsigned long flags; 1206 1190 1207 1191 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); 1208 1192 if (IS_ERR(data->ibi_pool)) 1209 1193 return PTR_ERR(data->ibi_pool); 1210 1194 1211 - spin_lock_irqsave(&master->devs_lock, flags); 1195 + guard(spinlock_irqsave)(&master->devs_lock); 1212 1196 master->devs[data->index].ibi_dev = dev; 1213 - spin_unlock_irqrestore(&master->devs_lock, flags); 1214 1197 1215 1198 return 0; 1216 1199 } ··· 1218 1205 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1219 1206 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1220 1207 struct dw_i3c_master *master = to_dw_i3c_master(m); 1221 - unsigned long flags; 1222 1208 1223 - spin_lock_irqsave(&master->devs_lock, flags); 1224 - master->devs[data->index].ibi_dev = NULL; 1225 - spin_unlock_irqrestore(&master->devs_lock, flags); 1209 + scoped_guard(spinlock_irqsave, &master->devs_lock) { 1210 + master->devs[data->index].ibi_dev = NULL; 1211 + } 1226 1212 1227 1213 i3c_generic_ibi_free_pool(data->ibi_pool); 1228 1214 data->ibi_pool = NULL; ··· 1248 1236 struct i3c_dev_desc *dev, 1249 1237 u8 idx, bool enable) 1250 1238 { 1251 - unsigned long flags; 1252 1239 u32 dat_entry, reg; 1253 1240 bool global; 1241 + u8 dynamic_addr; 1254 1242 1255 1243 dat_entry = DEV_ADDR_TABLE_LOC(master->datstartaddr, idx); 1256 1244 1257 - spin_lock_irqsave(&master->devs_lock, flags); 1245 + guard(spinlock_irqsave)(&master->devs_lock); 1258 1246 reg = readl(master->regs + dat_entry); 1247 + dynamic_addr = DEV_ADDR_TABLE_GET_DYNAMIC_ADDR(reg); 1248 + 1249 + if (!dynamic_addr) 1250 + dev_warn(master->dev, 1251 + "<%s> unassigned slave device, dynamic addr:%x\n", 1252 + __func__, dynamic_addr); 1253 + 1259 1254 if (enable) { 1260 1255 reg &= ~DEV_ADDR_TABLE_SIR_REJECT; 1261 1256 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) ··· 1275 1256 1276 1257 if (enable) { 1277 1258 global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL); 1278 - master->sir_rej_mask &= ~BIT(idx); 1259 + master->sir_rej_mask &= ~BIT(get_ibi_sir_bit_index(dynamic_addr)); 1279 1260 } else { 1280 1261 bool hj_rejected = !!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_HOT_JOIN_NACK); 1281 1262 1282 - master->sir_rej_mask |= BIT(idx); 1263 + master->sir_rej_mask |= BIT(get_ibi_sir_bit_index(dynamic_addr)); 1283 1264 global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL) && hj_rejected; 1284 1265 } 1285 1266 writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT); 1286 1267 1287 1268 if (global) 1288 1269 dw_i3c_master_enable_sir_signal(master, enable); 1289 - 1290 - 1291 - spin_unlock_irqrestore(&master->devs_lock, flags); 1292 1270 } 1293 1271 1294 1272 static int dw_i3c_master_enable_hotjoin(struct i3c_master_controller *m) ··· 1386 1370 struct dw_i3c_i2c_dev_data *data; 1387 1371 struct i3c_ibi_slot *slot; 1388 1372 struct i3c_dev_desc *dev; 1389 - unsigned long flags; 1390 1373 u8 addr, len; 1391 1374 int idx; 1392 1375 ··· 1403 1388 * a new platform op to validate it. 1404 1389 */ 1405 1390 1406 - spin_lock_irqsave(&master->devs_lock, flags); 1391 + guard(spinlock_irqsave)(&master->devs_lock); 1407 1392 idx = dw_i3c_master_get_addr_pos(master, addr); 1408 1393 if (idx < 0) { 1409 1394 dev_dbg_ratelimited(&master->base.dev, ··· 1439 1424 } 1440 1425 i3c_master_queue_ibi(dev, slot); 1441 1426 1442 - spin_unlock_irqrestore(&master->devs_lock, flags); 1443 - 1444 1427 return; 1445 1428 1446 1429 err_drain: 1447 1430 dw_i3c_master_drain_ibi_queue(master, len); 1448 - 1449 - spin_unlock_irqrestore(&master->devs_lock, flags); 1450 1431 } 1451 1432 1452 1433 /* "ibis": referring to In-Band Interrupts, and not ··· 1500 1489 return IRQ_HANDLED; 1501 1490 } 1502 1491 1492 + static int dw_i3c_master_set_dev_nack_retry(struct i3c_master_controller *m, 1493 + unsigned long dev_nack_retry_cnt) 1494 + { 1495 + struct dw_i3c_master *master = to_dw_i3c_master(m); 1496 + u32 reg; 1497 + int i; 1498 + 1499 + if (dev_nack_retry_cnt > DW_I3C_DEV_NACK_RETRY_CNT_MAX) { 1500 + dev_err(&master->base.dev, 1501 + "Value %ld exceeds maximum %d\n", 1502 + dev_nack_retry_cnt, DW_I3C_DEV_NACK_RETRY_CNT_MAX); 1503 + return -ERANGE; 1504 + } 1505 + 1506 + /* 1507 + * Update DAT entries for all currently attached devices. 1508 + * We directly iterate through the master's device array. 1509 + */ 1510 + for (i = 0; i < master->maxdevs; i++) { 1511 + /* Skip free/empty slots */ 1512 + if (master->free_pos & BIT(i)) 1513 + continue; 1514 + 1515 + reg = readl(master->regs + 1516 + DEV_ADDR_TABLE_LOC(master->datstartaddr, i)); 1517 + reg &= ~DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK; 1518 + reg |= DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(dev_nack_retry_cnt); 1519 + writel(reg, master->regs + 1520 + DEV_ADDR_TABLE_LOC(master->datstartaddr, i)); 1521 + } 1522 + 1523 + return 0; 1524 + } 1525 + 1503 1526 static const struct i3c_master_controller_ops dw_mipi_i3c_ops = { 1504 1527 .bus_init = dw_i3c_master_bus_init, 1505 1528 .bus_cleanup = dw_i3c_master_bus_cleanup, ··· 1554 1509 .recycle_ibi_slot = dw_i3c_master_recycle_ibi_slot, 1555 1510 .enable_hotjoin = dw_i3c_master_enable_hotjoin, 1556 1511 .disable_hotjoin = dw_i3c_master_disable_hotjoin, 1512 + .set_dev_nack_retry = dw_i3c_master_set_dev_nack_retry, 1557 1513 }; 1558 1514 1559 1515 /* default platform ops implementations */ ··· 1615 1569 1616 1570 spin_lock_init(&master->xferqueue.lock); 1617 1571 INIT_LIST_HEAD(&master->xferqueue.list); 1572 + 1573 + spin_lock_init(&master->devs_lock); 1618 1574 1619 1575 writel(INTR_ALL, master->regs + INTR_STATUS); 1620 1576 irq = platform_get_irq(pdev, 0); ··· 1724 1676 if (master->free_pos & BIT(pos)) 1725 1677 continue; 1726 1678 1727 - if (master->devs[pos].is_i2c_addr) 1728 - reg_val = DEV_ADDR_TABLE_LEGACY_I2C_DEV | 1679 + reg_val = readl(master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); 1680 + 1681 + if (master->devs[pos].is_i2c_addr) { 1682 + reg_val &= ~DEV_ADDR_TABLE_STATIC_MASK; 1683 + reg_val |= DEV_ADDR_TABLE_LEGACY_I2C_DEV | 1729 1684 DEV_ADDR_TABLE_STATIC_ADDR(master->devs[pos].addr); 1730 - else 1731 - reg_val = DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr); 1685 + } else { 1686 + reg_val &= ~DEV_ADDR_TABLE_DYNAMIC_MASK; 1687 + reg_val |= DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr); 1688 + } 1732 1689 1733 1690 writel(reg_val, master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); 1734 1691 }

-2

drivers/i3c/master/mipi-i3c-hci/cmd_v1.c

··· 15 15 #include "dat.h" 16 16 #include "dct.h" 17 17 18 - 19 18 /* 20 19 * Address Assignment Command 21 20 */ ··· 98 99 #define CMD_M0_MIPI_CMD W0_MASK(11, 8) 99 100 #define CMD_M0_VENDOR_INFO_PRESENT W0_BIT_( 7) 100 101 #define CMD_M0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v) 101 - 102 102 103 103 /* Data Transfer Speed and Mode */ 104 104 enum hci_cmd_mode {

-2

drivers/i3c/master/mipi-i3c-hci/cmd_v2.c

··· 16 16 #include "cmd.h" 17 17 #include "xfer_mode_rate.h" 18 18 19 - 20 19 /* 21 20 * Unified Data Transfer Command 22 21 */ ··· 60 61 #define CMD_A0_XFER_RATE(v) FIELD_PREP(W0_MASK( 17, 15), v) 61 62 #define CMD_A0_ASSIGN_ADDRESS(v) FIELD_PREP(W0_MASK( 14, 8), v) 62 63 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v) 63 - 64 64 65 65 static unsigned int get_i3c_rate_idx(struct i3c_hci *hci) 66 66 {

+336 -129

drivers/i3c/master/mipi-i3c-hci/core.c

··· 14 14 #include <linux/interrupt.h> 15 15 #include <linux/iopoll.h> 16 16 #include <linux/module.h> 17 + #include <linux/platform_data/mipi-i3c-hci.h> 17 18 #include <linux/platform_device.h> 19 + #include <linux/pm_runtime.h> 18 20 19 21 #include "hci.h" 20 22 #include "ext_caps.h" 21 23 #include "cmd.h" 22 24 #include "dat.h" 23 - 24 25 25 26 /* 26 27 * Host Controller Capabilities and Operation Registers ··· 110 109 #define DEV_CTX_BASE_LO 0x60 111 110 #define DEV_CTX_BASE_HI 0x64 112 111 113 - 114 112 static inline struct i3c_hci *to_i3c_hci(struct i3c_master_controller *m) 115 113 { 116 114 return container_of(m, struct i3c_hci, master); 115 + } 116 + 117 + static void i3c_hci_set_master_dyn_addr(struct i3c_hci *hci) 118 + { 119 + reg_write(MASTER_DEVICE_ADDR, 120 + MASTER_DYNAMIC_ADDR(hci->dyn_addr) | MASTER_DYNAMIC_ADDR_VALID); 117 121 } 118 122 119 123 static int i3c_hci_bus_init(struct i3c_master_controller *m) ··· 136 130 ret = i3c_master_get_free_addr(m, 0); 137 131 if (ret < 0) 138 132 return ret; 139 - reg_write(MASTER_DEVICE_ADDR, 140 - MASTER_DYNAMIC_ADDR(ret) | MASTER_DYNAMIC_ADDR_VALID); 133 + hci->dyn_addr = ret; 134 + i3c_hci_set_master_dyn_addr(hci); 141 135 memset(&info, 0, sizeof(info)); 142 - info.dyn_addr = ret; 136 + info.dyn_addr = hci->dyn_addr; 143 137 ret = i3c_master_set_info(m, &info); 144 138 if (ret) 145 139 return ret; ··· 158 152 return 0; 159 153 } 160 154 155 + /* Bus disable should never fail, so be generous with the timeout */ 156 + #define BUS_DISABLE_TIMEOUT_US (500 * USEC_PER_MSEC) 157 + 158 + static int i3c_hci_bus_disable(struct i3c_hci *hci) 159 + { 160 + u32 regval; 161 + int ret; 162 + 163 + reg_clear(HC_CONTROL, HC_CONTROL_BUS_ENABLE); 164 + 165 + /* Ensure controller is disabled */ 166 + ret = readx_poll_timeout(reg_read, HC_CONTROL, regval, 167 + !(regval & HC_CONTROL_BUS_ENABLE), 0, BUS_DISABLE_TIMEOUT_US); 168 + if (ret) 169 + dev_err(&hci->master.dev, "%s: Failed to disable bus\n", __func__); 170 + 171 + return ret; 172 + } 173 + 174 + void i3c_hci_sync_irq_inactive(struct i3c_hci *hci) 175 + { 176 + struct platform_device *pdev = to_platform_device(hci->master.dev.parent); 177 + int irq = platform_get_irq(pdev, 0); 178 + 179 + reg_write(INTR_SIGNAL_ENABLE, 0x0); 180 + hci->irq_inactive = true; 181 + synchronize_irq(irq); 182 + } 183 + 161 184 static void i3c_hci_bus_cleanup(struct i3c_master_controller *m) 162 185 { 163 186 struct i3c_hci *hci = to_i3c_hci(m); 164 - struct platform_device *pdev = to_platform_device(m->dev.parent); 165 187 166 - reg_clear(HC_CONTROL, HC_CONTROL_BUS_ENABLE); 167 - synchronize_irq(platform_get_irq(pdev, 0)); 188 + i3c_hci_bus_disable(hci); 168 189 hci->io->cleanup(hci); 169 - if (hci->cmd == &mipi_i3c_hci_cmd_v1) 170 - mipi_i3c_hci_dat_v1.cleanup(hci); 171 190 } 172 191 173 192 void mipi_i3c_hci_resume(struct i3c_hci *hci) ··· 566 535 irqreturn_t result = IRQ_NONE; 567 536 u32 val; 568 537 538 + /* 539 + * The IRQ can be shared, so the handler may be called when the IRQ is 540 + * due to a different device. That could happen when runtime suspended, 541 + * so exit immediately if IRQs are not expected for this device. 542 + */ 543 + if (hci->irq_inactive) 544 + return IRQ_NONE; 545 + 569 546 val = reg_read(INTR_STATUS); 570 547 reg_write(INTR_STATUS, val); 571 548 dev_dbg(&hci->master.dev, "INTR_STATUS %#x", val); ··· 601 562 return result; 602 563 } 603 564 604 - static int i3c_hci_init(struct i3c_hci *hci) 565 + static int i3c_hci_software_reset(struct i3c_hci *hci) 605 566 { 606 - bool size_in_dwords, mode_selector; 607 - u32 regval, offset; 567 + u32 regval; 608 568 int ret; 609 569 610 - /* Validate HCI hardware version */ 611 - regval = reg_read(HCI_VERSION); 612 - hci->version_major = (regval >> 8) & 0xf; 613 - hci->version_minor = (regval >> 4) & 0xf; 614 - hci->revision = regval & 0xf; 615 - dev_notice(&hci->master.dev, "MIPI I3C HCI v%u.%u r%02u\n", 616 - hci->version_major, hci->version_minor, hci->revision); 617 - /* known versions */ 618 - switch (regval & ~0xf) { 619 - case 0x100: /* version 1.0 */ 620 - case 0x110: /* version 1.1 */ 621 - case 0x200: /* version 2.0 */ 622 - break; 623 - default: 624 - dev_err(&hci->master.dev, "unsupported HCI version\n"); 625 - return -EPROTONOSUPPORT; 626 - } 627 - 628 - hci->caps = reg_read(HC_CAPABILITIES); 629 - dev_dbg(&hci->master.dev, "caps = %#x", hci->caps); 630 - 631 - size_in_dwords = hci->version_major < 1 || 632 - (hci->version_major == 1 && hci->version_minor < 1); 633 - 634 - regval = reg_read(DAT_SECTION); 635 - offset = FIELD_GET(DAT_TABLE_OFFSET, regval); 636 - hci->DAT_regs = offset ? hci->base_regs + offset : NULL; 637 - hci->DAT_entries = FIELD_GET(DAT_TABLE_SIZE, regval); 638 - hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8; 639 - if (size_in_dwords) 640 - hci->DAT_entries = 4 * hci->DAT_entries / hci->DAT_entry_size; 641 - dev_info(&hci->master.dev, "DAT: %u %u-bytes entries at offset %#x\n", 642 - hci->DAT_entries, hci->DAT_entry_size, offset); 643 - 644 - regval = reg_read(DCT_SECTION); 645 - offset = FIELD_GET(DCT_TABLE_OFFSET, regval); 646 - hci->DCT_regs = offset ? hci->base_regs + offset : NULL; 647 - hci->DCT_entries = FIELD_GET(DCT_TABLE_SIZE, regval); 648 - hci->DCT_entry_size = FIELD_GET(DCT_ENTRY_SIZE, regval) ? 0 : 16; 649 - if (size_in_dwords) 650 - hci->DCT_entries = 4 * hci->DCT_entries / hci->DCT_entry_size; 651 - dev_info(&hci->master.dev, "DCT: %u %u-bytes entries at offset %#x\n", 652 - hci->DCT_entries, hci->DCT_entry_size, offset); 653 - 654 - regval = reg_read(RING_HEADERS_SECTION); 655 - offset = FIELD_GET(RING_HEADERS_OFFSET, regval); 656 - hci->RHS_regs = offset ? hci->base_regs + offset : NULL; 657 - dev_info(&hci->master.dev, "Ring Headers at offset %#x\n", offset); 658 - 659 - regval = reg_read(PIO_SECTION); 660 - offset = FIELD_GET(PIO_REGS_OFFSET, regval); 661 - hci->PIO_regs = offset ? hci->base_regs + offset : NULL; 662 - dev_info(&hci->master.dev, "PIO section at offset %#x\n", offset); 663 - 664 - regval = reg_read(EXT_CAPS_SECTION); 665 - offset = FIELD_GET(EXT_CAPS_OFFSET, regval); 666 - hci->EXTCAPS_regs = offset ? hci->base_regs + offset : NULL; 667 - dev_info(&hci->master.dev, "Extended Caps at offset %#x\n", offset); 668 - 669 - ret = i3c_hci_parse_ext_caps(hci); 670 - if (ret) 671 - return ret; 672 - 673 570 /* 674 - * Now let's reset the hardware. 675 571 * SOFT_RST must be clear before we write to it. 676 572 * Then we must wait until it clears again. 677 573 */ 678 574 ret = readx_poll_timeout(reg_read, RESET_CONTROL, regval, 679 - !(regval & SOFT_RST), 1, 10000); 680 - if (ret) 681 - return -ENXIO; 575 + !(regval & SOFT_RST), 0, 10 * USEC_PER_MSEC); 576 + if (ret) { 577 + dev_err(&hci->master.dev, "%s: Software reset stuck\n", __func__); 578 + return ret; 579 + } 580 + 682 581 reg_write(RESET_CONTROL, SOFT_RST); 582 + 683 583 ret = readx_poll_timeout(reg_read, RESET_CONTROL, regval, 684 - !(regval & SOFT_RST), 1, 10000); 584 + !(regval & SOFT_RST), 0, 10 * USEC_PER_MSEC); 585 + if (ret) { 586 + dev_err(&hci->master.dev, "%s: Software reset failed\n", __func__); 587 + return ret; 588 + } 589 + 590 + return 0; 591 + } 592 + 593 + static inline bool is_version_1_1_or_newer(struct i3c_hci *hci) 594 + { 595 + return hci->version_major > 1 || (hci->version_major == 1 && hci->version_minor > 0); 596 + } 597 + 598 + static int i3c_hci_set_io_mode(struct i3c_hci *hci, bool dma) 599 + { 600 + bool pio_mode; 601 + 602 + if (dma) 603 + reg_clear(HC_CONTROL, HC_CONTROL_PIO_MODE); 604 + else 605 + reg_set(HC_CONTROL, HC_CONTROL_PIO_MODE); 606 + 607 + if (!is_version_1_1_or_newer(hci)) 608 + return 0; 609 + 610 + pio_mode = reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE; 611 + if ((dma && pio_mode) || (!dma && !pio_mode)) { 612 + dev_err(&hci->master.dev, "%s mode is stuck\n", pio_mode ? "PIO" : "DMA"); 613 + return -EIO; 614 + } 615 + 616 + return 0; 617 + } 618 + 619 + static int i3c_hci_reset_and_init(struct i3c_hci *hci) 620 + { 621 + u32 regval; 622 + int ret; 623 + 624 + ret = i3c_hci_software_reset(hci); 685 625 if (ret) 686 626 return -ENXIO; 687 627 ··· 697 679 } 698 680 } 699 681 682 + if (hci->io) { 683 + ret = i3c_hci_set_io_mode(hci, hci->io == &mipi_i3c_hci_dma); 684 + } else { 685 + /* Try activating DMA operations first */ 686 + if (hci->RHS_regs) { 687 + ret = i3c_hci_set_io_mode(hci, true); 688 + if (!ret) { 689 + hci->io = &mipi_i3c_hci_dma; 690 + dev_dbg(&hci->master.dev, "Using DMA\n"); 691 + } 692 + } 693 + 694 + /* If no DMA, try PIO */ 695 + if (!hci->io && hci->PIO_regs) { 696 + ret = i3c_hci_set_io_mode(hci, false); 697 + if (!ret) { 698 + hci->io = &mipi_i3c_hci_pio; 699 + dev_dbg(&hci->master.dev, "Using PIO\n"); 700 + } 701 + } 702 + 703 + if (!hci->io) { 704 + dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n"); 705 + ret = ret ?: -EINVAL; 706 + } 707 + } 708 + if (ret) 709 + return ret; 710 + 711 + /* Configure OD and PP timings for AMD platforms */ 712 + if (hci->quirks & HCI_QUIRK_OD_PP_TIMING) 713 + amd_set_od_pp_timing(hci); 714 + 715 + return 0; 716 + } 717 + 718 + static int i3c_hci_runtime_suspend(struct device *dev) 719 + { 720 + struct i3c_hci *hci = dev_get_drvdata(dev); 721 + int ret; 722 + 723 + ret = i3c_hci_bus_disable(hci); 724 + if (ret) 725 + return ret; 726 + 727 + hci->io->suspend(hci); 728 + 729 + return 0; 730 + } 731 + 732 + static int i3c_hci_runtime_resume(struct device *dev) 733 + { 734 + struct i3c_hci *hci = dev_get_drvdata(dev); 735 + int ret; 736 + 737 + ret = i3c_hci_reset_and_init(hci); 738 + if (ret) 739 + return -EIO; 740 + 741 + i3c_hci_set_master_dyn_addr(hci); 742 + 743 + mipi_i3c_hci_dat_v1.restore(hci); 744 + 745 + hci->irq_inactive = false; 746 + 747 + hci->io->resume(hci); 748 + 749 + reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE); 750 + 751 + return 0; 752 + } 753 + 754 + static int i3c_hci_suspend(struct device *dev) 755 + { 756 + struct i3c_hci *hci = dev_get_drvdata(dev); 757 + 758 + if (!(hci->quirks & HCI_QUIRK_RPM_ALLOWED)) 759 + return 0; 760 + 761 + return pm_runtime_force_suspend(dev); 762 + } 763 + 764 + static int i3c_hci_resume_common(struct device *dev, bool rstdaa) 765 + { 766 + struct i3c_hci *hci = dev_get_drvdata(dev); 767 + int ret; 768 + 769 + if (!(hci->quirks & HCI_QUIRK_RPM_ALLOWED)) 770 + return 0; 771 + 772 + ret = pm_runtime_force_resume(dev); 773 + if (ret) 774 + return ret; 775 + 776 + ret = i3c_master_do_daa_ext(&hci->master, rstdaa); 777 + if (ret) 778 + dev_err(dev, "Dynamic Address Assignment failed on resume, error %d\n", ret); 779 + 780 + /* 781 + * I3C devices may have retained their dynamic address anyway. Do not 782 + * fail the resume because of DAA error. 783 + */ 784 + return 0; 785 + } 786 + 787 + static int i3c_hci_resume(struct device *dev) 788 + { 789 + return i3c_hci_resume_common(dev, false); 790 + } 791 + 792 + static int i3c_hci_restore(struct device *dev) 793 + { 794 + return i3c_hci_resume_common(dev, true); 795 + } 796 + 797 + #define DEFAULT_AUTOSUSPEND_DELAY_MS 1000 798 + 799 + static void i3c_hci_rpm_enable(struct device *dev) 800 + { 801 + struct i3c_hci *hci = dev_get_drvdata(dev); 802 + 803 + pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY_MS); 804 + pm_runtime_use_autosuspend(dev); 805 + devm_pm_runtime_set_active_enabled(dev); 806 + 807 + hci->master.rpm_allowed = true; 808 + } 809 + 810 + static int i3c_hci_init(struct i3c_hci *hci) 811 + { 812 + bool size_in_dwords; 813 + u32 regval, offset; 814 + int ret; 815 + 816 + /* Validate HCI hardware version */ 817 + regval = reg_read(HCI_VERSION); 818 + hci->version_major = (regval >> 8) & 0xf; 819 + hci->version_minor = (regval >> 4) & 0xf; 820 + hci->revision = regval & 0xf; 821 + dev_notice(&hci->master.dev, "MIPI I3C HCI v%u.%u r%02u\n", 822 + hci->version_major, hci->version_minor, hci->revision); 823 + /* known versions */ 824 + switch (regval & ~0xf) { 825 + case 0x100: /* version 1.0 */ 826 + case 0x110: /* version 1.1 */ 827 + case 0x200: /* version 2.0 */ 828 + break; 829 + default: 830 + dev_err(&hci->master.dev, "unsupported HCI version\n"); 831 + return -EPROTONOSUPPORT; 832 + } 833 + 834 + hci->caps = reg_read(HC_CAPABILITIES); 835 + dev_dbg(&hci->master.dev, "caps = %#x", hci->caps); 836 + 837 + size_in_dwords = hci->version_major < 1 || 838 + (hci->version_major == 1 && hci->version_minor < 1); 839 + 840 + regval = reg_read(DAT_SECTION); 841 + offset = FIELD_GET(DAT_TABLE_OFFSET, regval); 842 + hci->DAT_regs = offset ? hci->base_regs + offset : NULL; 843 + hci->DAT_entries = FIELD_GET(DAT_TABLE_SIZE, regval); 844 + hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8; 845 + if (size_in_dwords) 846 + hci->DAT_entries = 4 * hci->DAT_entries / hci->DAT_entry_size; 847 + dev_dbg(&hci->master.dev, "DAT: %u %u-bytes entries at offset %#x\n", 848 + hci->DAT_entries, hci->DAT_entry_size, offset); 849 + 850 + regval = reg_read(DCT_SECTION); 851 + offset = FIELD_GET(DCT_TABLE_OFFSET, regval); 852 + hci->DCT_regs = offset ? hci->base_regs + offset : NULL; 853 + hci->DCT_entries = FIELD_GET(DCT_TABLE_SIZE, regval); 854 + hci->DCT_entry_size = FIELD_GET(DCT_ENTRY_SIZE, regval) ? 0 : 16; 855 + if (size_in_dwords) 856 + hci->DCT_entries = 4 * hci->DCT_entries / hci->DCT_entry_size; 857 + dev_dbg(&hci->master.dev, "DCT: %u %u-bytes entries at offset %#x\n", 858 + hci->DCT_entries, hci->DCT_entry_size, offset); 859 + 860 + regval = reg_read(RING_HEADERS_SECTION); 861 + offset = FIELD_GET(RING_HEADERS_OFFSET, regval); 862 + hci->RHS_regs = offset ? hci->base_regs + offset : NULL; 863 + dev_dbg(&hci->master.dev, "Ring Headers at offset %#x\n", offset); 864 + 865 + regval = reg_read(PIO_SECTION); 866 + offset = FIELD_GET(PIO_REGS_OFFSET, regval); 867 + hci->PIO_regs = offset ? hci->base_regs + offset : NULL; 868 + dev_dbg(&hci->master.dev, "PIO section at offset %#x\n", offset); 869 + 870 + regval = reg_read(EXT_CAPS_SECTION); 871 + offset = FIELD_GET(EXT_CAPS_OFFSET, regval); 872 + hci->EXTCAPS_regs = offset ? hci->base_regs + offset : NULL; 873 + dev_dbg(&hci->master.dev, "Extended Caps at offset %#x\n", offset); 874 + 875 + ret = i3c_hci_parse_ext_caps(hci); 876 + if (ret) 877 + return ret; 878 + 700 879 /* Select our command descriptor model */ 701 880 switch (FIELD_GET(HC_CAP_CMD_SIZE, hci->caps)) { 702 881 case 0: ··· 907 692 return -EINVAL; 908 693 } 909 694 910 - mode_selector = hci->version_major > 1 || 911 - (hci->version_major == 1 && hci->version_minor > 0); 912 - 913 695 /* Quirk for HCI_QUIRK_PIO_MODE on AMD platforms */ 914 696 if (hci->quirks & HCI_QUIRK_PIO_MODE) 915 697 hci->RHS_regs = NULL; 916 698 917 - /* Try activating DMA operations first */ 918 - if (hci->RHS_regs) { 919 - reg_clear(HC_CONTROL, HC_CONTROL_PIO_MODE); 920 - if (mode_selector && (reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE)) { 921 - dev_err(&hci->master.dev, "PIO mode is stuck\n"); 922 - ret = -EIO; 923 - } else { 924 - hci->io = &mipi_i3c_hci_dma; 925 - dev_info(&hci->master.dev, "Using DMA\n"); 926 - } 927 - } 928 - 929 - /* If no DMA, try PIO */ 930 - if (!hci->io && hci->PIO_regs) { 931 - reg_set(HC_CONTROL, HC_CONTROL_PIO_MODE); 932 - if (mode_selector && !(reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE)) { 933 - dev_err(&hci->master.dev, "DMA mode is stuck\n"); 934 - ret = -EIO; 935 - } else { 936 - hci->io = &mipi_i3c_hci_pio; 937 - dev_info(&hci->master.dev, "Using PIO\n"); 938 - } 939 - } 940 - 941 - if (!hci->io) { 942 - dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n"); 943 - if (!ret) 944 - ret = -EINVAL; 945 - return ret; 946 - } 947 - 948 - /* Configure OD and PP timings for AMD platforms */ 949 - if (hci->quirks & HCI_QUIRK_OD_PP_TIMING) 950 - amd_set_od_pp_timing(hci); 951 - 952 - return 0; 699 + return i3c_hci_reset_and_init(hci); 953 700 } 954 701 955 702 static int i3c_hci_probe(struct platform_device *pdev) 956 703 { 704 + const struct mipi_i3c_hci_platform_data *pdata = pdev->dev.platform_data; 957 705 struct i3c_hci *hci; 958 706 int irq, ret; 959 707 960 708 hci = devm_kzalloc(&pdev->dev, sizeof(*hci), GFP_KERNEL); 961 709 if (!hci) 962 710 return -ENOMEM; 963 - hci->base_regs = devm_platform_ioremap_resource(pdev, 0); 964 - if (IS_ERR(hci->base_regs)) 965 - return PTR_ERR(hci->base_regs); 711 + 712 + /* 713 + * Multi-bus instances share the same MMIO address range, but not 714 + * necessarily in separate contiguous sub-ranges. To avoid overlapping 715 + * mappings, provide base_regs from the parent mapping. 716 + */ 717 + if (pdata) 718 + hci->base_regs = pdata->base_regs; 719 + 720 + if (!hci->base_regs) { 721 + hci->base_regs = devm_platform_ioremap_resource(pdev, 0); 722 + if (IS_ERR(hci->base_regs)) 723 + return PTR_ERR(hci->base_regs); 724 + } 966 725 967 726 platform_set_drvdata(pdev, hci); 968 727 /* temporary for dev_printk's, to be replaced in i3c_master_register */ 969 728 hci->master.dev.init_name = dev_name(&pdev->dev); 970 729 971 730 hci->quirks = (unsigned long)device_get_match_data(&pdev->dev); 731 + if (!hci->quirks && platform_get_device_id(pdev)) 732 + hci->quirks = platform_get_device_id(pdev)->driver_data; 972 733 973 734 ret = i3c_hci_init(hci); 974 735 if (ret) ··· 952 761 953 762 irq = platform_get_irq(pdev, 0); 954 763 ret = devm_request_irq(&pdev->dev, irq, i3c_hci_irq_handler, 955 - 0, NULL, hci); 764 + IRQF_SHARED, NULL, hci); 956 765 if (ret) 957 766 return ret; 958 767 959 - ret = i3c_master_register(&hci->master, &pdev->dev, 960 - &i3c_hci_ops, false); 961 - if (ret) 962 - return ret; 768 + if (hci->quirks & HCI_QUIRK_RPM_ALLOWED) 769 + i3c_hci_rpm_enable(&pdev->dev); 963 770 964 - return 0; 771 + return i3c_master_register(&hci->master, &pdev->dev, &i3c_hci_ops, false); 965 772 } 966 773 967 774 static void i3c_hci_remove(struct platform_device *pdev) ··· 981 792 }; 982 793 MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); 983 794 795 + static const struct platform_device_id i3c_hci_driver_ids[] = { 796 + { .name = "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED }, 797 + { /* sentinel */ } 798 + }; 799 + MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids); 800 + 801 + static const struct dev_pm_ops i3c_hci_pm_ops = { 802 + .suspend = pm_sleep_ptr(i3c_hci_suspend), 803 + .resume = pm_sleep_ptr(i3c_hci_resume), 804 + .freeze = pm_sleep_ptr(i3c_hci_suspend), 805 + .thaw = pm_sleep_ptr(i3c_hci_resume), 806 + .poweroff = pm_sleep_ptr(i3c_hci_suspend), 807 + .restore = pm_sleep_ptr(i3c_hci_restore), 808 + RUNTIME_PM_OPS(i3c_hci_runtime_suspend, i3c_hci_runtime_resume, NULL) 809 + }; 810 + 984 811 static struct platform_driver i3c_hci_driver = { 985 812 .probe = i3c_hci_probe, 986 813 .remove = i3c_hci_remove, 814 + .id_table = i3c_hci_driver_ids, 987 815 .driver = { 988 816 .name = "mipi-i3c-hci", 989 817 .of_match_table = of_match_ptr(i3c_hci_of_match), 990 818 .acpi_match_table = i3c_hci_acpi_match, 819 + .pm = pm_ptr(&i3c_hci_pm_ops), 991 820 }, 992 821 }; 993 822 module_platform_driver(i3c_hci_driver);

+1 -1

drivers/i3c/master/mipi-i3c-hci/dat.h

··· 17 17 18 18 struct hci_dat_ops { 19 19 int (*init)(struct i3c_hci *hci); 20 - void (*cleanup)(struct i3c_hci *hci); 21 20 int (*alloc_entry)(struct i3c_hci *hci); 22 21 void (*free_entry)(struct i3c_hci *hci, unsigned int dat_idx); 23 22 void (*set_dynamic_addr)(struct i3c_hci *hci, unsigned int dat_idx, u8 addr); ··· 24 25 void (*set_flags)(struct i3c_hci *hci, unsigned int dat_idx, u32 w0, u32 w1); 25 26 void (*clear_flags)(struct i3c_hci *hci, unsigned int dat_idx, u32 w0, u32 w1); 26 27 int (*get_index)(struct i3c_hci *hci, u8 address); 28 + void (*restore)(struct i3c_hci *hci); 27 29 }; 28 30 29 31 extern const struct hci_dat_ops mipi_i3c_hci_dat_v1;

+33 -13

drivers/i3c/master/mipi-i3c-hci/dat_v1.c

··· 15 15 #include "hci.h" 16 16 #include "dat.h" 17 17 18 - 19 18 /* 20 19 * Device Address Table Structure 21 20 */ ··· 34 35 /* DAT_0_IBI_PAYLOAD W0_BIT_(12) */ 35 36 #define DAT_0_STATIC_ADDRESS W0_MASK(6, 0) 36 37 37 - #define dat_w0_read(i) readl(hci->DAT_regs + (i) * 8) 38 - #define dat_w1_read(i) readl(hci->DAT_regs + (i) * 8 + 4) 39 - #define dat_w0_write(i, v) writel(v, hci->DAT_regs + (i) * 8) 40 - #define dat_w1_write(i, v) writel(v, hci->DAT_regs + (i) * 8 + 4) 38 + #define dat_w0_read(i) hci->DAT[i].w0 39 + #define dat_w1_read(i) hci->DAT[i].w1 40 + #define dat_w0_write(i, v) hci_dat_w0_write(hci, i, v) 41 + #define dat_w1_write(i, v) hci_dat_w1_write(hci, i, v) 42 + 43 + static inline void hci_dat_w0_write(struct i3c_hci *hci, int i, u32 v) 44 + { 45 + hci->DAT[i].w0 = v; 46 + writel(v, hci->DAT_regs + i * 8); 47 + } 48 + 49 + static inline void hci_dat_w1_write(struct i3c_hci *hci, int i, u32 v) 50 + { 51 + hci->DAT[i].w1 = v; 52 + writel(v, hci->DAT_regs + i * 8 + 4); 53 + } 41 54 42 55 static int hci_dat_v1_init(struct i3c_hci *hci) 43 56 { 57 + struct device *dev = hci->master.dev.parent; 44 58 unsigned int dat_idx; 45 59 46 60 if (!hci->DAT_regs) { ··· 67 55 return -EOPNOTSUPP; 68 56 } 69 57 58 + if (!hci->DAT) { 59 + hci->DAT = devm_kcalloc(dev, hci->DAT_entries, hci->DAT_entry_size, GFP_KERNEL); 60 + if (!hci->DAT) 61 + return -ENOMEM; 62 + } 63 + 70 64 if (!hci->DAT_data) { 71 65 /* use a bitmap for faster free slot search */ 72 - hci->DAT_data = bitmap_zalloc(hci->DAT_entries, GFP_KERNEL); 66 + hci->DAT_data = devm_bitmap_zalloc(dev, hci->DAT_entries, GFP_KERNEL); 73 67 if (!hci->DAT_data) 74 68 return -ENOMEM; 75 69 ··· 87 69 } 88 70 89 71 return 0; 90 - } 91 - 92 - static void hci_dat_v1_cleanup(struct i3c_hci *hci) 93 - { 94 - bitmap_free(hci->DAT_data); 95 - hci->DAT_data = NULL; 96 72 } 97 73 98 74 static int hci_dat_v1_alloc_entry(struct i3c_hci *hci) ··· 181 169 return -ENODEV; 182 170 } 183 171 172 + static void hci_dat_v1_restore(struct i3c_hci *hci) 173 + { 174 + for (int i = 0; i < hci->DAT_entries; i++) { 175 + writel(hci->DAT[i].w0, hci->DAT_regs + i * 8); 176 + writel(hci->DAT[i].w1, hci->DAT_regs + i * 8 + 4); 177 + } 178 + } 179 + 184 180 const struct hci_dat_ops mipi_i3c_hci_dat_v1 = { 185 181 .init = hci_dat_v1_init, 186 - .cleanup = hci_dat_v1_cleanup, 187 182 .alloc_entry = hci_dat_v1_alloc_entry, 188 183 .free_entry = hci_dat_v1_free_entry, 189 184 .set_dynamic_addr = hci_dat_v1_set_dynamic_addr, ··· 198 179 .set_flags = hci_dat_v1_set_flags, 199 180 .clear_flags = hci_dat_v1_clear_flags, 200 181 .get_index = hci_dat_v1_get_index, 182 + .restore = hci_dat_v1_restore, 201 183 };

+123 -48

drivers/i3c/master/mipi-i3c-hci/dma.c

··· 20 20 #include "cmd.h" 21 21 #include "ibi.h" 22 22 23 - 24 23 /* 25 24 * Software Parameter Values (somewhat arb itrary for now). 26 25 * Some of them could be determined at run time eventually. ··· 123 124 #define DATA_BUF_IOC BIT(30) /* Interrupt on Completion */ 124 125 #define DATA_BUF_BLOCK_SIZE GENMASK(15, 0) 125 126 126 - 127 127 struct hci_rh_data { 128 128 void __iomem *regs; 129 129 void *xfer, *resp, *ibi_status, *ibi_data; ··· 160 162 161 163 rh_reg_write(INTR_SIGNAL_ENABLE, 0); 162 164 rh_reg_write(RING_CONTROL, 0); 165 + } 166 + 167 + i3c_hci_sync_irq_inactive(hci); 168 + 169 + for (i = 0; i < rings->total; i++) { 170 + rh = &rings->headers[i]; 171 + 163 172 rh_reg_write(CR_SETUP, 0); 164 173 rh_reg_write(IBI_SETUP, 0); 174 + } 175 + 176 + rhs_reg_write(CONTROL, 0); 177 + } 178 + 179 + static void hci_dma_free(void *data) 180 + { 181 + struct i3c_hci *hci = data; 182 + struct hci_rings_data *rings = hci->io_data; 183 + struct hci_rh_data *rh; 184 + 185 + if (!rings) 186 + return; 187 + 188 + for (int i = 0; i < rings->total; i++) { 189 + rh = &rings->headers[i]; 165 190 166 191 if (rh->xfer) 167 192 dma_free_coherent(rings->sysdev, ··· 206 185 kfree(rh->ibi_data); 207 186 } 208 187 209 - rhs_reg_write(CONTROL, 0); 210 - 211 188 kfree(rings); 212 189 hci->io_data = NULL; 190 + } 191 + 192 + static void hci_dma_init_rh(struct i3c_hci *hci, struct hci_rh_data *rh, int i) 193 + { 194 + u32 regval; 195 + 196 + rh_reg_write(CMD_RING_BASE_LO, lower_32_bits(rh->xfer_dma)); 197 + rh_reg_write(CMD_RING_BASE_HI, upper_32_bits(rh->xfer_dma)); 198 + rh_reg_write(RESP_RING_BASE_LO, lower_32_bits(rh->resp_dma)); 199 + rh_reg_write(RESP_RING_BASE_HI, upper_32_bits(rh->resp_dma)); 200 + 201 + regval = FIELD_PREP(CR_RING_SIZE, rh->xfer_entries); 202 + rh_reg_write(CR_SETUP, regval); 203 + 204 + rh_reg_write(INTR_STATUS_ENABLE, 0xffffffff); 205 + rh_reg_write(INTR_SIGNAL_ENABLE, INTR_IBI_READY | 206 + INTR_TRANSFER_COMPLETION | 207 + INTR_RING_OP | 208 + INTR_TRANSFER_ERR | 209 + INTR_IBI_RING_FULL | 210 + INTR_TRANSFER_ABORT); 211 + 212 + if (i >= IBI_RINGS) 213 + goto ring_ready; 214 + 215 + rh_reg_write(IBI_STATUS_RING_BASE_LO, lower_32_bits(rh->ibi_status_dma)); 216 + rh_reg_write(IBI_STATUS_RING_BASE_HI, upper_32_bits(rh->ibi_status_dma)); 217 + rh_reg_write(IBI_DATA_RING_BASE_LO, lower_32_bits(rh->ibi_data_dma)); 218 + rh_reg_write(IBI_DATA_RING_BASE_HI, upper_32_bits(rh->ibi_data_dma)); 219 + 220 + regval = FIELD_PREP(IBI_STATUS_RING_SIZE, rh->ibi_status_entries) | 221 + FIELD_PREP(IBI_DATA_CHUNK_SIZE, ilog2(rh->ibi_chunk_sz) - 2) | 222 + FIELD_PREP(IBI_DATA_CHUNK_COUNT, rh->ibi_chunks_total); 223 + rh_reg_write(IBI_SETUP, regval); 224 + 225 + regval = rh_reg_read(INTR_SIGNAL_ENABLE); 226 + regval |= INTR_IBI_READY; 227 + rh_reg_write(INTR_SIGNAL_ENABLE, regval); 228 + 229 + ring_ready: 230 + /* 231 + * The MIPI I3C HCI specification does not document reset values for 232 + * RING_OPERATION1 fields and some controllers (e.g. Intel controllers) 233 + * do not reset the values, so ensure the ring pointers are set to zero 234 + * here. 235 + */ 236 + rh_reg_write(RING_OPERATION1, 0); 237 + 238 + rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); 239 + rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP); 240 + 241 + rh->done_ptr = 0; 242 + rh->ibi_chunk_ptr = 0; 243 + } 244 + 245 + static void hci_dma_init_rings(struct i3c_hci *hci) 246 + { 247 + struct hci_rings_data *rings = hci->io_data; 248 + u32 regval; 249 + 250 + regval = FIELD_PREP(MAX_HEADER_COUNT, rings->total); 251 + rhs_reg_write(CONTROL, regval); 252 + 253 + for (int i = 0; i < rings->total; i++) 254 + hci_dma_init_rh(hci, &rings->headers[i], i); 255 + } 256 + 257 + static void hci_dma_suspend(struct i3c_hci *hci) 258 + { 259 + struct hci_rings_data *rings = hci->io_data; 260 + int n = rings ? rings->total : 0; 261 + 262 + for (int i = 0; i < n; i++) { 263 + struct hci_rh_data *rh = &rings->headers[i]; 264 + 265 + rh_reg_write(INTR_SIGNAL_ENABLE, 0); 266 + rh_reg_write(RING_CONTROL, 0); 267 + } 268 + 269 + i3c_hci_sync_irq_inactive(hci); 270 + } 271 + 272 + static void hci_dma_resume(struct i3c_hci *hci) 273 + { 274 + struct hci_rings_data *rings = hci->io_data; 275 + 276 + if (rings) 277 + hci_dma_init_rings(hci); 213 278 } 214 279 215 280 static int hci_dma_init(struct i3c_hci *hci) ··· 321 214 322 215 regval = rhs_reg_read(CONTROL); 323 216 nr_rings = FIELD_GET(MAX_HEADER_COUNT_CAP, regval); 324 - dev_info(&hci->master.dev, "%d DMA rings available\n", nr_rings); 217 + dev_dbg(&hci->master.dev, "%d DMA rings available\n", nr_rings); 325 218 if (unlikely(nr_rings > 8)) { 326 219 dev_err(&hci->master.dev, "number of rings should be <= 8\n"); 327 220 nr_rings = 8; ··· 335 228 rings->total = nr_rings; 336 229 rings->sysdev = sysdev; 337 230 338 - regval = FIELD_PREP(MAX_HEADER_COUNT, rings->total); 339 - rhs_reg_write(CONTROL, regval); 340 - 341 231 for (i = 0; i < rings->total; i++) { 342 232 u32 offset = rhs_reg_read(RHn_OFFSET(i)); 343 233 344 - dev_info(&hci->master.dev, "Ring %d at offset %#x\n", i, offset); 234 + dev_dbg(&hci->master.dev, "Ring %d at offset %#x\n", i, offset); 345 235 ret = -EINVAL; 346 236 if (!offset) 347 237 goto err_out; ··· 369 265 if (!rh->xfer || !rh->resp || !rh->src_xfers) 370 266 goto err_out; 371 267 372 - rh_reg_write(CMD_RING_BASE_LO, lower_32_bits(rh->xfer_dma)); 373 - rh_reg_write(CMD_RING_BASE_HI, upper_32_bits(rh->xfer_dma)); 374 - rh_reg_write(RESP_RING_BASE_LO, lower_32_bits(rh->resp_dma)); 375 - rh_reg_write(RESP_RING_BASE_HI, upper_32_bits(rh->resp_dma)); 376 - 377 - regval = FIELD_PREP(CR_RING_SIZE, rh->xfer_entries); 378 - rh_reg_write(CR_SETUP, regval); 379 - 380 - rh_reg_write(INTR_STATUS_ENABLE, 0xffffffff); 381 - rh_reg_write(INTR_SIGNAL_ENABLE, INTR_IBI_READY | 382 - INTR_TRANSFER_COMPLETION | 383 - INTR_RING_OP | 384 - INTR_TRANSFER_ERR | 385 - INTR_IBI_RING_FULL | 386 - INTR_TRANSFER_ABORT); 387 - 388 268 /* IBIs */ 389 269 390 270 if (i >= IBI_RINGS) 391 - goto ring_ready; 271 + continue; 392 272 393 273 regval = rh_reg_read(IBI_SETUP); 394 274 rh->ibi_status_sz = FIELD_GET(IBI_STATUS_STRUCT_SIZE, regval); ··· 411 323 ret = -ENOMEM; 412 324 goto err_out; 413 325 } 414 - 415 - rh_reg_write(IBI_STATUS_RING_BASE_LO, lower_32_bits(rh->ibi_status_dma)); 416 - rh_reg_write(IBI_STATUS_RING_BASE_HI, upper_32_bits(rh->ibi_status_dma)); 417 - rh_reg_write(IBI_DATA_RING_BASE_LO, lower_32_bits(rh->ibi_data_dma)); 418 - rh_reg_write(IBI_DATA_RING_BASE_HI, upper_32_bits(rh->ibi_data_dma)); 419 - 420 - regval = FIELD_PREP(IBI_STATUS_RING_SIZE, 421 - rh->ibi_status_entries) | 422 - FIELD_PREP(IBI_DATA_CHUNK_SIZE, 423 - ilog2(rh->ibi_chunk_sz) - 2) | 424 - FIELD_PREP(IBI_DATA_CHUNK_COUNT, 425 - rh->ibi_chunks_total); 426 - rh_reg_write(IBI_SETUP, regval); 427 - 428 - regval = rh_reg_read(INTR_SIGNAL_ENABLE); 429 - regval |= INTR_IBI_READY; 430 - rh_reg_write(INTR_SIGNAL_ENABLE, regval); 431 - 432 - ring_ready: 433 - rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | 434 - RING_CTRL_RUN_STOP); 435 326 } 327 + 328 + ret = devm_add_action(hci->master.dev.parent, hci_dma_free, hci); 329 + if (ret) 330 + goto err_out; 331 + 332 + hci_dma_init_rings(hci); 436 333 437 334 return 0; 438 335 439 336 err_out: 440 - hci_dma_cleanup(hci); 337 + hci_dma_free(hci); 441 338 return ret; 442 339 } 443 340 ··· 888 815 .request_ibi = hci_dma_request_ibi, 889 816 .free_ibi = hci_dma_free_ibi, 890 817 .recycle_ibi_slot = hci_dma_recycle_ibi_slot, 818 + .suspend = hci_dma_suspend, 819 + .resume = hci_dma_resume, 891 820 };

+27 -31

drivers/i3c/master/mipi-i3c-hci/ext_caps.c

··· 16 16 #include "ext_caps.h" 17 17 #include "xfer_mode_rate.h" 18 18 19 - 20 19 /* Extended Capability Header */ 21 20 #define CAP_HEADER_LENGTH GENMASK(23, 8) 22 21 #define CAP_HEADER_ID GENMASK(7, 0) ··· 26 27 hci->vendor_version_id = readl(base + 0x08); 27 28 hci->vendor_product_id = readl(base + 0x0c); 28 29 29 - dev_info(&hci->master.dev, "vendor MIPI ID: %#x\n", hci->vendor_mipi_id); 30 - dev_info(&hci->master.dev, "vendor version ID: %#x\n", hci->vendor_version_id); 31 - dev_info(&hci->master.dev, "vendor product ID: %#x\n", hci->vendor_product_id); 30 + dev_dbg(&hci->master.dev, "vendor MIPI ID: %#x\n", hci->vendor_mipi_id); 31 + dev_dbg(&hci->master.dev, "vendor version ID: %#x\n", hci->vendor_version_id); 32 + dev_dbg(&hci->master.dev, "vendor product ID: %#x\n", hci->vendor_product_id); 32 33 33 34 /* ought to go in a table if this grows too much */ 34 35 switch (hci->vendor_mipi_id) { ··· 48 49 static const char * const functionality[] = { 49 50 "(unknown)", "master only", "target only", 50 51 "primary/secondary master" }; 51 - dev_info(&hci->master.dev, "operation mode: %s\n", functionality[operation_mode]); 52 + dev_dbg(&hci->master.dev, "operation mode: %s\n", functionality[operation_mode]); 52 53 if (operation_mode & 0x1) 53 54 return 0; 54 55 dev_err(&hci->master.dev, "only master mode is currently supported\n"); ··· 60 61 u32 bus_instance = readl(base + 0x04); 61 62 unsigned int count = FIELD_GET(GENMASK(3, 0), bus_instance); 62 63 63 - dev_info(&hci->master.dev, "%d bus instances\n", count); 64 + dev_dbg(&hci->master.dev, "%d bus instances\n", count); 64 65 return 0; 65 66 } 66 67 ··· 70 71 u32 entries = FIELD_GET(CAP_HEADER_LENGTH, header) - 1; 71 72 unsigned int index; 72 73 73 - dev_info(&hci->master.dev, "transfer mode table has %d entries\n", 74 - entries); 74 + dev_dbg(&hci->master.dev, "transfer mode table has %d entries\n", entries); 75 75 base += 4; /* skip header */ 76 76 for (index = 0; index < entries; index++) { 77 77 u32 mode_entry = readl(base); ··· 93 95 94 96 base += 4; /* skip header */ 95 97 96 - dev_info(&hci->master.dev, "available data rates:\n"); 98 + dev_dbg(&hci->master.dev, "available data rates:\n"); 97 99 for (index = 0; index < entries; index++) { 98 100 rate_entry = readl(base); 99 101 dev_dbg(&hci->master.dev, "entry %d: 0x%08x", ··· 101 103 rate = FIELD_GET(XFERRATE_ACTUAL_RATE_KHZ, rate_entry); 102 104 rate_id = FIELD_GET(XFERRATE_RATE_ID, rate_entry); 103 105 mode_id = FIELD_GET(XFERRATE_MODE_ID, rate_entry); 104 - dev_info(&hci->master.dev, "rate %d for %s = %d kHz\n", 105 - rate_id, 106 - mode_id == XFERRATE_MODE_I3C ? "I3C" : 107 - mode_id == XFERRATE_MODE_I2C ? "I2C" : 108 - "unknown mode", 109 - rate); 106 + dev_dbg(&hci->master.dev, "rate %d for %s = %d kHz\n", 107 + rate_id, 108 + mode_id == XFERRATE_MODE_I3C ? "I3C" : 109 + mode_id == XFERRATE_MODE_I2C ? "I2C" : 110 + "unknown mode", 111 + rate); 110 112 base += 4; 111 113 } 112 114 ··· 120 122 u32 autocmd_ext_config = readl(base + 0x08); 121 123 unsigned int count = FIELD_GET(GENMASK(3, 0), autocmd_ext_config); 122 124 123 - dev_info(&hci->master.dev, "%d/%d active auto-command entries\n", 124 - count, max_count); 125 + dev_dbg(&hci->master.dev, "%d/%d active auto-command entries\n", 126 + count, max_count); 125 127 /* remember auto-command register location for later use */ 126 128 hci->AUTOCMD_regs = base; 127 129 return 0; ··· 129 131 130 132 static int hci_extcap_debug(struct i3c_hci *hci, void __iomem *base) 131 133 { 132 - dev_info(&hci->master.dev, "debug registers present\n"); 134 + dev_dbg(&hci->master.dev, "debug registers present\n"); 133 135 hci->DEBUG_regs = base; 134 136 return 0; 135 137 } 136 138 137 139 static int hci_extcap_scheduled_cmd(struct i3c_hci *hci, void __iomem *base) 138 140 { 139 - dev_info(&hci->master.dev, "scheduled commands available\n"); 141 + dev_dbg(&hci->master.dev, "scheduled commands available\n"); 140 142 /* hci->schedcmd_regs = base; */ 141 143 return 0; 142 144 } 143 145 144 146 static int hci_extcap_non_curr_master(struct i3c_hci *hci, void __iomem *base) 145 147 { 146 - dev_info(&hci->master.dev, "Non-Current Master support available\n"); 148 + dev_dbg(&hci->master.dev, "Non-Current Master support available\n"); 147 149 /* hci->NCM_regs = base; */ 148 150 return 0; 149 151 } 150 152 151 153 static int hci_extcap_ccc_resp_conf(struct i3c_hci *hci, void __iomem *base) 152 154 { 153 - dev_info(&hci->master.dev, "CCC Response Configuration available\n"); 155 + dev_dbg(&hci->master.dev, "CCC Response Configuration available\n"); 154 156 return 0; 155 157 } 156 158 157 159 static int hci_extcap_global_DAT(struct i3c_hci *hci, void __iomem *base) 158 160 { 159 - dev_info(&hci->master.dev, "Global DAT available\n"); 161 + dev_dbg(&hci->master.dev, "Global DAT available\n"); 160 162 return 0; 161 163 } 162 164 163 165 static int hci_extcap_multilane(struct i3c_hci *hci, void __iomem *base) 164 166 { 165 - dev_info(&hci->master.dev, "Master Multi-Lane support available\n"); 167 + dev_dbg(&hci->master.dev, "Master Multi-Lane support available\n"); 166 168 return 0; 167 169 } 168 170 169 171 static int hci_extcap_ncm_multilane(struct i3c_hci *hci, void __iomem *base) 170 172 { 171 - dev_info(&hci->master.dev, "NCM Multi-Lane support available\n"); 173 + dev_dbg(&hci->master.dev, "NCM Multi-Lane support available\n"); 172 174 return 0; 173 175 } 174 176 ··· 201 203 static int hci_extcap_vendor_NXP(struct i3c_hci *hci, void __iomem *base) 202 204 { 203 205 hci->vendor_data = (__force void *)base; 204 - dev_info(&hci->master.dev, "Build Date Info = %#x\n", readl(base + 1*4)); 206 + dev_dbg(&hci->master.dev, "Build Date Info = %#x\n", readl(base + 1 * 4)); 205 207 /* reset the FPGA */ 206 208 writel(0xdeadbeef, base + 1*4); 207 209 return 0; ··· 239 241 } 240 242 241 243 if (!vendor_cap_entry) { 242 - dev_notice(&hci->master.dev, 243 - "unknown ext_cap 0x%02x for vendor 0x%02x\n", 244 - cap_id, hci->vendor_mipi_id); 244 + dev_dbg(&hci->master.dev, "unknown ext_cap 0x%02x for vendor 0x%02x\n", 245 + cap_id, hci->vendor_mipi_id); 245 246 return 0; 246 247 } 247 248 if (cap_length < vendor_cap_entry->min_length) { ··· 269 272 cap_length = FIELD_GET(CAP_HEADER_LENGTH, cap_header); 270 273 dev_dbg(&hci->master.dev, "id=0x%02x length=%d", 271 274 cap_id, cap_length); 272 - if (!cap_length) 275 + if (!cap_id || !cap_length) 273 276 break; 274 277 if (curr_cap + cap_length * 4 >= end) { 275 278 dev_err(&hci->master.dev, ··· 293 296 } 294 297 } 295 298 if (!cap_entry) { 296 - dev_notice(&hci->master.dev, 297 - "unknown ext_cap 0x%02x\n", cap_id); 299 + dev_dbg(&hci->master.dev, "unknown ext_cap 0x%02x\n", cap_id); 298 300 } else if (cap_length < cap_entry->min_length) { 299 301 dev_err(&hci->master.dev, 300 302 "ext_cap 0x%02x has size %d (expecting >= %d)\n",

-1

drivers/i3c/master/mipi-i3c-hci/ext_caps.h

··· 13 13 /* MIPI vendor IDs */ 14 14 #define MIPI_VENDOR_NXP 0x11b 15 15 16 - 17 16 int i3c_hci_parse_ext_caps(struct i3c_hci *hci); 18 17 19 18 #endif

+12 -5

drivers/i3c/master/mipi-i3c-hci/hci.h

··· 31 31 32 32 struct hci_cmd_ops; 33 33 34 + struct dat_words { 35 + u32 w0; 36 + u32 w1; 37 + }; 38 + 34 39 /* Our main structure */ 35 40 struct i3c_hci { 36 41 struct i3c_master_controller master; ··· 51 46 void *io_data; 52 47 const struct hci_cmd_ops *cmd; 53 48 atomic_t next_cmd_tid; 49 + bool irq_inactive; 54 50 u32 caps; 55 51 unsigned int quirks; 56 52 unsigned int DAT_entries; 57 53 unsigned int DAT_entry_size; 58 54 void *DAT_data; 55 + struct dat_words *DAT; 59 56 unsigned int DCT_entries; 60 57 unsigned int DCT_entry_size; 61 58 u8 version_major; 62 59 u8 version_minor; 63 60 u8 revision; 61 + u8 dyn_addr; 64 62 u32 vendor_mipi_id; 65 63 u32 vendor_version_id; 66 64 u32 vendor_product_id; 67 65 void *vendor_data; 68 66 }; 69 - 70 67 71 68 /* 72 69 * Structure to represent a master initiated transfer. ··· 115 108 kfree(xfer); 116 109 } 117 110 118 - 119 111 /* This abstracts PIO vs DMA operations */ 120 112 struct hci_io_ops { 121 113 bool (*irq_handler)(struct i3c_hci *hci); ··· 127 121 struct i3c_ibi_slot *slot); 128 122 int (*init)(struct i3c_hci *hci); 129 123 void (*cleanup)(struct i3c_hci *hci); 124 + void (*suspend)(struct i3c_hci *hci); 125 + void (*resume)(struct i3c_hci *hci); 130 126 }; 131 127 132 128 extern const struct hci_io_ops mipi_i3c_hci_pio; 133 129 extern const struct hci_io_ops mipi_i3c_hci_dma; 134 - 135 130 136 131 /* Our per device master private data */ 137 132 struct i3c_hci_dev_data { ··· 140 133 void *ibi_data; 141 134 }; 142 135 143 - 144 136 /* list of quirks */ 145 137 #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ 146 138 #define HCI_QUIRK_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ 147 139 #define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */ 148 140 #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD platforms */ 149 - 141 + #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ 150 142 151 143 /* global functions */ 152 144 void mipi_i3c_hci_resume(struct i3c_hci *hci); ··· 153 147 void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); 154 148 void amd_set_od_pp_timing(struct i3c_hci *hci); 155 149 void amd_set_resp_buf_thld(struct i3c_hci *hci); 150 + void i3c_hci_sync_irq_inactive(struct i3c_hci *hci); 156 151 157 152 #endif

+124 -62

drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c

··· 12 12 #include <linux/idr.h> 13 13 #include <linux/iopoll.h> 14 14 #include <linux/kernel.h> 15 + #include <linux/mfd/core.h> 15 16 #include <linux/module.h> 16 17 #include <linux/pci.h> 18 + #include <linux/platform_data/mipi-i3c-hci.h> 17 19 #include <linux/platform_device.h> 18 20 #include <linux/pm_qos.h> 21 + #include <linux/pm_runtime.h> 22 + 23 + /* 24 + * There can up to 15 instances, but implementations have at most 2 at this 25 + * time. 26 + */ 27 + #define INST_MAX 2 19 28 20 29 struct mipi_i3c_hci_pci { 21 30 struct pci_dev *pci; 22 - struct platform_device *pdev; 31 + void __iomem *base; 23 32 const struct mipi_i3c_hci_pci_info *info; 24 33 void *private; 25 34 }; ··· 36 27 struct mipi_i3c_hci_pci_info { 37 28 int (*init)(struct mipi_i3c_hci_pci *hci); 38 29 void (*exit)(struct mipi_i3c_hci_pci *hci); 30 + const char *name; 31 + int id[INST_MAX]; 32 + u32 instance_offset[INST_MAX]; 33 + int instance_count; 39 34 }; 40 35 41 - static DEFINE_IDA(mipi_i3c_hci_pci_ida); 42 - 43 36 #define INTEL_PRIV_OFFSET 0x2b0 44 - #define INTEL_PRIV_SIZE 0x28 45 37 #define INTEL_RESETS 0x04 46 38 #define INTEL_RESETS_RESET BIT(0) 47 39 #define INTEL_RESETS_RESET_DONE BIT(1) ··· 153 143 writel(INTEL_RESETS_RESET, priv + INTEL_RESETS); 154 144 } 155 145 156 - static void __iomem *intel_priv(struct pci_dev *pci) 157 - { 158 - resource_size_t base = pci_resource_start(pci, 0); 159 - 160 - return devm_ioremap(&pci->dev, base + INTEL_PRIV_OFFSET, INTEL_PRIV_SIZE); 161 - } 162 - 163 146 static int intel_i3c_init(struct mipi_i3c_hci_pci *hci) 164 147 { 165 148 struct intel_host *host = devm_kzalloc(&hci->pci->dev, sizeof(*host), GFP_KERNEL); 166 - void __iomem *priv = intel_priv(hci->pci); 149 + void __iomem *priv = hci->base + INTEL_PRIV_OFFSET; 167 150 168 - if (!host || !priv) 151 + if (!host) 169 152 return -ENOMEM; 170 153 171 154 dma_set_mask_and_coherent(&hci->pci->dev, DMA_BIT_MASK(64)); ··· 182 179 intel_ltr_hide(&hci->pci->dev); 183 180 } 184 181 185 - static const struct mipi_i3c_hci_pci_info intel_info = { 182 + static const struct mipi_i3c_hci_pci_info intel_mi_1_info = { 186 183 .init = intel_i3c_init, 187 184 .exit = intel_i3c_exit, 185 + .name = "intel-lpss-i3c", 186 + .id = {0, 1}, 187 + .instance_offset = {0, 0x400}, 188 + .instance_count = 2, 188 189 }; 190 + 191 + static const struct mipi_i3c_hci_pci_info intel_mi_2_info = { 192 + .init = intel_i3c_init, 193 + .exit = intel_i3c_exit, 194 + .name = "intel-lpss-i3c", 195 + .id = {2, 3}, 196 + .instance_offset = {0, 0x400}, 197 + .instance_count = 2, 198 + }; 199 + 200 + static const struct mipi_i3c_hci_pci_info intel_si_2_info = { 201 + .init = intel_i3c_init, 202 + .exit = intel_i3c_exit, 203 + .name = "intel-lpss-i3c", 204 + .id = {2}, 205 + .instance_offset = {0}, 206 + .instance_count = 1, 207 + }; 208 + 209 + static void mipi_i3c_hci_pci_rpm_allow(struct device *dev) 210 + { 211 + pm_runtime_put(dev); 212 + pm_runtime_allow(dev); 213 + } 214 + 215 + static void mipi_i3c_hci_pci_rpm_forbid(struct device *dev) 216 + { 217 + pm_runtime_forbid(dev); 218 + pm_runtime_get_sync(dev); 219 + } 220 + 221 + struct mipi_i3c_hci_pci_cell_data { 222 + struct mipi_i3c_hci_platform_data pdata; 223 + struct resource res; 224 + }; 225 + 226 + static void mipi_i3c_hci_pci_setup_cell(struct mipi_i3c_hci_pci *hci, int idx, 227 + struct mipi_i3c_hci_pci_cell_data *data, 228 + struct mfd_cell *cell) 229 + { 230 + data->pdata.base_regs = hci->base + hci->info->instance_offset[idx]; 231 + 232 + data->res = DEFINE_RES_IRQ(0); 233 + 234 + cell->name = hci->info->name; 235 + cell->id = hci->info->id[idx]; 236 + cell->platform_data = &data->pdata; 237 + cell->pdata_size = sizeof(data->pdata); 238 + cell->num_resources = 1; 239 + cell->resources = &data->res; 240 + } 241 + 242 + #define mipi_i3c_hci_pci_alloc(h, x) kcalloc((h)->info->instance_count, sizeof(*(x)), GFP_KERNEL) 243 + 244 + static int mipi_i3c_hci_pci_add_instances(struct mipi_i3c_hci_pci *hci) 245 + { 246 + struct mipi_i3c_hci_pci_cell_data *data __free(kfree) = mipi_i3c_hci_pci_alloc(hci, data); 247 + struct mfd_cell *cells __free(kfree) = mipi_i3c_hci_pci_alloc(hci, cells); 248 + int irq = pci_irq_vector(hci->pci, 0); 249 + int nr = hci->info->instance_count; 250 + 251 + if (!cells || !data) 252 + return -ENOMEM; 253 + 254 + for (int i = 0; i < nr; i++) 255 + mipi_i3c_hci_pci_setup_cell(hci, i, data + i, cells + i); 256 + 257 + return mfd_add_devices(&hci->pci->dev, 0, cells, nr, NULL, irq, NULL); 258 + } 189 259 190 260 static int mipi_i3c_hci_pci_probe(struct pci_dev *pci, 191 261 const struct pci_device_id *id) 192 262 { 193 263 struct mipi_i3c_hci_pci *hci; 194 - struct resource res[2]; 195 - int dev_id, ret; 264 + int ret; 196 265 197 266 hci = devm_kzalloc(&pci->dev, sizeof(*hci), GFP_KERNEL); 198 267 if (!hci) ··· 278 203 279 204 pci_set_master(pci); 280 205 281 - memset(&res, 0, sizeof(res)); 206 + hci->base = pcim_iomap_region(pci, 0, pci_name(pci)); 207 + if (IS_ERR(hci->base)) 208 + return PTR_ERR(hci->base); 282 209 283 - res[0].flags = IORESOURCE_MEM; 284 - res[0].start = pci_resource_start(pci, 0); 285 - res[0].end = pci_resource_end(pci, 0); 286 - 287 - res[1].flags = IORESOURCE_IRQ; 288 - res[1].start = pci->irq; 289 - res[1].end = pci->irq; 290 - 291 - dev_id = ida_alloc(&mipi_i3c_hci_pci_ida, GFP_KERNEL); 292 - if (dev_id < 0) 293 - return dev_id; 294 - 295 - hci->pdev = platform_device_alloc("mipi-i3c-hci", dev_id); 296 - if (!hci->pdev) 297 - return -ENOMEM; 298 - 299 - hci->pdev->dev.parent = &pci->dev; 300 - device_set_node(&hci->pdev->dev, dev_fwnode(&pci->dev)); 301 - 302 - ret = platform_device_add_resources(hci->pdev, res, ARRAY_SIZE(res)); 303 - if (ret) 304 - goto err; 210 + ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_ALL_TYPES); 211 + if (ret < 0) 212 + return ret; 305 213 306 214 hci->info = (const struct mipi_i3c_hci_pci_info *)id->driver_data; 307 - if (hci->info && hci->info->init) { 308 - ret = hci->info->init(hci); 309 - if (ret) 310 - goto err; 311 - } 312 215 313 - ret = platform_device_add(hci->pdev); 216 + ret = hci->info->init ? hci->info->init(hci) : 0; 217 + if (ret) 218 + return ret; 219 + 220 + ret = mipi_i3c_hci_pci_add_instances(hci); 314 221 if (ret) 315 222 goto err_exit; 316 223 317 224 pci_set_drvdata(pci, hci); 318 225 226 + mipi_i3c_hci_pci_rpm_allow(&pci->dev); 227 + 319 228 return 0; 320 229 321 230 err_exit: 322 - if (hci->info && hci->info->exit) 231 + if (hci->info->exit) 323 232 hci->info->exit(hci); 324 - err: 325 - platform_device_put(hci->pdev); 326 - ida_free(&mipi_i3c_hci_pci_ida, dev_id); 327 233 return ret; 328 234 } 329 235 330 236 static void mipi_i3c_hci_pci_remove(struct pci_dev *pci) 331 237 { 332 238 struct mipi_i3c_hci_pci *hci = pci_get_drvdata(pci); 333 - struct platform_device *pdev = hci->pdev; 334 - int dev_id = pdev->id; 335 239 336 - if (hci->info && hci->info->exit) 240 + if (hci->info->exit) 337 241 hci->info->exit(hci); 338 242 339 - platform_device_unregister(pdev); 340 - ida_free(&mipi_i3c_hci_pci_ida, dev_id); 243 + mipi_i3c_hci_pci_rpm_forbid(&pci->dev); 244 + 245 + mfd_remove_devices(&pci->dev); 341 246 } 247 + 248 + /* PM ops must exist for PCI to put a device to a low power state */ 249 + static const struct dev_pm_ops mipi_i3c_hci_pci_pm_ops = { 250 + }; 342 251 343 252 static const struct pci_device_id mipi_i3c_hci_pci_devices[] = { 344 253 /* Wildcat Lake-U */ 345 - { PCI_VDEVICE(INTEL, 0x4d7c), (kernel_ulong_t)&intel_info}, 346 - { PCI_VDEVICE(INTEL, 0x4d6f), (kernel_ulong_t)&intel_info}, 254 + { PCI_VDEVICE(INTEL, 0x4d7c), (kernel_ulong_t)&intel_mi_1_info}, 255 + { PCI_VDEVICE(INTEL, 0x4d6f), (kernel_ulong_t)&intel_si_2_info}, 347 256 /* Panther Lake-H */ 348 - { PCI_VDEVICE(INTEL, 0xe37c), (kernel_ulong_t)&intel_info}, 349 - { PCI_VDEVICE(INTEL, 0xe36f), (kernel_ulong_t)&intel_info}, 257 + { PCI_VDEVICE(INTEL, 0xe37c), (kernel_ulong_t)&intel_mi_1_info}, 258 + { PCI_VDEVICE(INTEL, 0xe36f), (kernel_ulong_t)&intel_si_2_info}, 350 259 /* Panther Lake-P */ 351 - { PCI_VDEVICE(INTEL, 0xe47c), (kernel_ulong_t)&intel_info}, 352 - { PCI_VDEVICE(INTEL, 0xe46f), (kernel_ulong_t)&intel_info}, 260 + { PCI_VDEVICE(INTEL, 0xe47c), (kernel_ulong_t)&intel_mi_1_info}, 261 + { PCI_VDEVICE(INTEL, 0xe46f), (kernel_ulong_t)&intel_si_2_info}, 353 262 /* Nova Lake-S */ 354 - { PCI_VDEVICE(INTEL, 0x6e2c), (kernel_ulong_t)&intel_info}, 355 - { PCI_VDEVICE(INTEL, 0x6e2d), (kernel_ulong_t)&intel_info}, 263 + { PCI_VDEVICE(INTEL, 0x6e2c), (kernel_ulong_t)&intel_mi_1_info}, 264 + { PCI_VDEVICE(INTEL, 0x6e2d), (kernel_ulong_t)&intel_mi_2_info}, 356 265 { }, 357 266 }; 358 267 MODULE_DEVICE_TABLE(pci, mipi_i3c_hci_pci_devices); ··· 346 287 .id_table = mipi_i3c_hci_pci_devices, 347 288 .probe = mipi_i3c_hci_pci_probe, 348 289 .remove = mipi_i3c_hci_pci_remove, 290 + .driver = { 291 + .pm = pm_ptr(&mipi_i3c_hci_pci_pm_ops) 292 + }, 349 293 }; 350 294 351 295 module_pci_driver(mipi_i3c_hci_pci_driver);

+44 -20

drivers/i3c/master/mipi-i3c-hci/pio.c

··· 15 15 #include "cmd.h" 16 16 #include "ibi.h" 17 17 18 - 19 18 /* 20 19 * PIO Access Area 21 20 */ ··· 135 136 u32 enabled_irqs; 136 137 }; 137 138 138 - static int hci_pio_init(struct i3c_hci *hci) 139 + static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr) 139 140 { 140 - struct hci_pio_data *pio; 141 141 u32 val, size_val, rx_thresh, tx_thresh, ibi_val; 142 - 143 - pio = kzalloc(sizeof(*pio), GFP_KERNEL); 144 - if (!pio) 145 - return -ENOMEM; 146 - 147 - hci->io_data = pio; 148 - spin_lock_init(&pio->lock); 142 + struct hci_pio_data *pio = hci->io_data; 149 143 150 144 size_val = pio_reg_read(QUEUE_SIZE); 151 - dev_info(&hci->master.dev, "CMD/RESP FIFO = %ld entries\n", 152 - FIELD_GET(CR_QUEUE_SIZE, size_val)); 153 - dev_info(&hci->master.dev, "IBI FIFO = %ld bytes\n", 154 - 4 * FIELD_GET(IBI_STATUS_SIZE, size_val)); 155 - dev_info(&hci->master.dev, "RX data FIFO = %d bytes\n", 156 - 4 * (2 << FIELD_GET(RX_DATA_BUFFER_SIZE, size_val))); 157 - dev_info(&hci->master.dev, "TX data FIFO = %d bytes\n", 158 - 4 * (2 << FIELD_GET(TX_DATA_BUFFER_SIZE, size_val))); 145 + if (size_val_ptr) 146 + *size_val_ptr = size_val; 159 147 160 148 /* 161 149 * Let's initialize data thresholds to half of the actual FIFO size. ··· 188 202 189 203 /* Always accept error interrupts (will be activated on first xfer) */ 190 204 pio->enabled_irqs = STAT_ALL_ERRORS; 205 + } 206 + 207 + static void hci_pio_suspend(struct i3c_hci *hci) 208 + { 209 + pio_reg_write(INTR_SIGNAL_ENABLE, 0); 210 + 211 + i3c_hci_sync_irq_inactive(hci); 212 + } 213 + 214 + static void hci_pio_resume(struct i3c_hci *hci) 215 + { 216 + __hci_pio_init(hci, NULL); 217 + } 218 + 219 + static int hci_pio_init(struct i3c_hci *hci) 220 + { 221 + struct hci_pio_data *pio; 222 + u32 size_val; 223 + 224 + pio = devm_kzalloc(hci->master.dev.parent, sizeof(*pio), GFP_KERNEL); 225 + if (!pio) 226 + return -ENOMEM; 227 + 228 + hci->io_data = pio; 229 + spin_lock_init(&pio->lock); 230 + 231 + __hci_pio_init(hci, &size_val); 232 + 233 + dev_dbg(&hci->master.dev, "CMD/RESP FIFO = %ld entries\n", 234 + FIELD_GET(CR_QUEUE_SIZE, size_val)); 235 + dev_dbg(&hci->master.dev, "IBI FIFO = %ld bytes\n", 236 + 4 * FIELD_GET(IBI_STATUS_SIZE, size_val)); 237 + dev_dbg(&hci->master.dev, "RX data FIFO = %d bytes\n", 238 + 4 * (2 << FIELD_GET(RX_DATA_BUFFER_SIZE, size_val))); 239 + dev_dbg(&hci->master.dev, "TX data FIFO = %d bytes\n", 240 + 4 * (2 << FIELD_GET(TX_DATA_BUFFER_SIZE, size_val))); 191 241 192 242 return 0; 193 243 } ··· 234 212 235 213 pio_reg_write(INTR_SIGNAL_ENABLE, 0x0); 236 214 215 + i3c_hci_sync_irq_inactive(hci); 216 + 237 217 if (pio) { 238 218 dev_dbg(&hci->master.dev, "status = %#x/%#x", 239 219 pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); ··· 243 219 BUG_ON(pio->curr_rx); 244 220 BUG_ON(pio->curr_tx); 245 221 BUG_ON(pio->curr_resp); 246 - kfree(pio); 247 - hci->io_data = NULL; 248 222 } 249 223 } 250 224 ··· 1071 1049 .request_ibi = hci_pio_request_ibi, 1072 1050 .free_ibi = hci_pio_free_ibi, 1073 1051 .recycle_ibi_slot = hci_pio_recycle_ibi_slot, 1052 + .suspend = hci_pio_suspend, 1053 + .resume = hci_pio_resume, 1074 1054 };

+200 -119

drivers/i3c/master/renesas-i3c.c

··· 198 198 #define RENESAS_I3C_MAX_DEVS 8 199 199 #define I2C_INIT_MSG -1 200 200 201 + #define RENESAS_I3C_TCLK_IDX 1 202 + 201 203 enum i3c_internal_state { 202 204 I3C_INTERNAL_STATE_DISABLED, 203 205 I3C_INTERNAL_STATE_CONTROLLER_IDLE, ··· 256 254 enum i3c_internal_state internal_state; 257 255 u16 maxdevs; 258 256 u32 free_pos; 257 + u32 dyn_addr; 259 258 u32 i2c_STDBR; 260 259 u32 i3c_STDBR; 260 + unsigned long rate; 261 261 u8 addrs[RENESAS_I3C_MAX_DEVS]; 262 262 struct renesas_i3c_xferqueue xferqueue; 263 263 void __iomem *regs; 264 - struct clk *tclk; 264 + u32 *DATBASn; 265 + struct clk_bulk_data *clks; 266 + struct reset_control *presetn; 267 + struct reset_control *tresetn; 268 + u8 num_clks; 269 + u8 refclk_div; 265 270 }; 266 271 267 272 struct renesas_i3c_i2c_dev_data { ··· 279 270 const char *name; 280 271 irq_handler_t isr; 281 272 const char *desc; 282 - }; 283 - 284 - struct renesas_i3c_config { 285 - unsigned int has_pclkrw:1; 286 273 }; 287 274 288 275 static inline void renesas_i3c_reg_update(void __iomem *reg, u32 mask, u32 val) ··· 482 477 0, 1000, false, i3c->regs, RSTCTL); 483 478 } 484 479 485 - static int renesas_i3c_bus_init(struct i3c_master_controller *m) 480 + static void renesas_i3c_hw_init(struct renesas_i3c *i3c) 486 481 { 487 - struct renesas_i3c *i3c = to_renesas_i3c(m); 488 - struct i3c_bus *bus = i3c_master_get_bus(m); 489 - struct i3c_device_info info = {}; 490 - struct i2c_timings t; 491 - unsigned long rate; 492 - u32 double_SBR, val; 493 - int cks, pp_high_ticks, pp_low_ticks, i3c_total_ticks; 494 - int od_high_ticks, od_low_ticks, i2c_total_ticks; 495 - int ret; 496 - 497 - rate = clk_get_rate(i3c->tclk); 498 - if (!rate) 499 - return -EINVAL; 500 - 501 - ret = renesas_i3c_reset(i3c); 502 - if (ret) 503 - return ret; 504 - 505 - i2c_total_ticks = DIV_ROUND_UP(rate, bus->scl_rate.i2c); 506 - i3c_total_ticks = DIV_ROUND_UP(rate, bus->scl_rate.i3c); 507 - 508 - i2c_parse_fw_timings(&m->dev, &t, true); 509 - 510 - for (cks = 0; cks < 7; cks++) { 511 - /* SCL low-period calculation in Open-drain mode */ 512 - od_low_ticks = ((i2c_total_ticks * 6) / 10); 513 - 514 - /* SCL clock calculation in Push-Pull mode */ 515 - if (bus->mode == I3C_BUS_MODE_PURE) 516 - pp_high_ticks = ((i3c_total_ticks * 5) / 10); 517 - else 518 - pp_high_ticks = DIV_ROUND_UP(I3C_BUS_THIGH_MIXED_MAX_NS, 519 - NSEC_PER_SEC / rate); 520 - pp_low_ticks = i3c_total_ticks - pp_high_ticks; 521 - 522 - if ((od_low_ticks / 2) <= 0xFF && pp_low_ticks < 0x3F) 523 - break; 524 - 525 - i2c_total_ticks /= 2; 526 - i3c_total_ticks /= 2; 527 - rate /= 2; 528 - } 529 - 530 - /* SCL clock period calculation in Open-drain mode */ 531 - if ((od_low_ticks / 2) > 0xFF || pp_low_ticks > 0x3F) { 532 - dev_err(&m->dev, "invalid speed (i2c-scl = %lu Hz, i3c-scl = %lu Hz). Too slow.\n", 533 - (unsigned long)bus->scl_rate.i2c, (unsigned long)bus->scl_rate.i3c); 534 - return -EINVAL; 535 - } 536 - 537 - /* SCL high-period calculation in Open-drain mode */ 538 - od_high_ticks = i2c_total_ticks - od_low_ticks; 539 - 540 - /* Standard Bit Rate setting */ 541 - double_SBR = od_low_ticks > 0xFF ? 1 : 0; 542 - i3c->i3c_STDBR = (double_SBR ? STDBR_DSBRPO : 0) | 543 - STDBR_SBRLO(double_SBR, od_low_ticks) | 544 - STDBR_SBRHO(double_SBR, od_high_ticks) | 545 - STDBR_SBRLP(pp_low_ticks) | 546 - STDBR_SBRHP(pp_high_ticks); 547 - 548 - od_low_ticks -= t.scl_fall_ns / (NSEC_PER_SEC / rate) + 1; 549 - od_high_ticks -= t.scl_rise_ns / (NSEC_PER_SEC / rate) + 1; 550 - i3c->i2c_STDBR = (double_SBR ? STDBR_DSBRPO : 0) | 551 - STDBR_SBRLO(double_SBR, od_low_ticks) | 552 - STDBR_SBRHO(double_SBR, od_high_ticks) | 553 - STDBR_SBRLP(pp_low_ticks) | 554 - STDBR_SBRHP(pp_high_ticks); 555 - renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR); 556 - 557 - /* Extended Bit Rate setting */ 558 - renesas_writel(i3c->regs, EXTBR, EXTBR_EBRLO(od_low_ticks) | 559 - EXTBR_EBRHO(od_high_ticks) | 560 - EXTBR_EBRLP(pp_low_ticks) | 561 - EXTBR_EBRHP(pp_high_ticks)); 562 - 563 - renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(cks)); 482 + u32 val; 564 483 565 484 /* Disable Slave Mode */ 566 485 renesas_writel(i3c->regs, SVCTL, 0); 567 486 568 487 /* Initialize Queue/Buffer threshold */ 569 488 renesas_writel(i3c->regs, NQTHCTL, NQTHCTL_IBIDSSZ(6) | 570 - NQTHCTL_CMDQTH(1)); 489 + NQTHCTL_CMDQTH(1)); 571 490 572 491 /* The only supported configuration is two entries*/ 573 492 renesas_writel(i3c->regs, NTBTHCTL0, 0); ··· 515 586 renesas_set_bit(i3c->regs, BCTL, BCTL_HJACKCTL); 516 587 517 588 renesas_writel(i3c->regs, IBINCTL, IBINCTL_NRHJCTL | IBINCTL_NRMRCTL | 518 - IBINCTL_NRSIRCTL); 589 + IBINCTL_NRSIRCTL); 519 590 520 591 renesas_writel(i3c->regs, SCSTLCTL, 0); 521 592 renesas_set_bit(i3c->regs, SCSTRCTL, SCSTRCTL_ACKTWE); 522 593 523 594 /* Bus condition timing */ 524 - val = DIV_ROUND_UP(I3C_BUS_TBUF_MIXED_FM_MIN_NS, NSEC_PER_SEC / rate); 595 + val = DIV_ROUND_UP(I3C_BUS_TBUF_MIXED_FM_MIN_NS, 596 + NSEC_PER_SEC / i3c->rate); 525 597 renesas_writel(i3c->regs, BFRECDT, BFRECDT_FRECYC(val)); 526 598 527 - val = DIV_ROUND_UP(I3C_BUS_TAVAL_MIN_NS, NSEC_PER_SEC / rate); 599 + val = DIV_ROUND_UP(I3C_BUS_TAVAL_MIN_NS, 600 + NSEC_PER_SEC / i3c->rate); 528 601 renesas_writel(i3c->regs, BAVLCDT, BAVLCDT_AVLCYC(val)); 529 602 530 - val = DIV_ROUND_UP(I3C_BUS_TIDLE_MIN_NS, NSEC_PER_SEC / rate); 603 + val = DIV_ROUND_UP(I3C_BUS_TIDLE_MIN_NS, 604 + NSEC_PER_SEC / i3c->rate); 531 605 renesas_writel(i3c->regs, BIDLCDT, BIDLCDT_IDLCYC(val)); 606 + } 607 + 608 + static int renesas_i3c_bus_init(struct i3c_master_controller *m) 609 + { 610 + struct renesas_i3c *i3c = to_renesas_i3c(m); 611 + struct i3c_bus *bus = i3c_master_get_bus(m); 612 + struct i3c_device_info info = {}; 613 + struct i2c_timings t; 614 + u32 double_SBR; 615 + int cks, pp_high_ticks, pp_low_ticks, i3c_total_ticks; 616 + int od_high_ticks, od_low_ticks, i2c_total_ticks; 617 + int ret; 618 + 619 + i3c->rate = clk_get_rate(i3c->clks[RENESAS_I3C_TCLK_IDX].clk); 620 + if (!i3c->rate) 621 + return -EINVAL; 622 + 623 + ret = renesas_i3c_reset(i3c); 624 + if (ret) 625 + return ret; 626 + 627 + i2c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c); 628 + i3c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i3c); 629 + 630 + i2c_parse_fw_timings(&m->dev, &t, true); 631 + 632 + for (cks = 0; cks < 7; cks++) { 633 + /* SCL low-period calculation in Open-drain mode */ 634 + od_low_ticks = ((i2c_total_ticks * 6) / 10); 635 + 636 + /* SCL clock calculation in Push-Pull mode */ 637 + if (bus->mode == I3C_BUS_MODE_PURE) 638 + pp_high_ticks = ((i3c_total_ticks * 5) / 10); 639 + else 640 + pp_high_ticks = DIV_ROUND_UP(I3C_BUS_THIGH_MIXED_MAX_NS, 641 + NSEC_PER_SEC / i3c->rate); 642 + pp_low_ticks = i3c_total_ticks - pp_high_ticks; 643 + 644 + if ((od_low_ticks / 2) <= 0xFF && pp_low_ticks < 0x3F) 645 + break; 646 + 647 + i2c_total_ticks /= 2; 648 + i3c_total_ticks /= 2; 649 + i3c->rate /= 2; 650 + } 651 + 652 + /* SCL clock period calculation in Open-drain mode */ 653 + if ((od_low_ticks / 2) > 0xFF || pp_low_ticks > 0x3F) { 654 + dev_err(&m->dev, "invalid speed (i2c-scl = %lu Hz, i3c-scl = %lu Hz). Too slow.\n", 655 + (unsigned long)bus->scl_rate.i2c, (unsigned long)bus->scl_rate.i3c); 656 + return -EINVAL; 657 + } 658 + 659 + /* SCL high-period calculation in Open-drain mode */ 660 + od_high_ticks = i2c_total_ticks - od_low_ticks; 661 + 662 + /* Standard Bit Rate setting */ 663 + double_SBR = od_low_ticks > 0xFF ? 1 : 0; 664 + i3c->i3c_STDBR = (double_SBR ? STDBR_DSBRPO : 0) | 665 + STDBR_SBRLO(double_SBR, od_low_ticks) | 666 + STDBR_SBRHO(double_SBR, od_high_ticks) | 667 + STDBR_SBRLP(pp_low_ticks) | 668 + STDBR_SBRHP(pp_high_ticks); 669 + 670 + od_low_ticks -= t.scl_fall_ns / (NSEC_PER_SEC / i3c->rate) + 1; 671 + od_high_ticks -= t.scl_rise_ns / (NSEC_PER_SEC / i3c->rate) + 1; 672 + i3c->i2c_STDBR = (double_SBR ? STDBR_DSBRPO : 0) | 673 + STDBR_SBRLO(double_SBR, od_low_ticks) | 674 + STDBR_SBRHO(double_SBR, od_high_ticks) | 675 + STDBR_SBRLP(pp_low_ticks) | 676 + STDBR_SBRHP(pp_high_ticks); 677 + renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR); 678 + 679 + /* Extended Bit Rate setting */ 680 + renesas_writel(i3c->regs, EXTBR, EXTBR_EBRLO(od_low_ticks) | 681 + EXTBR_EBRHO(od_high_ticks) | 682 + EXTBR_EBRLP(pp_low_ticks) | 683 + EXTBR_EBRHP(pp_high_ticks)); 684 + 685 + renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(cks)); 686 + i3c->refclk_div = cks; 687 + 688 + /* I3C hw init*/ 689 + renesas_i3c_hw_init(i3c); 532 690 533 691 ret = i3c_master_get_free_addr(m, 0); 534 692 if (ret < 0) 535 693 return ret; 536 694 695 + i3c->dyn_addr = ret; 537 696 renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYAD(ret) | MSDVAD_MDYADV); 538 697 539 698 memset(&info, 0, sizeof(info)); ··· 1318 1301 static int renesas_i3c_probe(struct platform_device *pdev) 1319 1302 { 1320 1303 struct renesas_i3c *i3c; 1321 - struct reset_control *reset; 1322 - struct clk *clk; 1323 - const struct renesas_i3c_config *config = of_device_get_match_data(&pdev->dev); 1324 1304 int ret, i; 1325 - 1326 - if (!config) 1327 - return -ENODATA; 1328 1305 1329 1306 i3c = devm_kzalloc(&pdev->dev, sizeof(*i3c), GFP_KERNEL); 1330 1307 if (!i3c) ··· 1328 1317 if (IS_ERR(i3c->regs)) 1329 1318 return PTR_ERR(i3c->regs); 1330 1319 1331 - clk = devm_clk_get_enabled(&pdev->dev, "pclk"); 1332 - if (IS_ERR(clk)) 1333 - return PTR_ERR(clk); 1320 + ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &i3c->clks); 1321 + if (ret <= RENESAS_I3C_TCLK_IDX) 1322 + return dev_err_probe(&pdev->dev, ret < 0 ? ret : -EINVAL, 1323 + "Failed to get clocks (need > %d, got %d)\n", 1324 + RENESAS_I3C_TCLK_IDX, ret); 1325 + i3c->num_clks = ret; 1334 1326 1335 - if (config->has_pclkrw) { 1336 - clk = devm_clk_get_enabled(&pdev->dev, "pclkrw"); 1337 - if (IS_ERR(clk)) 1338 - return PTR_ERR(clk); 1339 - } 1340 - 1341 - i3c->tclk = devm_clk_get_enabled(&pdev->dev, "tclk"); 1342 - if (IS_ERR(i3c->tclk)) 1343 - return PTR_ERR(i3c->tclk); 1344 - 1345 - reset = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, "tresetn"); 1346 - if (IS_ERR(reset)) 1347 - return dev_err_probe(&pdev->dev, PTR_ERR(reset), 1327 + i3c->tresetn = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, "tresetn"); 1328 + if (IS_ERR(i3c->tresetn)) 1329 + return dev_err_probe(&pdev->dev, PTR_ERR(i3c->tresetn), 1348 1330 "Error: missing tresetn ctrl\n"); 1349 1331 1350 - reset = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, "presetn"); 1351 - if (IS_ERR(reset)) 1352 - return dev_err_probe(&pdev->dev, PTR_ERR(reset), 1332 + i3c->presetn = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, "presetn"); 1333 + if (IS_ERR(i3c->presetn)) 1334 + return dev_err_probe(&pdev->dev, PTR_ERR(i3c->presetn), 1353 1335 "Error: missing presetn ctrl\n"); 1354 1336 1355 1337 spin_lock_init(&i3c->xferqueue.lock); ··· 1368 1364 i3c->maxdevs = RENESAS_I3C_MAX_DEVS; 1369 1365 i3c->free_pos = GENMASK(i3c->maxdevs - 1, 0); 1370 1366 1367 + /* Allocate dynamic Device Address Table backup. */ 1368 + i3c->DATBASn = devm_kzalloc(&pdev->dev, sizeof(u32) * i3c->maxdevs, 1369 + GFP_KERNEL); 1370 + if (!i3c->DATBASn) 1371 + return -ENOMEM; 1372 + 1371 1373 return i3c_master_register(&i3c->base, &pdev->dev, &renesas_i3c_ops, false); 1372 1374 } 1373 1375 ··· 1384 1374 i3c_master_unregister(&i3c->base); 1385 1375 } 1386 1376 1387 - static const struct renesas_i3c_config empty_i3c_config = { 1388 - }; 1377 + static int renesas_i3c_suspend_noirq(struct device *dev) 1378 + { 1379 + struct renesas_i3c *i3c = dev_get_drvdata(dev); 1380 + int i, ret; 1389 1381 1390 - static const struct renesas_i3c_config r9a09g047_i3c_config = { 1391 - .has_pclkrw = 1, 1382 + i2c_mark_adapter_suspended(&i3c->base.i2c); 1383 + 1384 + /* Store Device Address Table values. */ 1385 + for (i = 0; i < i3c->maxdevs; i++) 1386 + i3c->DATBASn[i] = renesas_readl(i3c->regs, DATBAS(i)); 1387 + 1388 + ret = reset_control_assert(i3c->presetn); 1389 + if (ret) 1390 + goto err_mark_resumed; 1391 + 1392 + ret = reset_control_assert(i3c->tresetn); 1393 + if (ret) 1394 + goto err_presetn; 1395 + 1396 + clk_bulk_disable(i3c->num_clks, i3c->clks); 1397 + 1398 + return 0; 1399 + 1400 + err_presetn: 1401 + reset_control_deassert(i3c->presetn); 1402 + err_mark_resumed: 1403 + i2c_mark_adapter_resumed(&i3c->base.i2c); 1404 + 1405 + return ret; 1406 + } 1407 + 1408 + static int renesas_i3c_resume_noirq(struct device *dev) 1409 + { 1410 + struct renesas_i3c *i3c = dev_get_drvdata(dev); 1411 + int i, ret; 1412 + 1413 + ret = reset_control_deassert(i3c->presetn); 1414 + if (ret) 1415 + return ret; 1416 + 1417 + ret = reset_control_deassert(i3c->tresetn); 1418 + if (ret) 1419 + goto err_presetn; 1420 + 1421 + ret = clk_bulk_enable(i3c->num_clks, i3c->clks); 1422 + if (ret) 1423 + goto err_tresetn; 1424 + 1425 + /* Re-store I3C registers value. */ 1426 + renesas_writel(i3c->regs, REFCKCTL, 1427 + REFCKCTL_IREFCKS(i3c->refclk_div)); 1428 + renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYADV | 1429 + MSDVAD_MDYAD(i3c->dyn_addr)); 1430 + 1431 + /* Restore Device Address Table values. */ 1432 + for (i = 0; i < i3c->maxdevs; i++) 1433 + renesas_writel(i3c->regs, DATBAS(i), i3c->DATBASn[i]); 1434 + 1435 + /* I3C hw init. */ 1436 + renesas_i3c_hw_init(i3c); 1437 + 1438 + i2c_mark_adapter_resumed(&i3c->base.i2c); 1439 + 1440 + return 0; 1441 + 1442 + err_tresetn: 1443 + reset_control_assert(i3c->tresetn); 1444 + err_presetn: 1445 + reset_control_assert(i3c->presetn); 1446 + return ret; 1447 + } 1448 + 1449 + static const struct dev_pm_ops renesas_i3c_pm_ops = { 1450 + NOIRQ_SYSTEM_SLEEP_PM_OPS(renesas_i3c_suspend_noirq, 1451 + renesas_i3c_resume_noirq) 1392 1452 }; 1393 1453 1394 1454 static const struct of_device_id renesas_i3c_of_ids[] = { 1395 - { .compatible = "renesas,r9a08g045-i3c", .data = &empty_i3c_config }, 1396 - { .compatible = "renesas,r9a09g047-i3c", .data = &r9a09g047_i3c_config }, 1455 + { .compatible = "renesas,r9a08g045-i3c" }, 1456 + { .compatible = "renesas,r9a09g047-i3c" }, 1397 1457 { /* sentinel */ }, 1398 1458 }; 1399 1459 MODULE_DEVICE_TABLE(of, renesas_i3c_of_ids); ··· 1474 1394 .driver = { 1475 1395 .name = "renesas-i3c", 1476 1396 .of_match_table = renesas_i3c_of_ids, 1397 + .pm = pm_sleep_ptr(&renesas_i3c_pm_ops), 1477 1398 }, 1478 1399 }; 1479 1400 module_platform_driver(renesas_i3c);

+2 -2

drivers/i3c/master/svc-i3c-master.c

··· 533 533 static void svc_i3c_master_ibi_isr(struct svc_i3c_master *master) 534 534 { 535 535 struct svc_i3c_i2c_dev_data *data; 536 + struct i3c_dev_desc *dev = NULL; 536 537 unsigned int ibitype, ibiaddr; 537 - struct i3c_dev_desc *dev; 538 538 u32 status, val; 539 539 int ret; 540 540 ··· 627 627 * for the slave to interrupt again. 628 628 */ 629 629 if (svc_i3c_master_error(master)) { 630 - if (master->ibi.tbq_slot) { 630 + if (master->ibi.tbq_slot && dev) { 631 631 data = i3c_dev_get_master_data(dev); 632 632 i3c_generic_ibi_recycle_slot(data->ibi_pool, 633 633 master->ibi.tbq_slot);

+14 -10

include/linux/i3c/device.h

··· 25 25 * @I3C_ERROR_M2: M2 error 26 26 * 27 27 * These are the standard error codes as defined by the I3C specification. 28 - * When -EIO is returned by the i3c_device_do_priv_xfers() or 28 + * When -EIO is returned by the i3c_device_do_i3c_xfers() or 29 29 * i3c_device_send_hdr_cmds() one can check the error code in 30 30 * &struct_i3c_xfer.err or &struct i3c_hdr_cmd.err to get a better idea of 31 31 * what went wrong. ··· 78 78 } data; 79 79 enum i3c_error_code err; 80 80 }; 81 - 82 - /* keep back compatible */ 83 - #define i3c_priv_xfer i3c_xfer 84 81 85 82 /** 86 83 * enum i3c_dcr - I3C DCR values ··· 305 308 i3c_i2c_driver_unregister, \ 306 309 __i2cdrv) 307 310 311 + #if IS_ENABLED(CONFIG_I3C) 308 312 int i3c_device_do_xfers(struct i3c_device *dev, struct i3c_xfer *xfers, 309 313 int nxfers, enum i3c_xfer_mode mode); 310 - 311 - static inline int i3c_device_do_priv_xfers(struct i3c_device *dev, 312 - struct i3c_xfer *xfers, 313 - int nxfers) 314 + u32 i3c_device_get_supported_xfer_mode(struct i3c_device *dev); 315 + #else 316 + static inline int 317 + i3c_device_do_xfers(struct i3c_device *dev, struct i3c_xfer *xfers, 318 + int nxfers, enum i3c_xfer_mode mode) 314 319 { 315 - return i3c_device_do_xfers(dev, xfers, nxfers, I3C_SDR); 320 + return -EOPNOTSUPP; 316 321 } 322 + 323 + static inline u32 i3c_device_get_supported_xfer_mode(struct i3c_device *dev) 324 + { 325 + return 0; 326 + } 327 + #endif 317 328 318 329 int i3c_device_do_setdasa(struct i3c_device *dev); 319 330 ··· 363 358 void i3c_device_free_ibi(struct i3c_device *dev); 364 359 int i3c_device_enable_ibi(struct i3c_device *dev); 365 360 int i3c_device_disable_ibi(struct i3c_device *dev); 366 - u32 i3c_device_get_supported_xfer_mode(struct i3c_device *dev); 367 361 368 362 #endif /* I3C_DEV_H */

+11

include/linux/i3c/master.h

··· 462 462 * @enable_hotjoin: enable hot join event detect. 463 463 * @disable_hotjoin: disable hot join event detect. 464 464 * @set_speed: adjust I3C open drain mode timing. 465 + * @set_dev_nack_retry: configure device NACK retry count for the master 466 + * controller. 465 467 */ 466 468 struct i3c_master_controller_ops { 467 469 int (*bus_init)(struct i3c_master_controller *master); ··· 493 491 int (*enable_hotjoin)(struct i3c_master_controller *master); 494 492 int (*disable_hotjoin)(struct i3c_master_controller *master); 495 493 int (*set_speed)(struct i3c_master_controller *master, enum i3c_open_drain_speed speed); 494 + int (*set_dev_nack_retry)(struct i3c_master_controller *master, 495 + unsigned long dev_nack_retry_cnt); 496 496 }; 497 497 498 498 /** ··· 509 505 * @secondary: true if the master is a secondary master 510 506 * @init_done: true when the bus initialization is done 511 507 * @hotjoin: true if the master support hotjoin 508 + * @rpm_allowed: true if Runtime PM allowed 509 + * @rpm_ibi_allowed: true if IBI and Hot-Join allowed while runtime suspended 512 510 * @boardinfo.i3c: list of I3C boardinfo objects 513 511 * @boardinfo.i2c: list of I2C boardinfo objects 514 512 * @boardinfo: board-level information attached to devices connected on the bus ··· 520 514 * in a thread context. Typical examples are Hot Join processing which 521 515 * requires taking the bus lock in maintenance, which in turn, can only 522 516 * be done from a sleep-able context 517 + * @dev_nack_retry_count: retry count when slave device nack 523 518 * 524 519 * A &struct i3c_master_controller has to be registered to the I3C subsystem 525 520 * through i3c_master_register(). None of &struct i3c_master_controller fields ··· 535 528 unsigned int secondary : 1; 536 529 unsigned int init_done : 1; 537 530 unsigned int hotjoin: 1; 531 + unsigned int rpm_allowed: 1; 532 + unsigned int rpm_ibi_allowed: 1; 538 533 struct { 539 534 struct list_head i3c; 540 535 struct list_head i2c; 541 536 } boardinfo; 542 537 struct i3c_bus bus; 543 538 struct workqueue_struct *wq; 539 + unsigned int dev_nack_retry_count; 544 540 }; 545 541 546 542 /** ··· 605 595 int i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, 606 596 u8 addr); 607 597 int i3c_master_do_daa(struct i3c_master_controller *master); 598 + int i3c_master_do_daa_ext(struct i3c_master_controller *master, bool rstdaa); 608 599 struct i3c_dma *i3c_master_dma_map_single(struct device *dev, void *ptr, 609 600 size_t len, bool force_bounce, 610 601 enum dma_data_direction dir);

+15

include/linux/platform_data/mipi-i3c-hci.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + #ifndef INCLUDE_PLATFORM_DATA_MIPI_I3C_HCI_H 3 + #define INCLUDE_PLATFORM_DATA_MIPI_I3C_HCI_H 4 + 5 + #include <linux/compiler_types.h> 6 + 7 + /** 8 + * struct mipi_i3c_hci_platform_data - Platform-dependent data for mipi_i3c_hci 9 + * @base_regs: Register set base address (to support multi-bus instances) 10 + */ 11 + struct mipi_i3c_hci_platform_data { 12 + void __iomem *base_regs; 13 + }; 14 + 15 + #endif

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