Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-intel-next-2023-12-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
- Improve display debug msgs and other general clean-ups (Ville, Rahuul)
- PSR fixes and improvements around selective fetch (Jouni, Ville)
- Remove FBC restrictions for Xe2LPD displays (Vinod)
- Skip some timing checks on BXT/GLK DSI transcoders (Ville)
- DP MST Fixes (Ville)
- Correct the input parameter on _intel_dsb_commit (heminhong)
- Fix IP version of the display WAs (Bala)
- DGFX uses direct VBT pin mapping (Clint)
- Proper handling of bool on PIPE_CONF_CHECK macros (Jani)
- Skip state verification with TBT-ALT mod (Mika Kahona)
- General organization of display code for reusage with Xe
(Jouni, Luca, Jani, Maarten)
- Squelch a sparse warning (Jani)
- Don't use "proxy" headers (Andy Shevchenko)
- Use devm_gpiod_get() for all GPIOs (Hans)
- Fix ADL+ tiled plane stride (Ville)
- Use octal permissions in display debugfs (Jani)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZXIWG6bRYaUw0w6-@intel.com
+750
-481
+3
-1
drivers/gpu/drm/i915/Makefile
+3
-1
drivers/gpu/drm/i915/Makefile
···
280
280
display/intel_dsb.o \
281
281
display/intel_dsb_buffer.o \
282
282
display/intel_fb.o \
283
+
display/intel_fb_bo.o \
283
284
display/intel_fb_pin.o \
284
285
display/intel_fbc.o \
285
286
display/intel_fdi.o \
···
319
318
display/intel_acpi.o \
320
319
display/intel_opregion.o
321
320
i915-$(CONFIG_DRM_FBDEV_EMULATION) += \
322
-
display/intel_fbdev.o
321
+
display/intel_fbdev.o \
322
+
display/intel_fbdev_fb.o
323
323
i915-$(CONFIG_DEBUG_FS) += \
324
324
display/intel_display_debugfs.o \
325
325
display/intel_display_debugfs_params.o \
+4
-4
drivers/gpu/drm/i915/display/i9xx_wm.c
+4
-4
drivers/gpu/drm/i915/display/i9xx_wm.c
···
2477
2477
* FIFO size is only half of the self
2478
2478
* refresh FIFO size on ILK/SNB.
2479
2479
*/
2480
-
if (DISPLAY_VER(dev_priv) <= 6)
2480
+
if (DISPLAY_VER(dev_priv) < 7)
2481
2481
fifo_size /= 2;
2482
2482
}
2483
2483
···
2818
2818
usable_level = dev_priv->display.wm.num_levels - 1;
2819
2819
2820
2820
/* ILK/SNB: LP2+ watermarks only w/o sprites */
2821
-
if (DISPLAY_VER(dev_priv) <= 6 && pipe_wm->sprites_enabled)
2821
+
if (DISPLAY_VER(dev_priv) < 7 && pipe_wm->sprites_enabled)
2822
2822
usable_level = 1;
2823
2823
2824
2824
/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
···
2961
2961
int last_enabled_level = num_levels - 1;
2962
2962
2963
2963
/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2964
-
if ((DISPLAY_VER(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2964
+
if ((DISPLAY_VER(dev_priv) < 7 || IS_IVYBRIDGE(dev_priv)) &&
2965
2965
config->num_pipes_active > 1)
2966
2966
last_enabled_level = 0;
2967
2967
···
3060
3060
* Always set WM_LP_SPRITE_EN when spr_val != 0, even if the
3061
3061
* level is disabled. Doing otherwise could cause underruns.
3062
3062
*/
3063
-
if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {
3063
+
if (DISPLAY_VER(dev_priv) < 7 && r->spr_val) {
3064
3064
drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
3065
3065
results->wm_lp_spr[wm_lp - 1] |= WM_LP_SPRITE_ENABLE;
3066
3066
}
+7
drivers/gpu/drm/i915/display/icl_dsi.c
+7
drivers/gpu/drm/i915/display/icl_dsi.c
···
1440
1440
static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
1441
1441
struct drm_display_mode *mode)
1442
1442
{
1443
+
struct drm_i915_private *i915 = to_i915(connector->dev);
1444
+
enum drm_mode_status status;
1445
+
1446
+
status = intel_cpu_transcoder_mode_valid(i915, mode);
1447
+
if (status != MODE_OK)
1448
+
return status;
1449
+
1443
1450
/* FIXME: DSC? */
1444
1451
return intel_dsi_mode_valid(connector, mode);
1445
1452
}
+3
-2
drivers/gpu/drm/i915/display/intel_bios.c
+3
-2
drivers/gpu/drm/i915/display/intel_bios.c
···
2201
2201
const u8 *ddc_pin_map;
2202
2202
int i, n_entries;
2203
2203
2204
+
if (IS_DGFX(i915))
2205
+
return vbt_pin;
2206
+
2204
2207
if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||
2205
2208
IS_ALDERLAKE_P(i915)) {
2206
2209
ddc_pin_map = adlp_ddc_pin_map;
···
2211
2208
} else if (IS_ALDERLAKE_S(i915)) {
2212
2209
ddc_pin_map = adls_ddc_pin_map;
2213
2210
n_entries = ARRAY_SIZE(adls_ddc_pin_map);
2214
-
} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
2215
-
return vbt_pin;
2216
2211
} else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) {
2217
2212
ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
2218
2213
n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
+4
-3
drivers/gpu/drm/i915/display/intel_bw.c
+4
-3
drivers/gpu/drm/i915/display/intel_bw.c
···
87
87
return ret;
88
88
89
89
dclk = val & 0xffff;
90
-
sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > 11 ? 500 : 0), 1000);
90
+
sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ? 500 : 0),
91
+
1000);
91
92
sp->t_rp = (val & 0xff0000) >> 16;
92
93
sp->t_rcd = (val & 0xff000000) >> 24;
93
94
···
481
480
if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12)
482
481
qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);
483
482
484
-
if (DISPLAY_VER(dev_priv) > 11 && num_channels > qi.max_numchannels)
483
+
if (DISPLAY_VER(dev_priv) >= 12 && num_channels > qi.max_numchannels)
485
484
drm_warn(&dev_priv->drm, "Number of channels exceeds max number of channels.");
486
485
if (qi.max_numchannels != 0)
487
486
num_channels = min_t(u8, num_channels, qi.max_numchannels);
···
898
897
unsigned int idx;
899
898
unsigned int max_data_rate;
900
899
901
-
if (DISPLAY_VER(i915) > 11)
900
+
if (DISPLAY_VER(i915) >= 12)
902
901
idx = tgl_max_bw_index(i915, num_active_planes, i);
903
902
else
904
903
idx = icl_max_bw_index(i915, num_active_planes, i);
+1
-1
drivers/gpu/drm/i915/display/intel_cdclk.c
+1
-1
drivers/gpu/drm/i915/display/intel_cdclk.c
···
2597
2597
* Since PPC = 2 with bigjoiner
2598
2598
* => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
2599
2599
*/
2600
-
int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
2600
+
int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
2601
2601
int min_cdclk_bj =
2602
2602
(to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
2603
2603
pixel_clock) / (2 * bigjoiner_interface_bits);
+5
drivers/gpu/drm/i915/display/intel_crt.c
+5
drivers/gpu/drm/i915/display/intel_crt.c
···
348
348
struct drm_device *dev = connector->dev;
349
349
struct drm_i915_private *dev_priv = to_i915(dev);
350
350
int max_dotclk = dev_priv->max_dotclk_freq;
351
+
enum drm_mode_status status;
351
352
int max_clock;
353
+
354
+
status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
355
+
if (status != MODE_OK)
356
+
return status;
352
357
353
358
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
354
359
return MODE_NO_DBLESCAN;
+9
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+9
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
···
262
262
drm_dbg_kms(&i915->drm, "fec: %s, enhanced framing: %s\n",
263
263
str_enabled_disabled(pipe_config->fec_enable),
264
264
str_enabled_disabled(pipe_config->enhanced_framing));
265
+
266
+
drm_dbg_kms(&i915->drm, "sdp split: %s\n",
267
+
str_enabled_disabled(pipe_config->sdp_split_enable));
268
+
269
+
drm_dbg_kms(&i915->drm, "psr: %s, psr2: %s, panel replay: %s, selective fetch: %s\n",
270
+
str_enabled_disabled(pipe_config->has_psr),
271
+
str_enabled_disabled(pipe_config->has_psr2),
272
+
str_enabled_disabled(pipe_config->has_panel_replay),
273
+
str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
265
274
}
266
275
267
276
drm_dbg_kms(&i915->drm, "framestart delay: %d, MSA timing delay: %d\n",
+37
-5
drivers/gpu/drm/i915/display/intel_cursor.c
+37
-5
drivers/gpu/drm/i915/display/intel_cursor.c
···
21
21
#include "intel_fb_pin.h"
22
22
#include "intel_frontbuffer.h"
23
23
#include "intel_psr.h"
24
+
#include "intel_psr_regs.h"
24
25
#include "skl_watermark.h"
26
+
27
+
#include "gem/i915_gem_object.h"
25
28
26
29
/* Cursor formats */
27
30
static const u32 intel_cursor_formats[] = {
···
36
33
struct drm_i915_private *dev_priv =
37
34
to_i915(plane_state->uapi.plane->dev);
38
35
const struct drm_framebuffer *fb = plane_state->hw.fb;
39
-
const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
36
+
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
40
37
u32 base;
41
38
42
39
if (DISPLAY_INFO(dev_priv)->cursor_needs_physical)
43
-
base = sg_dma_address(obj->mm.pages->sgl);
40
+
base = i915_gem_object_get_dma_address(obj, 0);
44
41
else
45
42
base = intel_plane_ggtt_offset(plane_state);
46
43
···
487
484
return 0;
488
485
}
489
486
487
+
static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane,
488
+
const struct intel_crtc_state *crtc_state)
489
+
{
490
+
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
491
+
enum pipe pipe = plane->pipe;
492
+
493
+
if (!crtc_state->enable_psr2_sel_fetch)
494
+
return;
495
+
496
+
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
497
+
}
498
+
499
+
static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
500
+
const struct intel_crtc_state *crtc_state,
501
+
const struct intel_plane_state *plane_state)
502
+
{
503
+
struct drm_i915_private *i915 = to_i915(plane->base.dev);
504
+
enum pipe pipe = plane->pipe;
505
+
506
+
if (!crtc_state->enable_psr2_sel_fetch)
507
+
return;
508
+
509
+
if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0)
510
+
intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id),
511
+
plane_state->ctl);
512
+
else
513
+
i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);
514
+
}
515
+
490
516
/* TODO: split into noarm+arm pair */
491
517
static void i9xx_cursor_update_arm(struct intel_plane *plane,
492
518
const struct intel_crtc_state *crtc_state,
···
563
531
skl_write_cursor_wm(plane, crtc_state);
564
532
565
533
if (plane_state)
566
-
intel_psr2_program_plane_sel_fetch_arm(plane, crtc_state,
567
-
plane_state);
534
+
i9xx_cursor_update_sel_fetch_arm(plane, crtc_state,
535
+
plane_state);
568
536
else
569
-
intel_psr2_disable_plane_sel_fetch_arm(plane, crtc_state);
537
+
i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);
570
538
571
539
if (plane->cursor.base != base ||
572
540
plane->cursor.size != fbc_ctl ||
+10
-1
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+10
-1
drivers/gpu/drm/i915/display/intel_cx0_phy.c
···
415
415
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
416
416
const struct intel_ddi_buf_trans *trans;
417
417
enum phy phy = intel_port_to_phy(i915, encoder->port);
418
-
u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
418
+
u8 owned_lane_mask;
419
419
intel_wakeref_t wakeref;
420
420
int n_entries, ln;
421
+
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
422
+
423
+
if (intel_tc_port_in_tbt_alt_mode(dig_port))
424
+
return;
425
+
426
+
owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
421
427
422
428
wakeref = intel_cx0_phy_transaction_begin(encoder);
423
429
···
3141
3135
3142
3136
encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
3143
3137
phy = intel_port_to_phy(i915, encoder->port);
3138
+
3139
+
if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
3140
+
return;
3144
3141
3145
3142
intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state);
3146
3143
+26
-8
drivers/gpu/drm/i915/display/intel_display.c
+26
-8
drivers/gpu/drm/i915/display/intel_display.c
···
2627
2627
crtc_vblank_start = 1;
2628
2628
}
2629
2629
2630
-
if (DISPLAY_VER(dev_priv) > 3)
2630
+
if (DISPLAY_VER(dev_priv) >= 4)
2631
2631
intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
2632
2632
vsyncshift);
2633
2633
···
3167
3167
break;
3168
3168
case 36:
3169
3169
/* Port output 12BPC defined for ADLP+ */
3170
-
if (DISPLAY_VER(dev_priv) > 12)
3170
+
if (DISPLAY_VER(dev_priv) >= 13)
3171
3171
val |= PIPE_MISC_BPC_12_ADLP;
3172
3172
break;
3173
3173
default:
···
3224
3224
* MIPI DSI HW readout.
3225
3225
*/
3226
3226
case PIPE_MISC_BPC_12_ADLP:
3227
-
if (DISPLAY_VER(dev_priv) > 12)
3227
+
if (DISPLAY_VER(dev_priv) >= 13)
3228
3228
return 36;
3229
3229
fallthrough;
3230
3230
default:
···
4923
4923
4924
4924
#define PIPE_CONF_CHECK_X(name) do { \
4925
4925
if (current_config->name != pipe_config->name) { \
4926
+
BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
4927
+
__stringify(name) " is bool"); \
4926
4928
pipe_config_mismatch(fastset, crtc, __stringify(name), \
4927
4929
"(expected 0x%08x, found 0x%08x)", \
4928
4930
current_config->name, \
···
4935
4933
4936
4934
#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
4937
4935
if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
4936
+
BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
4937
+
__stringify(name) " is bool"); \
4938
4938
pipe_config_mismatch(fastset, crtc, __stringify(name), \
4939
4939
"(expected 0x%08x, found 0x%08x)", \
4940
4940
current_config->name & (mask), \
···
4947
4943
4948
4944
#define PIPE_CONF_CHECK_I(name) do { \
4949
4945
if (current_config->name != pipe_config->name) { \
4946
+
BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
4947
+
__stringify(name) " is bool"); \
4950
4948
pipe_config_mismatch(fastset, crtc, __stringify(name), \
4951
4949
"(expected %i, found %i)", \
4952
4950
current_config->name, \
···
4959
4953
4960
4954
#define PIPE_CONF_CHECK_BOOL(name) do { \
4961
4955
if (current_config->name != pipe_config->name) { \
4956
+
BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
4957
+
__stringify(name) " is not bool"); \
4962
4958
pipe_config_mismatch(fastset, crtc, __stringify(name), \
4963
4959
"(expected %s, found %s)", \
4964
4960
str_yes_no(current_config->name), \
···
5099
5091
#define PIPE_CONF_QUIRK(quirk) \
5100
5092
((current_config->quirks | pipe_config->quirks) & (quirk))
5101
5093
5102
-
PIPE_CONF_CHECK_I(hw.enable);
5103
-
PIPE_CONF_CHECK_I(hw.active);
5094
+
PIPE_CONF_CHECK_BOOL(hw.enable);
5095
+
PIPE_CONF_CHECK_BOOL(hw.active);
5104
5096
5105
5097
PIPE_CONF_CHECK_I(cpu_transcoder);
5106
5098
PIPE_CONF_CHECK_I(mst_master_transcoder);
···
5309
5301
PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
5310
5302
PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
5311
5303
5312
-
PIPE_CONF_CHECK_I(dsc.compression_enable);
5313
-
PIPE_CONF_CHECK_I(dsc.dsc_split);
5304
+
PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
5305
+
PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
5314
5306
PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
5315
5307
5316
5308
PIPE_CONF_CHECK_BOOL(splitter.enable);
···
7742
7734
mode->vtotal > vtotal_max)
7743
7735
return MODE_V_ILLEGAL;
7744
7736
7737
+
return MODE_OK;
7738
+
}
7739
+
7740
+
enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv,
7741
+
const struct drm_display_mode *mode)
7742
+
{
7743
+
/*
7744
+
* Additional transcoder timing limits,
7745
+
* excluding BXT/GLK DSI transcoders.
7746
+
*/
7745
7747
if (DISPLAY_VER(dev_priv) >= 5) {
7746
7748
if (mode->hdisplay < 64 ||
7747
7749
mode->htotal - mode->hdisplay < 32)
···
7771
7753
* Cantiga+ cannot handle modes with a hsync front porch of 0.
7772
7754
* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7773
7755
*/
7774
-
if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7756
+
if ((DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) &&
7775
7757
mode->hsync_start == mode->hdisplay)
7776
7758
return MODE_H_ILLEGAL;
7777
7759
+3
drivers/gpu/drm/i915/display/intel_display.h
+3
drivers/gpu/drm/i915/display/intel_display.h
···
402
402
intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
403
403
const struct drm_display_mode *mode,
404
404
bool bigjoiner);
405
+
enum drm_mode_status
406
+
intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
407
+
const struct drm_display_mode *mode);
405
408
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
406
409
bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
407
410
bool is_trans_port_sync_master(const struct intel_crtc_state *state);
+81
-84
drivers/gpu/drm/i915/display/intel_display_debugfs.c
+81
-84
drivers/gpu/drm/i915/display/intel_display_debugfs.c
···
1095
1095
1096
1096
for (i = 0; i < ARRAY_SIZE(intel_display_debugfs_files); i++) {
1097
1097
debugfs_create_file(intel_display_debugfs_files[i].name,
1098
-
S_IRUGO | S_IWUSR,
1098
+
0644,
1099
1099
minor->debugfs_root,
1100
1100
to_i915(minor->dev),
1101
1101
intel_display_debugfs_files[i].fops);
···
1116
1116
1117
1117
static int i915_panel_show(struct seq_file *m, void *data)
1118
1118
{
1119
-
struct drm_connector *connector = m->private;
1120
-
struct intel_dp *intel_dp =
1121
-
intel_attached_dp(to_intel_connector(connector));
1119
+
struct intel_connector *connector = m->private;
1120
+
struct intel_dp *intel_dp = intel_attached_dp(connector);
1122
1121
1123
-
if (connector->status != connector_status_connected)
1122
+
if (connector->base.status != connector_status_connected)
1124
1123
return -ENODEV;
1125
1124
1126
1125
seq_printf(m, "Panel power up delay: %d\n",
···
1137
1138
1138
1139
static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
1139
1140
{
1140
-
struct drm_connector *connector = m->private;
1141
-
struct drm_i915_private *i915 = to_i915(connector->dev);
1142
-
struct intel_connector *intel_connector = to_intel_connector(connector);
1141
+
struct intel_connector *connector = m->private;
1142
+
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1143
1143
int ret;
1144
1144
1145
1145
ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
1146
1146
if (ret)
1147
1147
return ret;
1148
1148
1149
-
if (!connector->encoder || connector->status != connector_status_connected) {
1149
+
if (!connector->base.encoder ||
1150
+
connector->base.status != connector_status_connected) {
1150
1151
ret = -ENODEV;
1151
1152
goto out;
1152
1153
}
1153
1154
1154
-
seq_printf(m, "%s:%d HDCP version: ", connector->name,
1155
-
connector->base.id);
1156
-
intel_hdcp_info(m, intel_connector);
1155
+
seq_printf(m, "%s:%d HDCP version: ", connector->base.name,
1156
+
connector->base.base.id);
1157
+
intel_hdcp_info(m, connector);
1157
1158
1158
1159
out:
1159
1160
drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
···
1164
1165
1165
1166
static int i915_lpsp_capability_show(struct seq_file *m, void *data)
1166
1167
{
1167
-
struct drm_connector *connector = m->private;
1168
-
struct drm_i915_private *i915 = to_i915(connector->dev);
1169
-
struct intel_encoder *encoder;
1168
+
struct intel_connector *connector = m->private;
1169
+
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1170
+
struct intel_encoder *encoder = intel_attached_encoder(connector);
1171
+
int connector_type = connector->base.connector_type;
1170
1172
bool lpsp_capable = false;
1171
1173
1172
-
encoder = intel_attached_encoder(to_intel_connector(connector));
1173
1174
if (!encoder)
1174
1175
return -ENODEV;
1175
1176
1176
-
if (connector->status != connector_status_connected)
1177
+
if (connector->base.status != connector_status_connected)
1177
1178
return -ENODEV;
1178
1179
1179
1180
if (DISPLAY_VER(i915) >= 13)
···
1186
1187
*/
1187
1188
lpsp_capable = encoder->port <= PORT_B;
1188
1189
else if (DISPLAY_VER(i915) == 11)
1189
-
lpsp_capable = (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
1190
-
connector->connector_type == DRM_MODE_CONNECTOR_eDP);
1190
+
lpsp_capable = (connector_type == DRM_MODE_CONNECTOR_DSI ||
1191
+
connector_type == DRM_MODE_CONNECTOR_eDP);
1191
1192
else if (IS_DISPLAY_VER(i915, 9, 10))
1192
1193
lpsp_capable = (encoder->port == PORT_A &&
1193
-
(connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
1194
-
connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
1195
-
connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort));
1194
+
(connector_type == DRM_MODE_CONNECTOR_DSI ||
1195
+
connector_type == DRM_MODE_CONNECTOR_eDP ||
1196
+
connector_type == DRM_MODE_CONNECTOR_DisplayPort));
1196
1197
else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
1197
-
lpsp_capable = connector->connector_type == DRM_MODE_CONNECTOR_eDP;
1198
+
lpsp_capable = connector_type == DRM_MODE_CONNECTOR_eDP;
1198
1199
1199
1200
seq_printf(m, "LPSP: %s\n", lpsp_capable ? "capable" : "incapable");
1200
1201
···
1204
1205
1205
1206
static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
1206
1207
{
1207
-
struct intel_connector *connector = to_intel_connector(m->private);
1208
+
struct intel_connector *connector = m->private;
1208
1209
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1209
1210
struct drm_crtc *crtc;
1210
1211
struct intel_dp *intel_dp;
···
1274
1275
const char __user *ubuf,
1275
1276
size_t len, loff_t *offp)
1276
1277
{
1278
+
struct seq_file *m = file->private_data;
1279
+
struct intel_connector *connector = m->private;
1280
+
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1281
+
struct intel_encoder *encoder = intel_attached_encoder(connector);
1282
+
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1277
1283
bool dsc_enable = false;
1278
1284
int ret;
1279
-
struct drm_connector *connector =
1280
-
((struct seq_file *)file->private_data)->private;
1281
-
struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
1282
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1283
-
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1284
1285
1285
1286
if (len == 0)
1286
1287
return 0;
···
1318
1319
1319
1320
static int i915_dsc_bpc_show(struct seq_file *m, void *data)
1320
1321
{
1321
-
struct drm_connector *connector = m->private;
1322
-
struct drm_device *dev = connector->dev;
1322
+
struct intel_connector *connector = m->private;
1323
+
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1324
+
struct intel_encoder *encoder = intel_attached_encoder(connector);
1323
1325
struct drm_crtc *crtc;
1324
1326
struct intel_crtc_state *crtc_state;
1325
-
struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
1326
1327
int ret;
1327
1328
1328
1329
if (!encoder)
1329
1330
return -ENODEV;
1330
1331
1331
-
ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
1332
+
ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
1332
1333
if (ret)
1333
1334
return ret;
1334
1335
1335
-
crtc = connector->state->crtc;
1336
-
if (connector->status != connector_status_connected || !crtc) {
1336
+
crtc = connector->base.state->crtc;
1337
+
if (connector->base.status != connector_status_connected || !crtc) {
1337
1338
ret = -ENODEV;
1338
1339
goto out;
1339
1340
}
···
1341
1342
crtc_state = to_intel_crtc_state(crtc->state);
1342
1343
seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component);
1343
1344
1344
-
out: drm_modeset_unlock(&dev->mode_config.connection_mutex);
1345
+
out: drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
1345
1346
1346
1347
return ret;
1347
1348
}
···
1350
1351
const char __user *ubuf,
1351
1352
size_t len, loff_t *offp)
1352
1353
{
1353
-
struct drm_connector *connector =
1354
-
((struct seq_file *)file->private_data)->private;
1355
-
struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
1354
+
struct seq_file *m = file->private_data;
1355
+
struct intel_connector *connector = m->private;
1356
+
struct intel_encoder *encoder = intel_attached_encoder(connector);
1356
1357
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1357
1358
int dsc_bpc = 0;
1358
1359
int ret;
···
1384
1385
1385
1386
static int i915_dsc_output_format_show(struct seq_file *m, void *data)
1386
1387
{
1387
-
struct drm_connector *connector = m->private;
1388
-
struct drm_device *dev = connector->dev;
1388
+
struct intel_connector *connector = m->private;
1389
+
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1390
+
struct intel_encoder *encoder = intel_attached_encoder(connector);
1389
1391
struct drm_crtc *crtc;
1390
1392
struct intel_crtc_state *crtc_state;
1391
-
struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
1392
1393
int ret;
1393
1394
1394
1395
if (!encoder)
1395
1396
return -ENODEV;
1396
1397
1397
-
ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
1398
+
ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
1398
1399
if (ret)
1399
1400
return ret;
1400
1401
1401
-
crtc = connector->state->crtc;
1402
-
if (connector->status != connector_status_connected || !crtc) {
1402
+
crtc = connector->base.state->crtc;
1403
+
if (connector->base.status != connector_status_connected || !crtc) {
1403
1404
ret = -ENODEV;
1404
1405
goto out;
1405
1406
}
···
1408
1409
seq_printf(m, "DSC_Output_Format: %s\n",
1409
1410
intel_output_format_name(crtc_state->output_format));
1410
1411
1411
-
out: drm_modeset_unlock(&dev->mode_config.connection_mutex);
1412
+
out: drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
1412
1413
1413
1414
return ret;
1414
1415
}
···
1417
1418
const char __user *ubuf,
1418
1419
size_t len, loff_t *offp)
1419
1420
{
1420
-
struct drm_connector *connector =
1421
-
((struct seq_file *)file->private_data)->private;
1422
-
struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
1421
+
struct seq_file *m = file->private_data;
1422
+
struct intel_connector *connector = m->private;
1423
+
struct intel_encoder *encoder = intel_attached_encoder(connector);
1423
1424
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1424
1425
int dsc_output_format = 0;
1425
1426
int ret;
···
1451
1452
1452
1453
static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
1453
1454
{
1454
-
struct drm_connector *connector = m->private;
1455
-
struct drm_device *dev = connector->dev;
1455
+
struct intel_connector *connector = m->private;
1456
+
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1457
+
struct intel_encoder *encoder = intel_attached_encoder(connector);
1456
1458
struct drm_crtc *crtc;
1457
1459
struct intel_dp *intel_dp;
1458
-
struct intel_connector *intel_connector = to_intel_connector(connector);
1459
-
struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
1460
1460
int ret;
1461
1461
1462
1462
if (!encoder)
1463
1463
return -ENODEV;
1464
1464
1465
-
ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
1465
+
ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
1466
1466
if (ret)
1467
1467
return ret;
1468
1468
1469
-
crtc = connector->state->crtc;
1470
-
if (connector->status != connector_status_connected || !crtc) {
1469
+
crtc = connector->base.state->crtc;
1470
+
if (connector->base.status != connector_status_connected || !crtc) {
1471
1471
ret = -ENODEV;
1472
1472
goto out;
1473
1473
}
1474
1474
1475
-
intel_dp = intel_attached_dp(intel_connector);
1475
+
intel_dp = intel_attached_dp(connector);
1476
1476
seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
1477
1477
str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
1478
1478
1479
1479
out:
1480
-
drm_modeset_unlock(&dev->mode_config.connection_mutex);
1480
+
drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
1481
1481
1482
1482
return ret;
1483
1483
}
···
1485
1487
const char __user *ubuf,
1486
1488
size_t len, loff_t *offp)
1487
1489
{
1488
-
struct drm_connector *connector =
1489
-
((struct seq_file *)file->private_data)->private;
1490
-
struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
1491
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1490
+
struct seq_file *m = file->private_data;
1491
+
struct intel_connector *connector = m->private;
1492
+
struct intel_encoder *encoder = intel_attached_encoder(connector);
1493
+
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1492
1494
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1493
1495
bool dsc_fractional_bpp_enable = false;
1494
1496
int ret;
···
1563
1565
1564
1566
/**
1565
1567
* intel_connector_debugfs_add - add i915 specific connector debugfs files
1566
-
* @intel_connector: pointer to a registered drm_connector
1568
+
* @connector: pointer to a registered intel_connector
1567
1569
*
1568
1570
* Cleanup will be done by drm_connector_unregister() through a call to
1569
1571
* drm_debugfs_connector_remove().
1570
1572
*/
1571
-
void intel_connector_debugfs_add(struct intel_connector *intel_connector)
1573
+
void intel_connector_debugfs_add(struct intel_connector *connector)
1572
1574
{
1573
-
struct drm_connector *connector = &intel_connector->base;
1574
-
struct dentry *root = connector->debugfs_entry;
1575
-
struct drm_i915_private *dev_priv = to_i915(connector->dev);
1575
+
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1576
+
struct dentry *root = connector->base.debugfs_entry;
1577
+
int connector_type = connector->base.connector_type;
1576
1578
1577
1579
/* The connector must have been registered beforehands. */
1578
1580
if (!root)
1579
1581
return;
1580
1582
1581
-
intel_drrs_connector_debugfs_add(intel_connector);
1582
-
intel_psr_connector_debugfs_add(intel_connector);
1583
+
intel_drrs_connector_debugfs_add(connector);
1584
+
intel_psr_connector_debugfs_add(connector);
1583
1585
1584
-
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1585
-
debugfs_create_file("i915_panel_timings", S_IRUGO, root,
1586
+
if (connector_type == DRM_MODE_CONNECTOR_eDP)
1587
+
debugfs_create_file("i915_panel_timings", 0444, root,
1586
1588
connector, &i915_panel_fops);
1587
1589
1588
-
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1589
-
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
1590
-
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
1591
-
debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root,
1590
+
if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1591
+
connector_type == DRM_MODE_CONNECTOR_HDMIA ||
1592
+
connector_type == DRM_MODE_CONNECTOR_HDMIB) {
1593
+
debugfs_create_file("i915_hdcp_sink_capability", 0444, root,
1592
1594
connector, &i915_hdcp_sink_capability_fops);
1593
1595
}
1594
1596
1595
-
if (DISPLAY_VER(dev_priv) >= 11 &&
1596
-
((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
1597
-
!to_intel_connector(connector)->mst_port) ||
1598
-
connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1597
+
if (DISPLAY_VER(i915) >= 11 &&
1598
+
((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !connector->mst_port) ||
1599
+
connector_type == DRM_MODE_CONNECTOR_eDP)) {
1599
1600
debugfs_create_file("i915_dsc_fec_support", 0644, root,
1600
1601
connector, &i915_dsc_fec_support_fops);
1601
1602
···
1608
1611
connector, &i915_dsc_fractional_bpp_fops);
1609
1612
}
1610
1613
1611
-
if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
1612
-
connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
1613
-
connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1614
-
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
1615
-
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
1614
+
if (connector_type == DRM_MODE_CONNECTOR_DSI ||
1615
+
connector_type == DRM_MODE_CONNECTOR_eDP ||
1616
+
connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1617
+
connector_type == DRM_MODE_CONNECTOR_HDMIA ||
1618
+
connector_type == DRM_MODE_CONNECTOR_HDMIB)
1616
1619
debugfs_create_file("i915_lpsp_capability", 0444, root,
1617
1620
connector, &i915_lpsp_capability_fops);
1618
1621
}
+1
-1
drivers/gpu/drm/i915/display/intel_display_device.h
+1
-1
drivers/gpu/drm/i915/display/intel_display_device.h
···
49
49
#define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
50
50
#define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
51
51
#define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
52
-
#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
52
+
#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) >= 3)
53
53
#define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
54
54
#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915))
55
55
#define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
+2
-2
drivers/gpu/drm/i915/display/intel_display_irq.c
+2
-2
drivers/gpu/drm/i915/display/intel_display_irq.c
···
896
896
}
897
897
898
898
if (!found)
899
-
drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
899
+
drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir);
900
900
}
901
901
902
902
static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
···
1653
1653
else if (HAS_PCH_SPLIT(dev_priv))
1654
1654
ibx_irq_postinstall(dev_priv);
1655
1655
1656
-
if (DISPLAY_VER(dev_priv) <= 10)
1656
+
if (DISPLAY_VER(dev_priv) < 11)
1657
1657
de_misc_masked |= GEN8_DE_MISC_GSE;
1658
1658
1659
1659
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
+3
-3
drivers/gpu/drm/i915/display/intel_display_power.c
+3
-3
drivers/gpu/drm/i915/display/intel_display_power.c
···
1697
1697
if (resume)
1698
1698
intel_dmc_load_program(dev_priv);
1699
1699
1700
-
/* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */
1701
-
if (DISPLAY_VER(dev_priv) >= 12)
1700
+
/* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */
1701
+
if (IS_DISPLAY_IP_RANGE(dev_priv, IP_VER(12, 0), IP_VER(13, 0)))
1702
1702
intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0,
1703
1703
DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
1704
1704
DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR);
1705
1705
1706
1706
/* Wa_14011503030:xelpd */
1707
-
if (DISPLAY_VER(dev_priv) >= 13)
1707
+
if (DISPLAY_VER(dev_priv) == 13)
1708
1708
intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
1709
1709
}
1710
1710
+5
-8
drivers/gpu/drm/i915/display/intel_dp.c
+5
-8
drivers/gpu/drm/i915/display/intel_dp.c
···
1227
1227
enum drm_mode_status status;
1228
1228
bool dsc = false, bigjoiner = false;
1229
1229
1230
+
status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1231
+
if (status != MODE_OK)
1232
+
return status;
1233
+
1230
1234
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1231
1235
return MODE_H_ILLEGAL;
1232
1236
···
1890
1886
* Max Compressed bpp for Gen 13+ is 27bpp.
1891
1887
* For earlier platform is 23bpp. (Bspec:49259).
1892
1888
*/
1893
-
if (DISPLAY_VER(i915) <= 12)
1889
+
if (DISPLAY_VER(i915) < 13)
1894
1890
return 23;
1895
1891
else
1896
1892
return 27;
···
2848
2844
struct intel_crtc_state *pipe_config,
2849
2845
struct drm_connector_state *conn_state)
2850
2846
{
2851
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2852
-
struct drm_connector *connector = conn_state->connector;
2853
-
2854
2847
pipe_config->has_audio =
2855
2848
intel_dp_has_audio(encoder, pipe_config, conn_state) &&
2856
2849
intel_audio_compute_config(encoder, pipe_config, conn_state);
2857
2850
2858
2851
pipe_config->sdp_split_enable = pipe_config->has_audio &&
2859
2852
intel_dp_is_uhbr(pipe_config);
2860
-
2861
-
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDP split enable: %s\n",
2862
-
connector->base.id, connector->name,
2863
-
str_yes_no(pipe_config->sdp_split_enable));
2864
2853
}
2865
2854
2866
2855
int
+17
-5
drivers/gpu/drm/i915/display/intel_dp_mst.c
+17
-5
drivers/gpu/drm/i915/display/intel_dp_mst.c
···
54
54
struct intel_crtc_state *crtc_state,
55
55
bool dsc)
56
56
{
57
-
if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) <= 13 && dsc) {
57
+
if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
58
58
int output_bpp = bpp;
59
59
/* DisplayPort 2 128b/132b, bits per lane is always 32 */
60
60
int symbol_clock = crtc_state->port_clock / 32;
···
1282
1282
return 0;
1283
1283
}
1284
1284
1285
+
*status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1286
+
if (*status != MODE_OK)
1287
+
return 0;
1288
+
1285
1289
if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
1286
1290
*status = MODE_NO_DBLESCAN;
1287
1291
return 0;
···
1332
1328
if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1333
1329
bigjoiner = true;
1334
1330
max_dotclk *= 2;
1331
+
1332
+
/* TODO: add support for bigjoiner */
1333
+
*status = MODE_CLOCK_HIGH;
1334
+
return 0;
1335
1335
}
1336
1336
1337
1337
if (DISPLAY_VER(dev_priv) >= 10 &&
···
1370
1362
* Big joiner configuration needs DSC for TGL which is not true for
1371
1363
* XE_LPD where uncompressed joiner is supported.
1372
1364
*/
1373
-
if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1374
-
return MODE_CLOCK_HIGH;
1365
+
if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) {
1366
+
*status = MODE_CLOCK_HIGH;
1367
+
return 0;
1368
+
}
1375
1369
1376
-
if (mode_rate > max_rate && !dsc)
1377
-
return MODE_CLOCK_HIGH;
1370
+
if (mode_rate > max_rate && !dsc) {
1371
+
*status = MODE_CLOCK_HIGH;
1372
+
return 0;
1373
+
}
1378
1374
1379
1375
*status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
1380
1376
return 0;
+1
-1
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+1
-1
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
···
4537
4537
"pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
4538
4538
pipe_name(crtc->pipe), pll->active_mask);
4539
4539
I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask,
4540
-
"pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n",
4540
+
"pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
4541
4541
pipe_name(crtc->pipe), pll->state.pipe_mask);
4542
4542
}
4543
4543
}
+1
-1
drivers/gpu/drm/i915/display/intel_dsb.c
+1
-1
drivers/gpu/drm/i915/display/intel_dsb.c
+2
-15
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+2
-15
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
···
922
922
gpiod_add_lookup_table(gpiod_lookup_table);
923
923
924
924
if (want_panel_gpio) {
925
-
intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags);
925
+
intel_dsi->gpio_panel = devm_gpiod_get(dev->dev, "panel", flags);
926
926
if (IS_ERR(intel_dsi->gpio_panel)) {
927
927
drm_err(&dev_priv->drm,
928
928
"Failed to own gpio for panel control\n");
···
932
932
933
933
if (want_backlight_gpio) {
934
934
intel_dsi->gpio_backlight =
935
-
gpiod_get(dev->dev, "backlight", flags);
935
+
devm_gpiod_get(dev->dev, "backlight", flags);
936
936
if (IS_ERR(intel_dsi->gpio_backlight)) {
937
937
drm_err(&dev_priv->drm,
938
938
"Failed to own gpio for backlight control\n");
···
942
942
943
943
if (gpiod_lookup_table)
944
944
gpiod_remove_lookup_table(gpiod_lookup_table);
945
-
}
946
-
947
-
void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
948
-
{
949
-
if (intel_dsi->gpio_panel) {
950
-
gpiod_put(intel_dsi->gpio_panel);
951
-
intel_dsi->gpio_panel = NULL;
952
-
}
953
-
954
-
if (intel_dsi->gpio_backlight) {
955
-
gpiod_put(intel_dsi->gpio_backlight);
956
-
intel_dsi->gpio_backlight = NULL;
957
-
}
958
945
}
-1
drivers/gpu/drm/i915/display/intel_dsi_vbt.h
-1
drivers/gpu/drm/i915/display/intel_dsi_vbt.h
···
13
13
14
14
bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
15
15
void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on);
16
-
void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi);
17
16
void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
18
17
enum mipi_seq seq_id);
19
18
void intel_dsi_log_params(struct intel_dsi *intel_dsi);
+6
drivers/gpu/drm/i915/display/intel_dvo.c
+6
drivers/gpu/drm/i915/display/intel_dvo.c
···
217
217
struct drm_display_mode *mode)
218
218
{
219
219
struct intel_connector *connector = to_intel_connector(_connector);
220
+
struct drm_i915_private *i915 = to_i915(connector->base.dev);
220
221
struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
221
222
const struct drm_display_mode *fixed_mode =
222
223
intel_panel_fixed_mode(connector, mode);
223
224
int max_dotclk = to_i915(connector->base.dev)->max_dotclk_freq;
224
225
int target_clock = mode->clock;
226
+
enum drm_mode_status status;
227
+
228
+
status = intel_cpu_transcoder_mode_valid(i915, mode);
229
+
if (status != MODE_OK)
230
+
return status;
225
231
226
232
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
227
233
return MODE_NO_DBLESCAN;
+61
-100
drivers/gpu/drm/i915/display/intel_fb.c
+61
-100
drivers/gpu/drm/i915/display/intel_fb.c
···
4
4
*/
5
5
6
6
#include <drm/drm_blend.h>
7
-
#include <drm/drm_framebuffer.h>
8
7
#include <drm/drm_modeset_helper.h>
9
8
10
9
#include <linux/dma-fence.h>
···
14
15
#include "intel_display_types.h"
15
16
#include "intel_dpt.h"
16
17
#include "intel_fb.h"
18
+
#include "intel_fb_bo.h"
17
19
#include "intel_frontbuffer.h"
18
20
19
21
#define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
···
299
299
}
300
300
301
301
return NULL;
302
+
}
303
+
304
+
unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
305
+
{
306
+
const struct intel_modifier_desc *md;
307
+
u8 tiling_caps;
308
+
309
+
md = lookup_modifier_or_null(fb_modifier);
310
+
if (!md)
311
+
return I915_TILING_NONE;
312
+
313
+
tiling_caps = lookup_modifier_or_null(fb_modifier)->plane_caps &
314
+
INTEL_PLANE_CAP_TILING_MASK;
315
+
316
+
switch (tiling_caps) {
317
+
case INTEL_PLANE_CAP_TILING_Y:
318
+
return I915_TILING_Y;
319
+
case INTEL_PLANE_CAP_TILING_X:
320
+
return I915_TILING_X;
321
+
case INTEL_PLANE_CAP_TILING_4:
322
+
case INTEL_PLANE_CAP_TILING_Yf:
323
+
case INTEL_PLANE_CAP_TILING_NONE:
324
+
return I915_TILING_NONE;
325
+
default:
326
+
MISSING_CASE(tiling_caps);
327
+
return I915_TILING_NONE;
328
+
}
302
329
}
303
330
304
331
/**
···
762
735
unsigned int tile_height = intel_tile_height(fb, color_plane);
763
736
764
737
return ALIGN(height, tile_height);
765
-
}
766
-
767
-
static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
768
-
{
769
-
u8 tiling_caps = lookup_modifier(fb_modifier)->plane_caps &
770
-
INTEL_PLANE_CAP_TILING_MASK;
771
-
772
-
switch (tiling_caps) {
773
-
case INTEL_PLANE_CAP_TILING_Y:
774
-
return I915_TILING_Y;
775
-
case INTEL_PLANE_CAP_TILING_X:
776
-
return I915_TILING_X;
777
-
case INTEL_PLANE_CAP_TILING_4:
778
-
case INTEL_PLANE_CAP_TILING_Yf:
779
-
case INTEL_PLANE_CAP_TILING_NONE:
780
-
return I915_TILING_NONE;
781
-
default:
782
-
MISSING_CASE(tiling_caps);
783
-
return I915_TILING_NONE;
784
-
}
785
738
}
786
739
787
740
bool intel_fb_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)
···
1381
1374
struct drm_i915_private *i915 = to_i915(fb->base.dev);
1382
1375
unsigned int stride_tiles;
1383
1376
1384
-
if (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
1377
+
if ((IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) &&
1378
+
src_stride_tiles < dst_stride_tiles)
1385
1379
stride_tiles = src_stride_tiles;
1386
1380
else
1387
1381
stride_tiles = dst_stride_tiles;
···
1665
1657
max_size = max(max_size, offset + size);
1666
1658
}
1667
1659
1668
-
if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
1660
+
if (mul_u32_u32(max_size, tile_size) > intel_bo_to_drm_bo(obj)->size) {
1669
1661
drm_dbg_kms(&i915->drm,
1670
1662
"fb too big for bo (need %llu bytes, have %zu bytes)\n",
1671
-
mul_u32_u32(max_size, tile_size), obj->base.size);
1663
+
mul_u32_u32(max_size, tile_size), intel_bo_to_drm_bo(obj)->size);
1672
1664
return -EINVAL;
1673
1665
}
1674
1666
···
1889
1881
1890
1882
intel_frontbuffer_put(intel_fb->frontbuffer);
1891
1883
1884
+
intel_fb_bo_framebuffer_fini(intel_fb_obj(fb));
1885
+
1892
1886
kfree(intel_fb);
1893
1887
}
1894
1888
···
1899
1889
unsigned int *handle)
1900
1890
{
1901
1891
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1902
-
struct drm_i915_private *i915 = to_i915(obj->base.dev);
1892
+
struct drm_i915_private *i915 = to_i915(intel_bo_to_drm_bo(obj)->dev);
1903
1893
1904
1894
if (i915_gem_object_is_userptr(obj)) {
1905
1895
drm_dbg(&i915->drm,
···
1907
1897
return -EINVAL;
1908
1898
}
1909
1899
1910
-
return drm_gem_handle_create(file, &obj->base, handle);
1900
+
return drm_gem_handle_create(file, intel_bo_to_drm_bo(obj), handle);
1911
1901
}
1912
1902
1913
1903
struct frontbuffer_fence_cb {
···
1985
1975
struct drm_i915_gem_object *obj,
1986
1976
struct drm_mode_fb_cmd2 *mode_cmd)
1987
1977
{
1988
-
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
1978
+
struct drm_i915_private *dev_priv = to_i915(intel_bo_to_drm_bo(obj)->dev);
1989
1979
struct drm_framebuffer *fb = &intel_fb->base;
1990
1980
u32 max_stride;
1991
-
unsigned int tiling, stride;
1992
1981
int ret = -EINVAL;
1993
1982
int i;
1994
1983
1984
+
ret = intel_fb_bo_framebuffer_init(intel_fb, obj, mode_cmd);
1985
+
if (ret)
1986
+
return ret;
1987
+
1995
1988
intel_fb->frontbuffer = intel_frontbuffer_get(obj);
1996
-
if (!intel_fb->frontbuffer)
1997
-
return -ENOMEM;
1998
-
1999
-
i915_gem_object_lock(obj, NULL);
2000
-
tiling = i915_gem_object_get_tiling(obj);
2001
-
stride = i915_gem_object_get_stride(obj);
2002
-
i915_gem_object_unlock(obj);
2003
-
2004
-
if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
2005
-
/*
2006
-
* If there's a fence, enforce that
2007
-
* the fb modifier and tiling mode match.
2008
-
*/
2009
-
if (tiling != I915_TILING_NONE &&
2010
-
tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
2011
-
drm_dbg_kms(&dev_priv->drm,
2012
-
"tiling_mode doesn't match fb modifier\n");
2013
-
goto err;
2014
-
}
2015
-
} else {
2016
-
if (tiling == I915_TILING_X) {
2017
-
mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
2018
-
} else if (tiling == I915_TILING_Y) {
2019
-
drm_dbg_kms(&dev_priv->drm,
2020
-
"No Y tiling for legacy addfb\n");
2021
-
goto err;
2022
-
}
1989
+
if (!intel_fb->frontbuffer) {
1990
+
ret = -ENOMEM;
1991
+
goto err;
2023
1992
}
2024
1993
1994
+
ret = -EINVAL;
2025
1995
if (!drm_any_plane_has_format(&dev_priv->drm,
2026
1996
mode_cmd->pixel_format,
2027
1997
mode_cmd->modifier[0])) {
2028
1998
drm_dbg_kms(&dev_priv->drm,
2029
1999
"unsupported pixel format %p4cc / modifier 0x%llx\n",
2030
2000
&mode_cmd->pixel_format, mode_cmd->modifier[0]);
2031
-
goto err;
2032
-
}
2033
-
2034
-
/*
2035
-
* gen2/3 display engine uses the fence if present,
2036
-
* so the tiling mode must match the fb modifier exactly.
2037
-
*/
2038
-
if (DISPLAY_VER(dev_priv) < 4 &&
2039
-
tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
2040
-
drm_dbg_kms(&dev_priv->drm,
2041
-
"tiling_mode must match fb modifier exactly on gen2/3\n");
2042
-
goto err;
2001
+
goto err_frontbuffer_put;
2043
2002
}
2044
2003
2045
2004
max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
···
2019
2040
mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
2020
2041
"tiled" : "linear",
2021
2042
mode_cmd->pitches[0], max_stride);
2022
-
goto err;
2023
-
}
2024
-
2025
-
/*
2026
-
* If there's a fence, enforce that
2027
-
* the fb pitch and fence stride match.
2028
-
*/
2029
-
if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
2030
-
drm_dbg_kms(&dev_priv->drm,
2031
-
"pitch (%d) must match tiling stride (%d)\n",
2032
-
mode_cmd->pitches[0], stride);
2033
-
goto err;
2043
+
goto err_frontbuffer_put;
2034
2044
}
2035
2045
2036
2046
/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
···
2027
2059
drm_dbg_kms(&dev_priv->drm,
2028
2060
"plane 0 offset (0x%08x) must be 0\n",
2029
2061
mode_cmd->offsets[0]);
2030
-
goto err;
2062
+
goto err_frontbuffer_put;
2031
2063
}
2032
2064
2033
2065
drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
···
2038
2070
if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
2039
2071
drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
2040
2072
i);
2041
-
goto err;
2073
+
goto err_frontbuffer_put;
2042
2074
}
2043
2075
2044
2076
stride_alignment = intel_fb_stride_alignment(fb, i);
···
2046
2078
drm_dbg_kms(&dev_priv->drm,
2047
2079
"plane %d pitch (%d) must be at least %u byte aligned\n",
2048
2080
i, fb->pitches[i], stride_alignment);
2049
-
goto err;
2081
+
goto err_frontbuffer_put;
2050
2082
}
2051
2083
2052
2084
if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) {
···
2057
2089
"ccs aux plane %d pitch (%d) must be %d\n",
2058
2090
i,
2059
2091
fb->pitches[i], ccs_aux_stride);
2060
-
goto err;
2092
+
goto err_frontbuffer_put;
2061
2093
}
2062
2094
}
2063
2095
···
2066
2098
2067
2099
ret = intel_fill_fb_info(dev_priv, intel_fb);
2068
2100
if (ret)
2069
-
goto err;
2101
+
goto err_frontbuffer_put;
2070
2102
2071
2103
if (intel_fb_uses_dpt(fb)) {
2072
2104
struct i915_address_space *vm;
···
2075
2107
if (IS_ERR(vm)) {
2076
2108
drm_dbg_kms(&dev_priv->drm, "failed to create DPT\n");
2077
2109
ret = PTR_ERR(vm);
2078
-
goto err;
2110
+
goto err_frontbuffer_put;
2079
2111
}
2080
2112
2081
2113
intel_fb->dpt_vm = vm;
···
2092
2124
err_free_dpt:
2093
2125
if (intel_fb_uses_dpt(fb))
2094
2126
intel_dpt_destroy(intel_fb->dpt_vm);
2095
-
err:
2127
+
err_frontbuffer_put:
2096
2128
intel_frontbuffer_put(intel_fb->frontbuffer);
2129
+
err:
2130
+
intel_fb_bo_framebuffer_fini(obj);
2097
2131
return ret;
2098
2132
}
2099
2133
···
2107
2137
struct drm_framebuffer *fb;
2108
2138
struct drm_i915_gem_object *obj;
2109
2139
struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
2110
-
struct drm_i915_private *i915;
2140
+
struct drm_i915_private *i915 = to_i915(dev);
2111
2141
2112
-
obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
2113
-
if (!obj)
2114
-
return ERR_PTR(-ENOENT);
2115
-
2116
-
/* object is backed with LMEM for discrete */
2117
-
i915 = to_i915(obj->base.dev);
2118
-
if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM_0)) {
2119
-
/* object is "remote", not in local memory */
2120
-
i915_gem_object_put(obj);
2121
-
drm_dbg_kms(&i915->drm, "framebuffer must reside in local memory\n");
2122
-
return ERR_PTR(-EREMOTE);
2123
-
}
2142
+
obj = intel_fb_bo_lookup_valid_bo(i915, filp, &mode_cmd);
2143
+
if (IS_ERR(obj))
2144
+
return ERR_CAST(obj);
2124
2145
2125
2146
fb = intel_framebuffer_create(obj, &mode_cmd);
2126
-
i915_gem_object_put(obj);
2147
+
drm_gem_object_put(intel_bo_to_drm_bo(obj));
2127
2148
2128
2149
return fb;
2129
2150
}
+2
drivers/gpu/drm/i915/display/intel_fb.h
+2
drivers/gpu/drm/i915/display/intel_fb.h
+97
drivers/gpu/drm/i915/display/intel_fb_bo.c
+97
drivers/gpu/drm/i915/display/intel_fb_bo.c
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/*
3
+
* Copyright © 2021 Intel Corporation
4
+
*/
5
+
6
+
#include <drm/drm_framebuffer.h>
7
+
8
+
#include "gem/i915_gem_object.h"
9
+
10
+
#include "i915_drv.h"
11
+
#include "intel_fb.h"
12
+
#include "intel_fb_bo.h"
13
+
14
+
void intel_fb_bo_framebuffer_fini(struct drm_i915_gem_object *obj)
15
+
{
16
+
/* Nothing to do for i915 */
17
+
}
18
+
19
+
int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb,
20
+
struct drm_i915_gem_object *obj,
21
+
struct drm_mode_fb_cmd2 *mode_cmd)
22
+
{
23
+
struct drm_i915_private *i915 = to_i915(obj->base.dev);
24
+
unsigned int tiling, stride;
25
+
26
+
i915_gem_object_lock(obj, NULL);
27
+
tiling = i915_gem_object_get_tiling(obj);
28
+
stride = i915_gem_object_get_stride(obj);
29
+
i915_gem_object_unlock(obj);
30
+
31
+
if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
32
+
/*
33
+
* If there's a fence, enforce that
34
+
* the fb modifier and tiling mode match.
35
+
*/
36
+
if (tiling != I915_TILING_NONE &&
37
+
tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
38
+
drm_dbg_kms(&i915->drm,
39
+
"tiling_mode doesn't match fb modifier\n");
40
+
return -EINVAL;
41
+
}
42
+
} else {
43
+
if (tiling == I915_TILING_X) {
44
+
mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
45
+
} else if (tiling == I915_TILING_Y) {
46
+
drm_dbg_kms(&i915->drm,
47
+
"No Y tiling for legacy addfb\n");
48
+
return -EINVAL;
49
+
}
50
+
}
51
+
52
+
/*
53
+
* gen2/3 display engine uses the fence if present,
54
+
* so the tiling mode must match the fb modifier exactly.
55
+
*/
56
+
if (DISPLAY_VER(i915) < 4 &&
57
+
tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
58
+
drm_dbg_kms(&i915->drm,
59
+
"tiling_mode must match fb modifier exactly on gen2/3\n");
60
+
return -EINVAL;
61
+
}
62
+
63
+
/*
64
+
* If there's a fence, enforce that
65
+
* the fb pitch and fence stride match.
66
+
*/
67
+
if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
68
+
drm_dbg_kms(&i915->drm,
69
+
"pitch (%d) must match tiling stride (%d)\n",
70
+
mode_cmd->pitches[0], stride);
71
+
return -EINVAL;
72
+
}
73
+
74
+
return 0;
75
+
}
76
+
77
+
struct drm_i915_gem_object *
78
+
intel_fb_bo_lookup_valid_bo(struct drm_i915_private *i915,
79
+
struct drm_file *filp,
80
+
const struct drm_mode_fb_cmd2 *mode_cmd)
81
+
{
82
+
struct drm_i915_gem_object *obj;
83
+
84
+
obj = i915_gem_object_lookup(filp, mode_cmd->handles[0]);
85
+
if (!obj)
86
+
return ERR_PTR(-ENOENT);
87
+
88
+
/* object is backed with LMEM for discrete */
89
+
if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM_0)) {
90
+
/* object is "remote", not in local memory */
91
+
i915_gem_object_put(obj);
92
+
drm_dbg_kms(&i915->drm, "framebuffer must reside in local memory\n");
93
+
return ERR_PTR(-EREMOTE);
94
+
}
95
+
96
+
return obj;
97
+
}
+26
drivers/gpu/drm/i915/display/intel_fb_bo.h
+26
drivers/gpu/drm/i915/display/intel_fb_bo.h
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/*
3
+
* Copyright © 2021 Intel Corporation
4
+
*/
5
+
6
+
#ifndef __INTEL_FB_BO_H__
7
+
#define __INTEL_FB_BO_H__
8
+
9
+
struct drm_file;
10
+
struct drm_mode_fb_cmd2;
11
+
struct drm_i915_gem_object;
12
+
struct drm_i915_private;
13
+
struct intel_framebuffer;
14
+
15
+
void intel_fb_bo_framebuffer_fini(struct drm_i915_gem_object *obj);
16
+
17
+
int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb,
18
+
struct drm_i915_gem_object *obj,
19
+
struct drm_mode_fb_cmd2 *mode_cmd);
20
+
21
+
struct drm_i915_gem_object *
22
+
intel_fb_bo_lookup_valid_bo(struct drm_i915_private *i915,
23
+
struct drm_file *filp,
24
+
const struct drm_mode_fb_cmd2 *user_mode_cmd);
25
+
26
+
#endif
+1
-1
drivers/gpu/drm/i915/display/intel_fbc.c
+1
-1
drivers/gpu/drm/i915/display/intel_fbc.c
···
1235
1235
* Recommendation is to keep this combination disabled
1236
1236
* Bspec: 50422 HSD: 14010260002
1237
1237
*/
1238
-
if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) {
1238
+
if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) {
1239
1239
plane_state->no_fbc_reason = "PSR2 enabled";
1240
1240
return 0;
1241
1241
}
+10
-102
drivers/gpu/drm/i915/display/intel_fbdev.c
+10
-102
drivers/gpu/drm/i915/display/intel_fbdev.c
···
43
43
#include <drm/drm_fourcc.h>
44
44
#include <drm/drm_gem_framebuffer_helper.h>
45
45
46
-
#include "gem/i915_gem_lmem.h"
47
46
#include "gem/i915_gem_mman.h"
48
47
49
48
#include "i915_drv.h"
···
50
51
#include "intel_fb.h"
51
52
#include "intel_fb_pin.h"
52
53
#include "intel_fbdev.h"
54
+
#include "intel_fbdev_fb.h"
53
55
#include "intel_frontbuffer.h"
54
56
55
57
struct intel_fbdev {
···
146
146
.fb_mmap = intel_fbdev_mmap,
147
147
};
148
148
149
-
static int intelfb_alloc(struct drm_fb_helper *helper,
150
-
struct drm_fb_helper_surface_size *sizes)
151
-
{
152
-
struct intel_fbdev *ifbdev = to_intel_fbdev(helper);
153
-
struct drm_framebuffer *fb;
154
-
struct drm_device *dev = helper->dev;
155
-
struct drm_i915_private *dev_priv = to_i915(dev);
156
-
struct drm_mode_fb_cmd2 mode_cmd = {};
157
-
struct drm_i915_gem_object *obj;
158
-
int size;
159
-
160
-
/* we don't do packed 24bpp */
161
-
if (sizes->surface_bpp == 24)
162
-
sizes->surface_bpp = 32;
163
-
164
-
mode_cmd.width = sizes->surface_width;
165
-
mode_cmd.height = sizes->surface_height;
166
-
167
-
mode_cmd.pitches[0] = ALIGN(mode_cmd.width *
168
-
DIV_ROUND_UP(sizes->surface_bpp, 8), 64);
169
-
mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
170
-
sizes->surface_depth);
171
-
172
-
size = mode_cmd.pitches[0] * mode_cmd.height;
173
-
size = PAGE_ALIGN(size);
174
-
175
-
obj = ERR_PTR(-ENODEV);
176
-
if (HAS_LMEM(dev_priv)) {
177
-
obj = i915_gem_object_create_lmem(dev_priv, size,
178
-
I915_BO_ALLOC_CONTIGUOUS |
179
-
I915_BO_ALLOC_USER);
180
-
} else {
181
-
/*
182
-
* If the FB is too big, just don't use it since fbdev is not very
183
-
* important and we should probably use that space with FBC or other
184
-
* features.
185
-
*
186
-
* Also skip stolen on MTL as Wa_22018444074 mitigation.
187
-
*/
188
-
if (!(IS_METEORLAKE(dev_priv)) && size * 2 < dev_priv->dsm.usable_size)
189
-
obj = i915_gem_object_create_stolen(dev_priv, size);
190
-
if (IS_ERR(obj))
191
-
obj = i915_gem_object_create_shmem(dev_priv, size);
192
-
}
193
-
194
-
if (IS_ERR(obj)) {
195
-
drm_err(&dev_priv->drm, "failed to allocate framebuffer (%pe)\n", obj);
196
-
return PTR_ERR(obj);
197
-
}
198
-
199
-
fb = intel_framebuffer_create(obj, &mode_cmd);
200
-
i915_gem_object_put(obj);
201
-
if (IS_ERR(fb))
202
-
return PTR_ERR(fb);
203
-
204
-
ifbdev->fb = to_intel_framebuffer(fb);
205
-
return 0;
206
-
}
207
-
208
149
static int intelfb_create(struct drm_fb_helper *helper,
209
150
struct drm_fb_helper_surface_size *sizes)
210
151
{
···
154
213
struct drm_device *dev = helper->dev;
155
214
struct drm_i915_private *dev_priv = to_i915(dev);
156
215
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
157
-
struct i915_ggtt *ggtt = to_gt(dev_priv)->ggtt;
158
216
const struct i915_gtt_view view = {
159
217
.type = I915_GTT_VIEW_NORMAL,
160
218
};
···
162
222
struct i915_vma *vma;
163
223
unsigned long flags = 0;
164
224
bool prealloc = false;
165
-
void __iomem *vaddr;
166
225
struct drm_i915_gem_object *obj;
167
-
struct i915_gem_ww_ctx ww;
168
226
int ret;
169
227
170
228
mutex_lock(&ifbdev->hpd_lock);
···
183
245
intel_fb = ifbdev->fb = NULL;
184
246
}
185
247
if (!intel_fb || drm_WARN_ON(dev, !intel_fb_obj(&intel_fb->base))) {
248
+
struct drm_framebuffer *fb;
186
249
drm_dbg_kms(&dev_priv->drm,
187
250
"no BIOS fb, allocating a new one\n");
188
-
ret = intelfb_alloc(helper, sizes);
189
-
if (ret)
190
-
return ret;
191
-
intel_fb = ifbdev->fb;
251
+
fb = intel_fbdev_fb_alloc(helper, sizes);
252
+
if (IS_ERR(fb))
253
+
return PTR_ERR(fb);
254
+
intel_fb = ifbdev->fb = to_intel_framebuffer(fb);
192
255
} else {
193
256
drm_dbg_kms(&dev_priv->drm, "re-using BIOS fb\n");
194
257
prealloc = true;
···
222
283
info->fbops = &intelfb_ops;
223
284
224
285
obj = intel_fb_obj(&intel_fb->base);
225
-
if (i915_gem_object_is_lmem(obj)) {
226
-
struct intel_memory_region *mem = obj->mm.region;
227
286
228
-
/* Use fbdev's framebuffer from lmem for discrete */
229
-
info->fix.smem_start =
230
-
(unsigned long)(mem->io_start +
231
-
i915_gem_object_get_dma_address(obj, 0));
232
-
info->fix.smem_len = obj->base.size;
233
-
} else {
234
-
/* Our framebuffer is the entirety of fbdev's system memory */
235
-
info->fix.smem_start =
236
-
(unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma));
237
-
info->fix.smem_len = vma->size;
238
-
}
239
-
240
-
for_i915_gem_ww(&ww, ret, false) {
241
-
ret = i915_gem_object_lock(vma->obj, &ww);
242
-
243
-
if (ret)
244
-
continue;
245
-
246
-
vaddr = i915_vma_pin_iomap(vma);
247
-
if (IS_ERR(vaddr)) {
248
-
drm_err(&dev_priv->drm,
249
-
"Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
250
-
ret = PTR_ERR(vaddr);
251
-
continue;
252
-
}
253
-
}
254
-
287
+
ret = intel_fbdev_fb_fill_info(dev_priv, info, obj, vma);
255
288
if (ret)
256
289
goto out_unpin;
257
-
258
-
info->screen_base = vaddr;
259
-
info->screen_size = vma->size;
260
290
261
291
drm_fb_helper_fill_info(info, &ifbdev->helper, sizes);
262
292
···
233
325
* If the object is stolen however, it will be full of whatever
234
326
* garbage was left in there.
235
327
*/
236
-
if (!i915_gem_object_is_shmem(vma->obj) && !prealloc)
328
+
if (!i915_gem_object_is_shmem(obj) && !prealloc)
237
329
memset_io(info->screen_base, 0, info->screen_size);
238
330
239
331
/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
···
332
424
continue;
333
425
}
334
426
335
-
if (obj->base.size > max_size) {
427
+
if (intel_bo_to_drm_bo(obj)->size > max_size) {
336
428
drm_dbg_kms(&i915->drm,
337
429
"found possible fb from [PLANE:%d:%s]\n",
338
430
plane->base.base.id, plane->base.name);
339
431
fb = to_intel_framebuffer(plane_state->uapi.fb);
340
-
max_size = obj->base.size;
432
+
max_size = intel_bo_to_drm_bo(obj)->size;
341
433
}
342
434
}
343
435
+115
drivers/gpu/drm/i915/display/intel_fbdev_fb.c
+115
drivers/gpu/drm/i915/display/intel_fbdev_fb.c
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/*
3
+
* Copyright © 2023 Intel Corporation
4
+
*/
5
+
6
+
#include <drm/drm_fb_helper.h>
7
+
8
+
#include "gem/i915_gem_lmem.h"
9
+
10
+
#include "i915_drv.h"
11
+
#include "intel_display_types.h"
12
+
#include "intel_fbdev_fb.h"
13
+
14
+
struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
15
+
struct drm_fb_helper_surface_size *sizes)
16
+
{
17
+
struct drm_framebuffer *fb;
18
+
struct drm_device *dev = helper->dev;
19
+
struct drm_i915_private *dev_priv = to_i915(dev);
20
+
struct drm_mode_fb_cmd2 mode_cmd = {};
21
+
struct drm_i915_gem_object *obj;
22
+
int size;
23
+
24
+
/* we don't do packed 24bpp */
25
+
if (sizes->surface_bpp == 24)
26
+
sizes->surface_bpp = 32;
27
+
28
+
mode_cmd.width = sizes->surface_width;
29
+
mode_cmd.height = sizes->surface_height;
30
+
31
+
mode_cmd.pitches[0] = ALIGN(mode_cmd.width *
32
+
DIV_ROUND_UP(sizes->surface_bpp, 8), 64);
33
+
mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
34
+
sizes->surface_depth);
35
+
36
+
size = mode_cmd.pitches[0] * mode_cmd.height;
37
+
size = PAGE_ALIGN(size);
38
+
39
+
obj = ERR_PTR(-ENODEV);
40
+
if (HAS_LMEM(dev_priv)) {
41
+
obj = i915_gem_object_create_lmem(dev_priv, size,
42
+
I915_BO_ALLOC_CONTIGUOUS |
43
+
I915_BO_ALLOC_USER);
44
+
} else {
45
+
/*
46
+
* If the FB is too big, just don't use it since fbdev is not very
47
+
* important and we should probably use that space with FBC or other
48
+
* features.
49
+
*
50
+
* Also skip stolen on MTL as Wa_22018444074 mitigation.
51
+
*/
52
+
if (!(IS_METEORLAKE(dev_priv)) && size * 2 < dev_priv->dsm.usable_size)
53
+
obj = i915_gem_object_create_stolen(dev_priv, size);
54
+
if (IS_ERR(obj))
55
+
obj = i915_gem_object_create_shmem(dev_priv, size);
56
+
}
57
+
58
+
if (IS_ERR(obj)) {
59
+
drm_err(&dev_priv->drm, "failed to allocate framebuffer (%pe)\n", obj);
60
+
return ERR_PTR(-ENOMEM);
61
+
}
62
+
63
+
fb = intel_framebuffer_create(obj, &mode_cmd);
64
+
i915_gem_object_put(obj);
65
+
66
+
return fb;
67
+
}
68
+
69
+
int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info,
70
+
struct drm_i915_gem_object *obj, struct i915_vma *vma)
71
+
{
72
+
struct i915_gem_ww_ctx ww;
73
+
void __iomem *vaddr;
74
+
int ret;
75
+
76
+
if (i915_gem_object_is_lmem(obj)) {
77
+
struct intel_memory_region *mem = obj->mm.region;
78
+
79
+
/* Use fbdev's framebuffer from lmem for discrete */
80
+
info->fix.smem_start =
81
+
(unsigned long)(mem->io_start +
82
+
i915_gem_object_get_dma_address(obj, 0));
83
+
info->fix.smem_len = obj->base.size;
84
+
} else {
85
+
struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
86
+
87
+
/* Our framebuffer is the entirety of fbdev's system memory */
88
+
info->fix.smem_start =
89
+
(unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma));
90
+
info->fix.smem_len = vma->size;
91
+
}
92
+
93
+
for_i915_gem_ww(&ww, ret, false) {
94
+
ret = i915_gem_object_lock(vma->obj, &ww);
95
+
96
+
if (ret)
97
+
continue;
98
+
99
+
vaddr = i915_vma_pin_iomap(vma);
100
+
if (IS_ERR(vaddr)) {
101
+
drm_err(&i915->drm,
102
+
"Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
103
+
ret = PTR_ERR(vaddr);
104
+
continue;
105
+
}
106
+
}
107
+
108
+
if (ret)
109
+
return ret;
110
+
111
+
info->screen_base = vaddr;
112
+
info->screen_size = intel_bo_to_drm_bo(obj)->size;
113
+
114
+
return 0;
115
+
}
+21
drivers/gpu/drm/i915/display/intel_fbdev_fb.h
+21
drivers/gpu/drm/i915/display/intel_fbdev_fb.h
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/*
3
+
* Copyright © 2023 Intel Corporation
4
+
*/
5
+
6
+
#ifndef __INTEL_FBDEV_FB_H__
7
+
#define __INTEL_FBDEV_FB_H__
8
+
9
+
struct drm_fb_helper;
10
+
struct drm_fb_helper_surface_size;
11
+
struct drm_i915_gem_object;
12
+
struct drm_i915_private;
13
+
struct fb_info;
14
+
struct i915_vma;
15
+
16
+
struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
17
+
struct drm_fb_helper_surface_size *sizes);
18
+
int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info,
19
+
struct drm_i915_gem_object *obj, struct i915_vma *vma);
20
+
21
+
#endif
+4
drivers/gpu/drm/i915/display/intel_hdmi.c
+4
drivers/gpu/drm/i915/display/intel_hdmi.c
···
1983
1983
bool ycbcr_420_only;
1984
1984
enum intel_output_format sink_format;
1985
1985
1986
+
status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1987
+
if (status != MODE_OK)
1988
+
return status;
1989
+
1986
1990
if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1987
1991
clock *= 2;
1988
1992
+6
-1
drivers/gpu/drm/i915/display/intel_lvds.c
+6
-1
drivers/gpu/drm/i915/display/intel_lvds.c
···
185
185
/* Convert from 100ms to 100us units */
186
186
pps->t4 = val * 1000;
187
187
188
-
if (DISPLAY_VER(dev_priv) <= 4 &&
188
+
if (DISPLAY_VER(dev_priv) < 5 &&
189
189
pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
190
190
drm_dbg_kms(&dev_priv->drm,
191
191
"Panel power timings uninitialized, "
···
389
389
struct drm_display_mode *mode)
390
390
{
391
391
struct intel_connector *connector = to_intel_connector(_connector);
392
+
struct drm_i915_private *i915 = to_i915(connector->base.dev);
392
393
const struct drm_display_mode *fixed_mode =
393
394
intel_panel_fixed_mode(connector, mode);
394
395
int max_pixclk = to_i915(connector->base.dev)->max_dotclk_freq;
395
396
enum drm_mode_status status;
397
+
398
+
status = intel_cpu_transcoder_mode_valid(i915, mode);
399
+
if (status != MODE_OK)
400
+
return status;
396
401
397
402
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
398
403
return MODE_NO_DBLESCAN;
+16
-80
drivers/gpu/drm/i915/display/intel_psr.c
+16
-80
drivers/gpu/drm/i915/display/intel_psr.c
···
806
806
807
807
val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
808
808
809
-
if (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv))
809
+
if (DISPLAY_VER(dev_priv) < 14 && !IS_ALDERLAKE_P(dev_priv))
810
810
val |= EDP_SU_TRACK_ENABLE;
811
811
812
-
if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
812
+
if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) < 13)
813
813
val |= EDP_Y_COORDINATE_ENABLE;
814
814
815
815
val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp));
···
1094
1094
return true;
1095
1095
1096
1096
/* Not supported <13 / Wa_22012279113:adl-p */
1097
-
if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
1097
+
if (DISPLAY_VER(dev_priv) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
1098
1098
return false;
1099
1099
1100
1100
crtc_state->req_psr2_sdp_prior_scanline = true;
···
1221
1221
* over PSR2.
1222
1222
*/
1223
1223
if (crtc_state->dsc.compression_enable &&
1224
-
(DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv))) {
1224
+
(DISPLAY_VER(dev_priv) < 14 && !IS_ALDERLAKE_P(dev_priv))) {
1225
1225
drm_dbg_kms(&dev_priv->drm,
1226
1226
"PSR2 cannot be enabled since DSC is enabled\n");
1227
1227
return false;
···
1917
1917
intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
1918
1918
}
1919
1919
1920
-
void intel_psr2_disable_plane_sel_fetch_arm(struct intel_plane *plane,
1921
-
const struct intel_crtc_state *crtc_state)
1922
-
{
1923
-
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1924
-
enum pipe pipe = plane->pipe;
1925
-
1926
-
if (!crtc_state->enable_psr2_sel_fetch)
1927
-
return;
1928
-
1929
-
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
1930
-
}
1931
-
1932
-
void intel_psr2_program_plane_sel_fetch_arm(struct intel_plane *plane,
1933
-
const struct intel_crtc_state *crtc_state,
1934
-
const struct intel_plane_state *plane_state)
1935
-
{
1936
-
struct drm_i915_private *i915 = to_i915(plane->base.dev);
1937
-
enum pipe pipe = plane->pipe;
1938
-
1939
-
if (!crtc_state->enable_psr2_sel_fetch)
1940
-
return;
1941
-
1942
-
if (plane->id == PLANE_CURSOR)
1943
-
intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id),
1944
-
plane_state->ctl);
1945
-
else
1946
-
intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id),
1947
-
PLANE_SEL_FETCH_CTL_ENABLE);
1948
-
}
1949
-
1950
-
void intel_psr2_program_plane_sel_fetch_noarm(struct intel_plane *plane,
1951
-
const struct intel_crtc_state *crtc_state,
1952
-
const struct intel_plane_state *plane_state,
1953
-
int color_plane)
1954
-
{
1955
-
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1956
-
enum pipe pipe = plane->pipe;
1957
-
const struct drm_rect *clip;
1958
-
u32 val;
1959
-
int x, y;
1960
-
1961
-
if (!crtc_state->enable_psr2_sel_fetch)
1962
-
return;
1963
-
1964
-
if (plane->id == PLANE_CURSOR)
1965
-
return;
1966
-
1967
-
clip = &plane_state->psr2_sel_fetch_area;
1968
-
1969
-
val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
1970
-
val |= plane_state->uapi.dst.x1;
1971
-
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
1972
-
1973
-
x = plane_state->view.color_plane[color_plane].x;
1974
-
1975
-
/*
1976
-
* From Bspec: UV surface Start Y Position = half of Y plane Y
1977
-
* start position.
1978
-
*/
1979
-
if (!color_plane)
1980
-
y = plane_state->view.color_plane[color_plane].y + clip->y1;
1981
-
else
1982
-
y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2;
1983
-
1984
-
val = y << 16 | x;
1985
-
1986
-
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
1987
-
val);
1988
-
1989
-
/* Sizes are 0 based */
1990
-
val = (drm_rect_height(clip) - 1) << 16;
1991
-
val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
1992
-
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
1993
-
}
1994
-
1995
1920
void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
1996
1921
{
1997
1922
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
···
2176
2251
continue;
2177
2252
2178
2253
inter = pipe_clip;
2179
-
if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst))
2254
+
sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
2255
+
if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) {
2256
+
sel_fetch_area->y1 = -1;
2257
+
sel_fetch_area->y2 = -1;
2258
+
/*
2259
+
* if plane sel fetch was previously enabled ->
2260
+
* disable it
2261
+
*/
2262
+
if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0)
2263
+
crtc_state->update_planes |= BIT(plane->id);
2264
+
2180
2265
continue;
2266
+
}
2181
2267
2182
2268
if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
2183
2269
full_update = true;
-10
drivers/gpu/drm/i915/display/intel_psr.h
-10
drivers/gpu/drm/i915/display/intel_psr.h
···
55
55
int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
56
56
struct intel_crtc *crtc);
57
57
void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state);
58
-
void intel_psr2_program_plane_sel_fetch_noarm(struct intel_plane *plane,
59
-
const struct intel_crtc_state *crtc_state,
60
-
const struct intel_plane_state *plane_state,
61
-
int color_plane);
62
-
void intel_psr2_program_plane_sel_fetch_arm(struct intel_plane *plane,
63
-
const struct intel_crtc_state *crtc_state,
64
-
const struct intel_plane_state *plane_state);
65
-
66
-
void intel_psr2_disable_plane_sel_fetch_arm(struct intel_plane *plane,
67
-
const struct intel_crtc_state *crtc_state);
68
58
void intel_psr_pause(struct intel_dp *intel_dp);
69
59
void intel_psr_resume(struct intel_dp *intel_dp);
70
60
+7
-1
drivers/gpu/drm/i915/display/intel_sdvo.c
+7
-1
drivers/gpu/drm/i915/display/intel_sdvo.c
···
1931
1931
intel_sdvo_mode_valid(struct drm_connector *connector,
1932
1932
struct drm_display_mode *mode)
1933
1933
{
1934
+
struct drm_i915_private *i915 = to_i915(connector->dev);
1934
1935
struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
1935
1936
struct intel_sdvo_connector *intel_sdvo_connector =
1936
1937
to_intel_sdvo_connector(connector);
1937
-
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1938
1938
bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state);
1939
+
int max_dotclk = i915->max_dotclk_freq;
1940
+
enum drm_mode_status status;
1939
1941
int clock = mode->clock;
1942
+
1943
+
status = intel_cpu_transcoder_mode_valid(i915, mode);
1944
+
if (status != MODE_OK)
1945
+
return status;
1940
1946
1941
1947
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1942
1948
return MODE_NO_DBLESCAN;
+1
-1
drivers/gpu/drm/i915/display/intel_snps_phy.c
+1
-1
drivers/gpu/drm/i915/display/intel_snps_phy.c
+7
-1
drivers/gpu/drm/i915/display/intel_tv.c
+7
-1
drivers/gpu/drm/i915/display/intel_tv.c
···
958
958
intel_tv_mode_valid(struct drm_connector *connector,
959
959
struct drm_display_mode *mode)
960
960
{
961
+
struct drm_i915_private *i915 = to_i915(connector->dev);
961
962
const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
962
-
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
963
+
int max_dotclk = i915->max_dotclk_freq;
964
+
enum drm_mode_status status;
965
+
966
+
status = intel_cpu_transcoder_mode_valid(i915, mode);
967
+
if (status != MODE_OK)
968
+
return status;
963
969
964
970
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
965
971
return MODE_NO_DBLESCAN;
+41
-10
drivers/gpu/drm/i915/display/intel_vblank.c
+41
-10
drivers/gpu/drm/i915/display/intel_vblank.c
···
265
265
return (scanline + vtotal - crtc->scanline_offset) % vtotal;
266
266
}
267
267
268
+
/*
269
+
* The uncore version of the spin lock functions is used to decide
270
+
* whether we need to lock the uncore lock or not. This is only
271
+
* needed in i915, not in Xe.
272
+
*
273
+
* This lock in i915 is needed because some old platforms (at least
274
+
* IVB and possibly HSW as well), which are not supported in Xe, need
275
+
* all register accesses to the same cacheline to be serialized,
276
+
* otherwise they may hang.
277
+
*/
278
+
static void intel_vblank_section_enter(struct drm_i915_private *i915)
279
+
__acquires(i915->uncore.lock)
280
+
{
281
+
#ifdef I915
282
+
spin_lock(&i915->uncore.lock);
283
+
#endif
284
+
}
285
+
286
+
static void intel_vblank_section_exit(struct drm_i915_private *i915)
287
+
__releases(i915->uncore.lock)
288
+
{
289
+
#ifdef I915
290
+
spin_unlock(&i915->uncore.lock);
291
+
#endif
292
+
}
293
+
268
294
static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
269
295
bool in_vblank_irq,
270
296
int *vpos, int *hpos,
···
328
302
}
329
303
330
304
/*
331
-
* Lock uncore.lock, as we will do multiple timing critical raw
332
-
* register reads, potentially with preemption disabled, so the
333
-
* following code must not block on uncore.lock.
305
+
* Enter vblank critical section, as we will do multiple
306
+
* timing critical raw register reads, potentially with
307
+
* preemption disabled, so the following code must not block.
334
308
*/
335
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
309
+
local_irq_save(irqflags);
310
+
intel_vblank_section_enter(dev_priv);
336
311
337
312
/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
338
313
···
401
374
402
375
/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
403
376
404
-
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
377
+
intel_vblank_section_exit(dev_priv);
378
+
local_irq_restore(irqflags);
405
379
406
380
/*
407
381
* While in vblank, position will be negative
···
440
412
unsigned long irqflags;
441
413
int position;
442
414
443
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
415
+
local_irq_save(irqflags);
416
+
intel_vblank_section_enter(dev_priv);
417
+
444
418
position = __intel_get_crtc_scanline(crtc);
445
-
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
419
+
420
+
intel_vblank_section_exit(dev_priv);
421
+
local_irq_restore(irqflags);
446
422
447
423
return position;
448
424
}
···
569
537
* Need to audit everything to make sure it's safe.
570
538
*/
571
539
spin_lock_irqsave(&i915->drm.vblank_time_lock, irqflags);
572
-
spin_lock(&i915->uncore.lock);
540
+
intel_vblank_section_enter(i915);
573
541
574
542
drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
575
543
···
578
546
crtc->mode_flags = mode_flags;
579
547
580
548
crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state);
581
-
582
-
spin_unlock(&i915->uncore.lock);
549
+
intel_vblank_section_exit(i915);
583
550
spin_unlock_irqrestore(&i915->drm.vblank_time_lock, irqflags);
584
551
}
+75
-3
drivers/gpu/drm/i915/display/skl_universal_plane.c
+75
-3
drivers/gpu/drm/i915/display/skl_universal_plane.c
···
18
18
#include "intel_fbc.h"
19
19
#include "intel_frontbuffer.h"
20
20
#include "intel_psr.h"
21
+
#include "intel_psr_regs.h"
21
22
#include "skl_scaler.h"
22
23
#include "skl_universal_plane.h"
23
24
#include "skl_watermark.h"
···
630
629
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
631
630
}
632
631
632
+
static void icl_plane_disable_sel_fetch_arm(struct intel_plane *plane,
633
+
const struct intel_crtc_state *crtc_state)
634
+
{
635
+
struct drm_i915_private *i915 = to_i915(plane->base.dev);
636
+
enum pipe pipe = plane->pipe;
637
+
638
+
if (!crtc_state->enable_psr2_sel_fetch)
639
+
return;
640
+
641
+
intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
642
+
}
643
+
633
644
static void
634
645
icl_plane_disable_arm(struct intel_plane *plane,
635
646
const struct intel_crtc_state *crtc_state)
···
655
642
656
643
skl_write_plane_wm(plane, crtc_state);
657
644
658
-
intel_psr2_disable_plane_sel_fetch_arm(plane, crtc_state);
645
+
icl_plane_disable_sel_fetch_arm(plane, crtc_state);
659
646
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
660
647
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
661
648
}
···
1210
1197
skl_plane_surf(plane_state, 0));
1211
1198
}
1212
1199
1200
+
static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane,
1201
+
const struct intel_crtc_state *crtc_state,
1202
+
const struct intel_plane_state *plane_state,
1203
+
int color_plane)
1204
+
{
1205
+
struct drm_i915_private *i915 = to_i915(plane->base.dev);
1206
+
enum pipe pipe = plane->pipe;
1207
+
const struct drm_rect *clip;
1208
+
u32 val;
1209
+
int x, y;
1210
+
1211
+
if (!crtc_state->enable_psr2_sel_fetch)
1212
+
return;
1213
+
1214
+
clip = &plane_state->psr2_sel_fetch_area;
1215
+
1216
+
val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
1217
+
val |= plane_state->uapi.dst.x1;
1218
+
intel_de_write_fw(i915, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
1219
+
1220
+
x = plane_state->view.color_plane[color_plane].x;
1221
+
1222
+
/*
1223
+
* From Bspec: UV surface Start Y Position = half of Y plane Y
1224
+
* start position.
1225
+
*/
1226
+
if (!color_plane)
1227
+
y = plane_state->view.color_plane[color_plane].y + clip->y1;
1228
+
else
1229
+
y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2;
1230
+
1231
+
val = y << 16 | x;
1232
+
1233
+
intel_de_write_fw(i915, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
1234
+
val);
1235
+
1236
+
/* Sizes are 0 based */
1237
+
val = (drm_rect_height(clip) - 1) << 16;
1238
+
val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
1239
+
intel_de_write_fw(i915, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
1240
+
}
1241
+
1213
1242
static void
1214
1243
icl_plane_update_noarm(struct intel_plane *plane,
1215
1244
const struct intel_crtc_state *crtc_state,
···
1324
1269
if (plane_state->force_black)
1325
1270
icl_plane_csc_load_black(plane);
1326
1271
1327
-
intel_psr2_program_plane_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane);
1272
+
icl_plane_update_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane);
1273
+
}
1274
+
1275
+
static void icl_plane_update_sel_fetch_arm(struct intel_plane *plane,
1276
+
const struct intel_crtc_state *crtc_state,
1277
+
const struct intel_plane_state *plane_state)
1278
+
{
1279
+
struct drm_i915_private *i915 = to_i915(plane->base.dev);
1280
+
enum pipe pipe = plane->pipe;
1281
+
1282
+
if (!crtc_state->enable_psr2_sel_fetch)
1283
+
return;
1284
+
1285
+
if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0)
1286
+
intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id),
1287
+
PLANE_SEL_FETCH_CTL_ENABLE);
1288
+
else
1289
+
icl_plane_disable_sel_fetch_arm(plane, crtc_state);
1328
1290
}
1329
1291
1330
1292
static void
···
1368
1296
if (plane_state->scaler_id >= 0)
1369
1297
skl_program_plane_scaler(plane, crtc_state, plane_state);
1370
1298
1371
-
intel_psr2_program_plane_sel_fetch_arm(plane, crtc_state, plane_state);
1299
+
icl_plane_update_sel_fetch_arm(plane, crtc_state, plane_state);
1372
1300
1373
1301
/*
1374
1302
* The control register self-arms if the plane was previously
+18
-10
drivers/gpu/drm/i915/display/vlv_dsi.c
+18
-10
drivers/gpu/drm/i915/display/vlv_dsi.c
···
1532
1532
}
1533
1533
}
1534
1534
1535
-
static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1536
-
{
1537
-
struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1538
-
1539
-
intel_dsi_vbt_gpio_cleanup(intel_dsi);
1540
-
intel_encoder_destroy(encoder);
1541
-
}
1542
-
1543
1535
static const struct drm_encoder_funcs intel_dsi_funcs = {
1544
-
.destroy = intel_dsi_encoder_destroy,
1536
+
.destroy = intel_encoder_destroy,
1545
1537
};
1538
+
1539
+
static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector,
1540
+
struct drm_display_mode *mode)
1541
+
{
1542
+
struct drm_i915_private *i915 = to_i915(connector->dev);
1543
+
1544
+
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1545
+
enum drm_mode_status status;
1546
+
1547
+
status = intel_cpu_transcoder_mode_valid(i915, mode);
1548
+
if (status != MODE_OK)
1549
+
return status;
1550
+
}
1551
+
1552
+
return intel_dsi_mode_valid(connector, mode);
1553
+
}
1546
1554
1547
1555
static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1548
1556
.get_modes = intel_dsi_get_modes,
1549
-
.mode_valid = intel_dsi_mode_valid,
1557
+
.mode_valid = vlv_dsi_mode_valid,
1550
1558
.atomic_check = intel_digital_connector_atomic_check,
1551
1559
};
1552
1560
+10
-14
drivers/gpu/drm/i915/intel_runtime_pm.c
+10
-14
drivers/gpu/drm/i915/intel_runtime_pm.c
···
50
50
* present for a given platform.
51
51
*/
52
52
53
+
static struct drm_i915_private *rpm_to_i915(struct intel_runtime_pm *rpm)
54
+
{
55
+
return container_of(rpm, struct drm_i915_private, runtime_pm);
56
+
}
57
+
53
58
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
54
59
55
60
#include <linux/sort.h>
···
354
349
static intel_wakeref_t __intel_runtime_pm_get(struct intel_runtime_pm *rpm,
355
350
bool wakelock)
356
351
{
357
-
struct drm_i915_private *i915 = container_of(rpm,
358
-
struct drm_i915_private,
359
-
runtime_pm);
352
+
struct drm_i915_private *i915 = rpm_to_i915(rpm);
360
353
int ret;
361
354
362
355
ret = pm_runtime_get_sync(rpm->kdev);
···
559
556
*/
560
557
void intel_runtime_pm_enable(struct intel_runtime_pm *rpm)
561
558
{
562
-
struct drm_i915_private *i915 = container_of(rpm,
563
-
struct drm_i915_private,
564
-
runtime_pm);
559
+
struct drm_i915_private *i915 = rpm_to_i915(rpm);
565
560
struct device *kdev = rpm->kdev;
566
561
567
562
/*
···
612
611
613
612
void intel_runtime_pm_disable(struct intel_runtime_pm *rpm)
614
613
{
615
-
struct drm_i915_private *i915 = container_of(rpm,
616
-
struct drm_i915_private,
617
-
runtime_pm);
614
+
struct drm_i915_private *i915 = rpm_to_i915(rpm);
618
615
struct device *kdev = rpm->kdev;
619
616
620
617
/* Transfer rpm ownership back to core */
···
627
628
628
629
void intel_runtime_pm_driver_release(struct intel_runtime_pm *rpm)
629
630
{
630
-
struct drm_i915_private *i915 = container_of(rpm,
631
-
struct drm_i915_private,
632
-
runtime_pm);
631
+
struct drm_i915_private *i915 = rpm_to_i915(rpm);
633
632
int count = atomic_read(&rpm->wakeref_count);
634
633
635
634
intel_wakeref_auto_fini(&rpm->userfault_wakeref);
···
642
645
643
646
void intel_runtime_pm_init_early(struct intel_runtime_pm *rpm)
644
647
{
645
-
struct drm_i915_private *i915 =
646
-
container_of(rpm, struct drm_i915_private, runtime_pm);
648
+
struct drm_i915_private *i915 = rpm_to_i915(rpm);
647
649
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
648
650
struct device *kdev = &pdev->dev;
649
651
+1
-1
drivers/gpu/drm/i915/selftests/i915_syncmap.c
+1
-1
drivers/gpu/drm/i915/selftests/i915_syncmap.c