Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull more clk updates from Stephen Boyd:
"This is the final part of the clk patches for this merge window.
The clk rate range series needed another week to fully bake. Maxime
fixed the bug that broke clk notifiers and prevented this from being
included in the first pull request. He also added a unit test on top
to make sure it doesn't break so easily again. The majority of the
series fixes up how the clk_set_rate_*() APIs work, particularly
around when the rate constraints are dropped and how they move around
when reparenting clks. Overall it's a much needed improvement to the
clk rate range APIs that used to be pretty broken if you looked
sideways.
Beyond the core changes there are a few driver fixes for a compilation
issue or improper data causing clks to fail to register or have the
wrong parents. These are good to get in before the first -rc so that
the system actually boots on the affected devices"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (31 commits)
clk: tegra: Fix Tegra PWM parent clock
clk: at91: fix the build with binutils 2.27
clk: qcom: gcc-msm8660: Drop hardcoded fixed board clocks
clk: mediatek: clk-mux: Add .determine_rate() callback
clk: tests: Add tests for notifiers
clk: Update req_rate on __clk_recalc_rates()
clk: tests: Add missing test case for ranges
clk: qcom: clk-rcg2: Take clock boundaries into consideration for gfx3d
clk: Introduce the clk_hw_get_rate_range function
clk: Zero the clk_rate_request structure
clk: Stop forwarding clk_rate_requests to the parent
clk: Constify clk_has_parent()
clk: Introduce clk_core_has_parent()
clk: Switch from __clk_determine_rate to clk_core_round_rate_nolock
clk: Add our request boundaries in clk_core_init_rate_req
clk: Introduce clk_hw_init_rate_request()
clk: Move clk_core_init_rate_req() from clk_core_round_rate_nolock() to its caller
clk: Change clk_core_init_rate_req prototype
clk: Set req_rate on reparenting
clk: Take into account uncached clocks in clk_set_rate_range()
...
+1833
-131
+3
-2
drivers/clk/at91/clk-generated.c
+3
-2
drivers/clk/at91/clk-generated.c
···
136
136
{
137
137
struct clk_generated *gck = to_clk_generated(hw);
138
138
struct clk_hw *parent = NULL;
139
-
struct clk_rate_request req_parent = *req;
140
139
long best_rate = -EINVAL;
141
140
unsigned long min_rate, parent_rate;
142
141
int best_diff = -1;
···
191
192
goto end;
192
193
193
194
for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
194
-
req_parent.rate = req->rate * div;
195
+
struct clk_rate_request req_parent;
196
+
197
+
clk_hw_forward_rate_request(hw, req, parent, &req_parent, req->rate * div);
195
198
if (__clk_determine_rate(parent, &req_parent))
196
199
continue;
197
200
clk_generated_best_diff(req, parent, req_parent.rate, div,
+8
-5
drivers/clk/at91/clk-master.c
+8
-5
drivers/clk/at91/clk-master.c
···
581
581
struct clk_rate_request *req)
582
582
{
583
583
struct clk_master *master = to_clk_master(hw);
584
-
struct clk_rate_request req_parent = *req;
585
584
struct clk_hw *parent;
586
585
long best_rate = LONG_MIN, best_diff = LONG_MIN;
587
586
unsigned long parent_rate;
···
617
618
goto end;
618
619
619
620
for (div = 0; div < MASTER_PRES_MAX + 1; div++) {
620
-
if (div == MASTER_PRES_MAX)
621
-
req_parent.rate = req->rate * 3;
622
-
else
623
-
req_parent.rate = req->rate << div;
621
+
struct clk_rate_request req_parent;
622
+
unsigned long req_rate;
624
623
624
+
if (div == MASTER_PRES_MAX)
625
+
req_rate = req->rate * 3;
626
+
else
627
+
req_rate = req->rate << div;
628
+
629
+
clk_hw_forward_rate_request(hw, req, parent, &req_parent, req_rate);
625
630
if (__clk_determine_rate(parent, &req_parent))
626
631
continue;
627
632
+2
-2
drivers/clk/at91/clk-peripheral.c
+2
-2
drivers/clk/at91/clk-peripheral.c
···
269
269
{
270
270
struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
271
271
struct clk_hw *parent = clk_hw_get_parent(hw);
272
-
struct clk_rate_request req_parent = *req;
273
272
unsigned long parent_rate = clk_hw_get_rate(parent);
274
273
unsigned long tmp_rate;
275
274
long best_rate = LONG_MIN;
···
301
302
goto end;
302
303
303
304
for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
304
-
req_parent.rate = req->rate << shift;
305
+
struct clk_rate_request req_parent;
305
306
307
+
clk_hw_forward_rate_request(hw, req, parent, &req_parent, req->rate << shift);
306
308
if (__clk_determine_rate(parent, &req_parent))
307
309
continue;
308
310
+4
-2
drivers/clk/clk-composite.c
+4
-2
drivers/clk/clk-composite.c
···
85
85
req->best_parent_hw = NULL;
86
86
87
87
if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
88
-
struct clk_rate_request tmp_req = *req;
88
+
struct clk_rate_request tmp_req;
89
89
90
90
parent = clk_hw_get_parent(mux_hw);
91
91
92
+
clk_hw_forward_rate_request(hw, req, parent, &tmp_req, req->rate);
92
93
ret = clk_composite_determine_rate_for_parent(rate_hw,
93
94
&tmp_req,
94
95
parent,
···
105
104
}
106
105
107
106
for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) {
108
-
struct clk_rate_request tmp_req = *req;
107
+
struct clk_rate_request tmp_req;
109
108
110
109
parent = clk_hw_get_parent_by_index(mux_hw, i);
111
110
if (!parent)
112
111
continue;
113
112
113
+
clk_hw_forward_rate_request(hw, req, parent, &tmp_req, req->rate);
114
114
ret = clk_composite_determine_rate_for_parent(rate_hw,
115
115
&tmp_req,
116
116
parent,
+10
-10
drivers/clk/clk-divider.c
+10
-10
drivers/clk/clk-divider.c
···
386
386
const struct clk_div_table *table,
387
387
u8 width, unsigned long flags)
388
388
{
389
-
struct clk_rate_request req = {
390
-
.rate = rate,
391
-
.best_parent_rate = *prate,
392
-
.best_parent_hw = parent,
393
-
};
389
+
struct clk_rate_request req;
394
390
int ret;
391
+
392
+
clk_hw_init_rate_request(hw, &req, rate);
393
+
req.best_parent_rate = *prate;
394
+
req.best_parent_hw = parent;
395
395
396
396
ret = divider_determine_rate(hw, &req, table, width, flags);
397
397
if (ret)
···
408
408
const struct clk_div_table *table, u8 width,
409
409
unsigned long flags, unsigned int val)
410
410
{
411
-
struct clk_rate_request req = {
412
-
.rate = rate,
413
-
.best_parent_rate = *prate,
414
-
.best_parent_hw = parent,
415
-
};
411
+
struct clk_rate_request req;
416
412
int ret;
413
+
414
+
clk_hw_init_rate_request(hw, &req, rate);
415
+
req.best_parent_rate = *prate;
416
+
req.best_parent_hw = parent;
417
417
418
418
ret = divider_ro_determine_rate(hw, &req, table, width, flags, val);
419
419
if (ret)
+221
-65
drivers/clk/clk.c
+221
-65
drivers/clk/clk.c
···
536
536
return now <= rate && now > best;
537
537
}
538
538
539
+
static void clk_core_init_rate_req(struct clk_core * const core,
540
+
struct clk_rate_request *req,
541
+
unsigned long rate);
542
+
543
+
static int clk_core_round_rate_nolock(struct clk_core *core,
544
+
struct clk_rate_request *req);
545
+
546
+
static bool clk_core_has_parent(struct clk_core *core, const struct clk_core *parent)
547
+
{
548
+
struct clk_core *tmp;
549
+
unsigned int i;
550
+
551
+
/* Optimize for the case where the parent is already the parent. */
552
+
if (core->parent == parent)
553
+
return true;
554
+
555
+
for (i = 0; i < core->num_parents; i++) {
556
+
tmp = clk_core_get_parent_by_index(core, i);
557
+
if (!tmp)
558
+
continue;
559
+
560
+
if (tmp == parent)
561
+
return true;
562
+
}
563
+
564
+
return false;
565
+
}
566
+
567
+
static void
568
+
clk_core_forward_rate_req(struct clk_core *core,
569
+
const struct clk_rate_request *old_req,
570
+
struct clk_core *parent,
571
+
struct clk_rate_request *req,
572
+
unsigned long parent_rate)
573
+
{
574
+
if (WARN_ON(!clk_core_has_parent(core, parent)))
575
+
return;
576
+
577
+
clk_core_init_rate_req(parent, req, parent_rate);
578
+
579
+
if (req->min_rate < old_req->min_rate)
580
+
req->min_rate = old_req->min_rate;
581
+
582
+
if (req->max_rate > old_req->max_rate)
583
+
req->max_rate = old_req->max_rate;
584
+
}
585
+
539
586
int clk_mux_determine_rate_flags(struct clk_hw *hw,
540
587
struct clk_rate_request *req,
541
588
unsigned long flags)
···
590
543
struct clk_core *core = hw->core, *parent, *best_parent = NULL;
591
544
int i, num_parents, ret;
592
545
unsigned long best = 0;
593
-
struct clk_rate_request parent_req = *req;
594
546
595
547
/* if NO_REPARENT flag set, pass through to current parent */
596
548
if (core->flags & CLK_SET_RATE_NO_REPARENT) {
597
549
parent = core->parent;
598
550
if (core->flags & CLK_SET_RATE_PARENT) {
599
-
ret = __clk_determine_rate(parent ? parent->hw : NULL,
600
-
&parent_req);
551
+
struct clk_rate_request parent_req;
552
+
553
+
if (!parent) {
554
+
req->rate = 0;
555
+
return 0;
556
+
}
557
+
558
+
clk_core_forward_rate_req(core, req, parent, &parent_req, req->rate);
559
+
ret = clk_core_round_rate_nolock(parent, &parent_req);
601
560
if (ret)
602
561
return ret;
603
562
···
620
567
/* find the parent that can provide the fastest rate <= rate */
621
568
num_parents = core->num_parents;
622
569
for (i = 0; i < num_parents; i++) {
570
+
unsigned long parent_rate;
571
+
623
572
parent = clk_core_get_parent_by_index(core, i);
624
573
if (!parent)
625
574
continue;
626
575
627
576
if (core->flags & CLK_SET_RATE_PARENT) {
628
-
parent_req = *req;
629
-
ret = __clk_determine_rate(parent->hw, &parent_req);
577
+
struct clk_rate_request parent_req;
578
+
579
+
clk_core_forward_rate_req(core, req, parent, &parent_req, req->rate);
580
+
ret = clk_core_round_rate_nolock(parent, &parent_req);
630
581
if (ret)
631
582
continue;
583
+
584
+
parent_rate = parent_req.rate;
632
585
} else {
633
-
parent_req.rate = clk_core_get_rate_nolock(parent);
586
+
parent_rate = clk_core_get_rate_nolock(parent);
634
587
}
635
588
636
-
if (mux_is_better_rate(req->rate, parent_req.rate,
589
+
if (mux_is_better_rate(req->rate, parent_rate,
637
590
best, flags)) {
638
591
best_parent = parent;
639
-
best = parent_req.rate;
592
+
best = parent_rate;
640
593
}
641
594
}
642
595
···
683
624
hlist_for_each_entry(clk_user, &core->clks, clks_node)
684
625
*max_rate = min(*max_rate, clk_user->max_rate);
685
626
}
627
+
628
+
/*
629
+
* clk_hw_get_rate_range() - returns the clock rate range for a hw clk
630
+
* @hw: the hw clk we want to get the range from
631
+
* @min_rate: pointer to the variable that will hold the minimum
632
+
* @max_rate: pointer to the variable that will hold the maximum
633
+
*
634
+
* Fills the @min_rate and @max_rate variables with the minimum and
635
+
* maximum that clock can reach.
636
+
*/
637
+
void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate,
638
+
unsigned long *max_rate)
639
+
{
640
+
clk_core_get_boundaries(hw->core, min_rate, max_rate);
641
+
}
642
+
EXPORT_SYMBOL_GPL(clk_hw_get_rate_range);
686
643
687
644
static bool clk_core_check_boundaries(struct clk_core *core,
688
645
unsigned long min_rate,
···
1415
1340
if (!core)
1416
1341
return 0;
1417
1342
1418
-
req->rate = clamp(req->rate, req->min_rate, req->max_rate);
1343
+
/*
1344
+
* Some clock providers hand-craft their clk_rate_requests and
1345
+
* might not fill min_rate and max_rate.
1346
+
*
1347
+
* If it's the case, clamping the rate is equivalent to setting
1348
+
* the rate to 0 which is bad. Skip the clamping but complain so
1349
+
* that it gets fixed, hopefully.
1350
+
*/
1351
+
if (!req->min_rate && !req->max_rate)
1352
+
pr_warn("%s: %s: clk_rate_request has initialized min or max rate.\n",
1353
+
__func__, core->name);
1354
+
else
1355
+
req->rate = clamp(req->rate, req->min_rate, req->max_rate);
1419
1356
1420
1357
/*
1421
1358
* At this point, core protection will be disabled
···
1454
1367
}
1455
1368
1456
1369
static void clk_core_init_rate_req(struct clk_core * const core,
1457
-
struct clk_rate_request *req)
1370
+
struct clk_rate_request *req,
1371
+
unsigned long rate)
1458
1372
{
1459
1373
struct clk_core *parent;
1460
1374
1461
1375
if (WARN_ON(!core || !req))
1462
1376
return;
1377
+
1378
+
memset(req, 0, sizeof(*req));
1379
+
1380
+
req->rate = rate;
1381
+
clk_core_get_boundaries(core, &req->min_rate, &req->max_rate);
1463
1382
1464
1383
parent = core->parent;
1465
1384
if (parent) {
···
1477
1384
}
1478
1385
}
1479
1386
1387
+
/**
1388
+
* clk_hw_init_rate_request - Initializes a clk_rate_request
1389
+
* @hw: the clk for which we want to submit a rate request
1390
+
* @req: the clk_rate_request structure we want to initialise
1391
+
* @rate: the rate which is to be requested
1392
+
*
1393
+
* Initializes a clk_rate_request structure to submit to
1394
+
* __clk_determine_rate() or similar functions.
1395
+
*/
1396
+
void clk_hw_init_rate_request(const struct clk_hw *hw,
1397
+
struct clk_rate_request *req,
1398
+
unsigned long rate)
1399
+
{
1400
+
if (WARN_ON(!hw || !req))
1401
+
return;
1402
+
1403
+
clk_core_init_rate_req(hw->core, req, rate);
1404
+
}
1405
+
EXPORT_SYMBOL_GPL(clk_hw_init_rate_request);
1406
+
1407
+
/**
1408
+
* clk_hw_forward_rate_request - Forwards a clk_rate_request to a clock's parent
1409
+
* @hw: the original clock that got the rate request
1410
+
* @old_req: the original clk_rate_request structure we want to forward
1411
+
* @parent: the clk we want to forward @old_req to
1412
+
* @req: the clk_rate_request structure we want to initialise
1413
+
* @parent_rate: The rate which is to be requested to @parent
1414
+
*
1415
+
* Initializes a clk_rate_request structure to submit to a clock parent
1416
+
* in __clk_determine_rate() or similar functions.
1417
+
*/
1418
+
void clk_hw_forward_rate_request(const struct clk_hw *hw,
1419
+
const struct clk_rate_request *old_req,
1420
+
const struct clk_hw *parent,
1421
+
struct clk_rate_request *req,
1422
+
unsigned long parent_rate)
1423
+
{
1424
+
if (WARN_ON(!hw || !old_req || !parent || !req))
1425
+
return;
1426
+
1427
+
clk_core_forward_rate_req(hw->core, old_req,
1428
+
parent->core, req,
1429
+
parent_rate);
1430
+
}
1431
+
1480
1432
static bool clk_core_can_round(struct clk_core * const core)
1481
1433
{
1482
1434
return core->ops->determine_rate || core->ops->round_rate;
···
1530
1392
static int clk_core_round_rate_nolock(struct clk_core *core,
1531
1393
struct clk_rate_request *req)
1532
1394
{
1395
+
int ret;
1396
+
1533
1397
lockdep_assert_held(&prepare_lock);
1534
1398
1535
1399
if (!core) {
···
1539
1399
return 0;
1540
1400
}
1541
1401
1542
-
clk_core_init_rate_req(core, req);
1543
-
1544
1402
if (clk_core_can_round(core))
1545
1403
return clk_core_determine_round_nolock(core, req);
1546
-
else if (core->flags & CLK_SET_RATE_PARENT)
1547
-
return clk_core_round_rate_nolock(core->parent, req);
1404
+
1405
+
if (core->flags & CLK_SET_RATE_PARENT) {
1406
+
struct clk_rate_request parent_req;
1407
+
1408
+
clk_core_forward_rate_req(core, req, core->parent, &parent_req, req->rate);
1409
+
ret = clk_core_round_rate_nolock(core->parent, &parent_req);
1410
+
if (ret)
1411
+
return ret;
1412
+
1413
+
req->best_parent_rate = parent_req.rate;
1414
+
req->rate = parent_req.rate;
1415
+
1416
+
return 0;
1417
+
}
1548
1418
1549
1419
req->rate = core->rate;
1550
1420
return 0;
···
1598
1448
int ret;
1599
1449
struct clk_rate_request req;
1600
1450
1601
-
clk_core_get_boundaries(hw->core, &req.min_rate, &req.max_rate);
1602
-
req.rate = rate;
1451
+
clk_core_init_rate_req(hw->core, &req, rate);
1603
1452
1604
1453
ret = clk_core_round_rate_nolock(hw->core, &req);
1605
1454
if (ret)
···
1630
1481
if (clk->exclusive_count)
1631
1482
clk_core_rate_unprotect(clk->core);
1632
1483
1633
-
clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate);
1634
-
req.rate = rate;
1484
+
clk_core_init_rate_req(clk->core, &req, rate);
1635
1485
1636
1486
ret = clk_core_round_rate_nolock(clk->core, &req);
1637
1487
···
1759
1611
/**
1760
1612
* __clk_recalc_rates
1761
1613
* @core: first clk in the subtree
1614
+
* @update_req: Whether req_rate should be updated with the new rate
1762
1615
* @msg: notification type (see include/linux/clk.h)
1763
1616
*
1764
1617
* Walks the subtree of clks starting with clk and recalculates rates as it
···
1769
1620
* clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
1770
1621
* if necessary.
1771
1622
*/
1772
-
static void __clk_recalc_rates(struct clk_core *core, unsigned long msg)
1623
+
static void __clk_recalc_rates(struct clk_core *core, bool update_req,
1624
+
unsigned long msg)
1773
1625
{
1774
1626
unsigned long old_rate;
1775
1627
unsigned long parent_rate = 0;
···
1784
1634
parent_rate = core->parent->rate;
1785
1635
1786
1636
core->rate = clk_recalc(core, parent_rate);
1637
+
if (update_req)
1638
+
core->req_rate = core->rate;
1787
1639
1788
1640
/*
1789
1641
* ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
···
1795
1643
__clk_notify(core, msg, old_rate, core->rate);
1796
1644
1797
1645
hlist_for_each_entry(child, &core->children, child_node)
1798
-
__clk_recalc_rates(child, msg);
1646
+
__clk_recalc_rates(child, update_req, msg);
1799
1647
}
1800
1648
1801
1649
static unsigned long clk_core_get_rate_recalc(struct clk_core *core)
1802
1650
{
1803
1651
if (core && (core->flags & CLK_GET_RATE_NOCACHE))
1804
-
__clk_recalc_rates(core, 0);
1652
+
__clk_recalc_rates(core, false, 0);
1805
1653
1806
1654
return clk_core_get_rate_nolock(core);
1807
1655
}
···
1811
1659
* @clk: the clk whose rate is being returned
1812
1660
*
1813
1661
* Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1814
-
* is set, which means a recalc_rate will be issued.
1815
-
* If clk is NULL then returns 0.
1662
+
* is set, which means a recalc_rate will be issued. Can be called regardless of
1663
+
* the clock enabledness. If clk is NULL, or if an error occurred, then returns
1664
+
* 0.
1816
1665
*/
1817
1666
unsigned long clk_get_rate(struct clk *clk)
1818
1667
{
···
2017
1864
flags = clk_enable_lock();
2018
1865
clk_reparent(core, old_parent);
2019
1866
clk_enable_unlock(flags);
1867
+
2020
1868
__clk_set_parent_after(core, old_parent, parent);
2021
1869
2022
1870
return ret;
···
2123
1969
if (clk_core_can_round(core)) {
2124
1970
struct clk_rate_request req;
2125
1971
2126
-
req.rate = rate;
2127
-
req.min_rate = min_rate;
2128
-
req.max_rate = max_rate;
2129
-
2130
-
clk_core_init_rate_req(core, &req);
1972
+
clk_core_init_rate_req(core, &req, rate);
2131
1973
2132
1974
ret = clk_core_determine_round_nolock(core, &req);
2133
1975
if (ret < 0)
···
2322
2172
if (cnt < 0)
2323
2173
return cnt;
2324
2174
2325
-
clk_core_get_boundaries(core, &req.min_rate, &req.max_rate);
2326
-
req.rate = req_rate;
2175
+
clk_core_init_rate_req(core, &req, req_rate);
2327
2176
2328
2177
ret = clk_core_round_rate_nolock(core, &req);
2329
2178
···
2473
2324
}
2474
2325
EXPORT_SYMBOL_GPL(clk_set_rate_exclusive);
2475
2326
2476
-
/**
2477
-
* clk_set_rate_range - set a rate range for a clock source
2478
-
* @clk: clock source
2479
-
* @min: desired minimum clock rate in Hz, inclusive
2480
-
* @max: desired maximum clock rate in Hz, inclusive
2481
-
*
2482
-
* Returns success (0) or negative errno.
2483
-
*/
2484
-
int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
2327
+
static int clk_set_rate_range_nolock(struct clk *clk,
2328
+
unsigned long min,
2329
+
unsigned long max)
2485
2330
{
2486
2331
int ret = 0;
2487
2332
unsigned long old_min, old_max, rate;
2333
+
2334
+
lockdep_assert_held(&prepare_lock);
2488
2335
2489
2336
if (!clk)
2490
2337
return 0;
···
2493
2348
min, max);
2494
2349
return -EINVAL;
2495
2350
}
2496
-
2497
-
clk_prepare_lock();
2498
2351
2499
2352
if (clk->exclusive_count)
2500
2353
clk_core_rate_unprotect(clk->core);
···
2507
2364
ret = -EINVAL;
2508
2365
goto out;
2509
2366
}
2367
+
2368
+
rate = clk->core->req_rate;
2369
+
if (clk->core->flags & CLK_GET_RATE_NOCACHE)
2370
+
rate = clk_core_get_rate_recalc(clk->core);
2510
2371
2511
2372
/*
2512
2373
* Since the boundaries have been changed, let's give the
···
2529
2382
* - the determine_rate() callback does not really check for
2530
2383
* this corner case when determining the rate
2531
2384
*/
2532
-
rate = clamp(clk->core->req_rate, min, max);
2385
+
rate = clamp(rate, min, max);
2533
2386
ret = clk_core_set_rate_nolock(clk->core, rate);
2534
2387
if (ret) {
2535
2388
/* rollback the changes */
···
2540
2393
out:
2541
2394
if (clk->exclusive_count)
2542
2395
clk_core_rate_protect(clk->core);
2396
+
2397
+
return ret;
2398
+
}
2399
+
2400
+
/**
2401
+
* clk_set_rate_range - set a rate range for a clock source
2402
+
* @clk: clock source
2403
+
* @min: desired minimum clock rate in Hz, inclusive
2404
+
* @max: desired maximum clock rate in Hz, inclusive
2405
+
*
2406
+
* Return: 0 for success or negative errno on failure.
2407
+
*/
2408
+
int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
2409
+
{
2410
+
int ret;
2411
+
2412
+
if (!clk)
2413
+
return 0;
2414
+
2415
+
clk_prepare_lock();
2416
+
2417
+
ret = clk_set_rate_range_nolock(clk, min, max);
2543
2418
2544
2419
clk_prepare_unlock();
2545
2420
···
2642
2473
{
2643
2474
clk_reparent(core, new_parent);
2644
2475
__clk_recalc_accuracies(core);
2645
-
__clk_recalc_rates(core, POST_RATE_CHANGE);
2476
+
__clk_recalc_rates(core, true, POST_RATE_CHANGE);
2646
2477
}
2647
2478
2648
2479
void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
···
2663
2494
*
2664
2495
* Returns true if @parent is a possible parent for @clk, false otherwise.
2665
2496
*/
2666
-
bool clk_has_parent(struct clk *clk, struct clk *parent)
2497
+
bool clk_has_parent(const struct clk *clk, const struct clk *parent)
2667
2498
{
2668
-
struct clk_core *core, *parent_core;
2669
-
int i;
2670
-
2671
2499
/* NULL clocks should be nops, so return success if either is NULL. */
2672
2500
if (!clk || !parent)
2673
2501
return true;
2674
2502
2675
-
core = clk->core;
2676
-
parent_core = parent->core;
2677
-
2678
-
/* Optimize for the case where the parent is already the parent. */
2679
-
if (core->parent == parent_core)
2680
-
return true;
2681
-
2682
-
for (i = 0; i < core->num_parents; i++)
2683
-
if (!strcmp(core->parents[i].name, parent_core->name))
2684
-
return true;
2685
-
2686
-
return false;
2503
+
return clk_core_has_parent(clk->core, parent->core);
2687
2504
}
2688
2505
EXPORT_SYMBOL_GPL(clk_has_parent);
2689
2506
···
2726
2571
2727
2572
/* propagate rate an accuracy recalculation accordingly */
2728
2573
if (ret) {
2729
-
__clk_recalc_rates(core, ABORT_RATE_CHANGE);
2574
+
__clk_recalc_rates(core, true, ABORT_RATE_CHANGE);
2730
2575
} else {
2731
-
__clk_recalc_rates(core, POST_RATE_CHANGE);
2576
+
__clk_recalc_rates(core, true, POST_RATE_CHANGE);
2732
2577
__clk_recalc_accuracies(core);
2733
2578
}
2734
2579
···
3625
3470
__clk_set_parent_before(orphan, parent);
3626
3471
__clk_set_parent_after(orphan, parent, NULL);
3627
3472
__clk_recalc_accuracies(orphan);
3628
-
__clk_recalc_rates(orphan, 0);
3473
+
__clk_recalc_rates(orphan, true, 0);
3629
3474
3630
3475
/*
3631
3476
* __clk_init_parent() will set the initial req_rate to
···
4501
4346
}
4502
4347
4503
4348
hlist_del(&clk->clks_node);
4504
-
if (clk->min_rate > clk->core->req_rate ||
4505
-
clk->max_rate < clk->core->req_rate)
4506
-
clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
4349
+
4350
+
/* If we had any boundaries on that clock, let's drop them. */
4351
+
if (clk->min_rate > 0 || clk->max_rate < ULONG_MAX)
4352
+
clk_set_rate_range_nolock(clk, 0, ULONG_MAX);
4507
4353
4508
4354
owner = clk->core->owner;
4509
4355
kref_put(&clk->core->ref, __clk_release);
+1540
-29
drivers/clk/clk_test.c
+1540
-29
drivers/clk/clk_test.c
···
108
108
.get_parent = clk_dummy_single_get_parent,
109
109
};
110
110
111
+
struct clk_multiple_parent_ctx {
112
+
struct clk_dummy_context parents_ctx[2];
113
+
struct clk_hw hw;
114
+
u8 current_parent;
115
+
};
116
+
117
+
static int clk_multiple_parents_mux_set_parent(struct clk_hw *hw, u8 index)
118
+
{
119
+
struct clk_multiple_parent_ctx *ctx =
120
+
container_of(hw, struct clk_multiple_parent_ctx, hw);
121
+
122
+
if (index >= clk_hw_get_num_parents(hw))
123
+
return -EINVAL;
124
+
125
+
ctx->current_parent = index;
126
+
127
+
return 0;
128
+
}
129
+
130
+
static u8 clk_multiple_parents_mux_get_parent(struct clk_hw *hw)
131
+
{
132
+
struct clk_multiple_parent_ctx *ctx =
133
+
container_of(hw, struct clk_multiple_parent_ctx, hw);
134
+
135
+
return ctx->current_parent;
136
+
}
137
+
138
+
static const struct clk_ops clk_multiple_parents_mux_ops = {
139
+
.get_parent = clk_multiple_parents_mux_get_parent,
140
+
.set_parent = clk_multiple_parents_mux_set_parent,
141
+
.determine_rate = __clk_mux_determine_rate_closest,
142
+
};
143
+
111
144
static int clk_test_init_with_ops(struct kunit *test, const struct clk_ops *ops)
112
145
{
113
146
struct clk_dummy_context *ctx;
···
193
160
{
194
161
struct clk_dummy_context *ctx = test->priv;
195
162
struct clk_hw *hw = &ctx->hw;
196
-
struct clk *clk = hw->clk;
163
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
197
164
unsigned long rate;
198
165
199
166
rate = clk_get_rate(clk);
200
167
KUNIT_ASSERT_GT(test, rate, 0);
201
168
KUNIT_EXPECT_EQ(test, rate, ctx->rate);
169
+
170
+
clk_put(clk);
202
171
}
203
172
204
173
/*
···
214
179
{
215
180
struct clk_dummy_context *ctx = test->priv;
216
181
struct clk_hw *hw = &ctx->hw;
217
-
struct clk *clk = hw->clk;
182
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
218
183
unsigned long rate;
219
184
220
185
KUNIT_ASSERT_EQ(test,
···
224
189
rate = clk_get_rate(clk);
225
190
KUNIT_ASSERT_GT(test, rate, 0);
226
191
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
192
+
193
+
clk_put(clk);
227
194
}
228
195
229
196
/*
···
239
202
{
240
203
struct clk_dummy_context *ctx = test->priv;
241
204
struct clk_hw *hw = &ctx->hw;
242
-
struct clk *clk = hw->clk;
205
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
243
206
unsigned long rate;
244
207
245
208
KUNIT_ASSERT_EQ(test,
···
253
216
rate = clk_get_rate(clk);
254
217
KUNIT_ASSERT_GT(test, rate, 0);
255
218
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2);
219
+
220
+
clk_put(clk);
256
221
}
257
222
258
223
/*
···
265
226
{
266
227
struct clk_dummy_context *ctx = test->priv;
267
228
struct clk_hw *hw = &ctx->hw;
268
-
struct clk *clk = hw->clk;
229
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
269
230
unsigned long rounded_rate, set_rate;
270
231
271
232
rounded_rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_1);
···
279
240
set_rate = clk_get_rate(clk);
280
241
KUNIT_ASSERT_GT(test, set_rate, 0);
281
242
KUNIT_EXPECT_EQ(test, rounded_rate, set_rate);
243
+
244
+
clk_put(clk);
282
245
}
283
246
284
247
static struct kunit_case clk_test_cases[] = {
···
291
250
{}
292
251
};
293
252
253
+
/*
254
+
* Test suite for a basic rate clock, without any parent.
255
+
*
256
+
* These tests exercise the rate API with simple scenarios
257
+
*/
294
258
static struct kunit_suite clk_test_suite = {
295
259
.name = "clk-test",
296
260
.init = clk_test_init,
···
303
257
.test_cases = clk_test_cases,
304
258
};
305
259
260
+
static int clk_uncached_test_init(struct kunit *test)
261
+
{
262
+
struct clk_dummy_context *ctx;
263
+
int ret;
264
+
265
+
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
266
+
if (!ctx)
267
+
return -ENOMEM;
268
+
test->priv = ctx;
269
+
270
+
ctx->rate = DUMMY_CLOCK_INIT_RATE;
271
+
ctx->hw.init = CLK_HW_INIT_NO_PARENT("test-clk",
272
+
&clk_dummy_rate_ops,
273
+
CLK_GET_RATE_NOCACHE);
274
+
275
+
ret = clk_hw_register(NULL, &ctx->hw);
276
+
if (ret)
277
+
return ret;
278
+
279
+
return 0;
280
+
}
281
+
282
+
/*
283
+
* Test that for an uncached clock, the clock framework doesn't cache
284
+
* the rate and clk_get_rate() will return the underlying clock rate
285
+
* even if it changed.
286
+
*/
287
+
static void clk_test_uncached_get_rate(struct kunit *test)
288
+
{
289
+
struct clk_dummy_context *ctx = test->priv;
290
+
struct clk_hw *hw = &ctx->hw;
291
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
292
+
unsigned long rate;
293
+
294
+
rate = clk_get_rate(clk);
295
+
KUNIT_ASSERT_GT(test, rate, 0);
296
+
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_INIT_RATE);
297
+
298
+
/* We change the rate behind the clock framework's back */
299
+
ctx->rate = DUMMY_CLOCK_RATE_1;
300
+
rate = clk_get_rate(clk);
301
+
KUNIT_ASSERT_GT(test, rate, 0);
302
+
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
303
+
304
+
clk_put(clk);
305
+
}
306
+
307
+
/*
308
+
* Test that for an uncached clock, clk_set_rate_range() will work
309
+
* properly if the rate hasn't changed.
310
+
*/
311
+
static void clk_test_uncached_set_range(struct kunit *test)
312
+
{
313
+
struct clk_dummy_context *ctx = test->priv;
314
+
struct clk_hw *hw = &ctx->hw;
315
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
316
+
unsigned long rate;
317
+
318
+
KUNIT_ASSERT_EQ(test,
319
+
clk_set_rate_range(clk,
320
+
DUMMY_CLOCK_RATE_1,
321
+
DUMMY_CLOCK_RATE_2),
322
+
0);
323
+
324
+
rate = clk_get_rate(clk);
325
+
KUNIT_ASSERT_GT(test, rate, 0);
326
+
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1);
327
+
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2);
328
+
329
+
clk_put(clk);
330
+
}
331
+
332
+
/*
333
+
* Test that for an uncached clock, clk_set_rate_range() will work
334
+
* properly if the rate has changed in hardware.
335
+
*
336
+
* In this case, it means that if the rate wasn't initially in the range
337
+
* we're trying to set, but got changed at some point into the range
338
+
* without the kernel knowing about it, its rate shouldn't be affected.
339
+
*/
340
+
static void clk_test_uncached_updated_rate_set_range(struct kunit *test)
341
+
{
342
+
struct clk_dummy_context *ctx = test->priv;
343
+
struct clk_hw *hw = &ctx->hw;
344
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
345
+
unsigned long rate;
346
+
347
+
/* We change the rate behind the clock framework's back */
348
+
ctx->rate = DUMMY_CLOCK_RATE_1 + 1000;
349
+
KUNIT_ASSERT_EQ(test,
350
+
clk_set_rate_range(clk,
351
+
DUMMY_CLOCK_RATE_1,
352
+
DUMMY_CLOCK_RATE_2),
353
+
0);
354
+
355
+
rate = clk_get_rate(clk);
356
+
KUNIT_ASSERT_GT(test, rate, 0);
357
+
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1 + 1000);
358
+
359
+
clk_put(clk);
360
+
}
361
+
362
+
static struct kunit_case clk_uncached_test_cases[] = {
363
+
KUNIT_CASE(clk_test_uncached_get_rate),
364
+
KUNIT_CASE(clk_test_uncached_set_range),
365
+
KUNIT_CASE(clk_test_uncached_updated_rate_set_range),
366
+
{}
367
+
};
368
+
369
+
/*
370
+
* Test suite for a basic, uncached, rate clock, without any parent.
371
+
*
372
+
* These tests exercise the rate API with simple scenarios
373
+
*/
374
+
static struct kunit_suite clk_uncached_test_suite = {
375
+
.name = "clk-uncached-test",
376
+
.init = clk_uncached_test_init,
377
+
.exit = clk_test_exit,
378
+
.test_cases = clk_uncached_test_cases,
379
+
};
380
+
381
+
static int
382
+
clk_multiple_parents_mux_test_init(struct kunit *test)
383
+
{
384
+
struct clk_multiple_parent_ctx *ctx;
385
+
const char *parents[2] = { "parent-0", "parent-1"};
386
+
int ret;
387
+
388
+
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
389
+
if (!ctx)
390
+
return -ENOMEM;
391
+
test->priv = ctx;
392
+
393
+
ctx->parents_ctx[0].hw.init = CLK_HW_INIT_NO_PARENT("parent-0",
394
+
&clk_dummy_rate_ops,
395
+
0);
396
+
ctx->parents_ctx[0].rate = DUMMY_CLOCK_RATE_1;
397
+
ret = clk_hw_register(NULL, &ctx->parents_ctx[0].hw);
398
+
if (ret)
399
+
return ret;
400
+
401
+
ctx->parents_ctx[1].hw.init = CLK_HW_INIT_NO_PARENT("parent-1",
402
+
&clk_dummy_rate_ops,
403
+
0);
404
+
ctx->parents_ctx[1].rate = DUMMY_CLOCK_RATE_2;
405
+
ret = clk_hw_register(NULL, &ctx->parents_ctx[1].hw);
406
+
if (ret)
407
+
return ret;
408
+
409
+
ctx->current_parent = 0;
410
+
ctx->hw.init = CLK_HW_INIT_PARENTS("test-mux", parents,
411
+
&clk_multiple_parents_mux_ops,
412
+
CLK_SET_RATE_PARENT);
413
+
ret = clk_hw_register(NULL, &ctx->hw);
414
+
if (ret)
415
+
return ret;
416
+
417
+
return 0;
418
+
}
419
+
420
+
static void
421
+
clk_multiple_parents_mux_test_exit(struct kunit *test)
422
+
{
423
+
struct clk_multiple_parent_ctx *ctx = test->priv;
424
+
425
+
clk_hw_unregister(&ctx->hw);
426
+
clk_hw_unregister(&ctx->parents_ctx[0].hw);
427
+
clk_hw_unregister(&ctx->parents_ctx[1].hw);
428
+
}
429
+
430
+
/*
431
+
* Test that for a clock with multiple parents, clk_get_parent()
432
+
* actually returns the current one.
433
+
*/
434
+
static void
435
+
clk_test_multiple_parents_mux_get_parent(struct kunit *test)
436
+
{
437
+
struct clk_multiple_parent_ctx *ctx = test->priv;
438
+
struct clk_hw *hw = &ctx->hw;
439
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
440
+
struct clk *parent = clk_hw_get_clk(&ctx->parents_ctx[0].hw, NULL);
441
+
442
+
KUNIT_EXPECT_TRUE(test, clk_is_match(clk_get_parent(clk), parent));
443
+
444
+
clk_put(parent);
445
+
clk_put(clk);
446
+
}
447
+
448
+
/*
449
+
* Test that for a clock with a multiple parents, clk_has_parent()
450
+
* actually reports all of them as parents.
451
+
*/
452
+
static void
453
+
clk_test_multiple_parents_mux_has_parent(struct kunit *test)
454
+
{
455
+
struct clk_multiple_parent_ctx *ctx = test->priv;
456
+
struct clk_hw *hw = &ctx->hw;
457
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
458
+
struct clk *parent;
459
+
460
+
parent = clk_hw_get_clk(&ctx->parents_ctx[0].hw, NULL);
461
+
KUNIT_EXPECT_TRUE(test, clk_has_parent(clk, parent));
462
+
clk_put(parent);
463
+
464
+
parent = clk_hw_get_clk(&ctx->parents_ctx[1].hw, NULL);
465
+
KUNIT_EXPECT_TRUE(test, clk_has_parent(clk, parent));
466
+
clk_put(parent);
467
+
468
+
clk_put(clk);
469
+
}
470
+
471
+
/*
472
+
* Test that for a clock with a multiple parents, if we set a range on
473
+
* that clock and the parent is changed, its rate after the reparenting
474
+
* is still within the range we asked for.
475
+
*
476
+
* FIXME: clk_set_parent() only does the reparenting but doesn't
477
+
* reevaluate whether the new clock rate is within its boundaries or
478
+
* not.
479
+
*/
480
+
static void
481
+
clk_test_multiple_parents_mux_set_range_set_parent_get_rate(struct kunit *test)
482
+
{
483
+
struct clk_multiple_parent_ctx *ctx = test->priv;
484
+
struct clk_hw *hw = &ctx->hw;
485
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
486
+
struct clk *parent1, *parent2;
487
+
unsigned long rate;
488
+
int ret;
489
+
490
+
kunit_skip(test, "This needs to be fixed in the core.");
491
+
492
+
parent1 = clk_hw_get_clk(&ctx->parents_ctx[0].hw, NULL);
493
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent1);
494
+
KUNIT_ASSERT_TRUE(test, clk_is_match(clk_get_parent(clk), parent1));
495
+
496
+
parent2 = clk_hw_get_clk(&ctx->parents_ctx[1].hw, NULL);
497
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent2);
498
+
499
+
ret = clk_set_rate(parent1, DUMMY_CLOCK_RATE_1);
500
+
KUNIT_ASSERT_EQ(test, ret, 0);
501
+
502
+
ret = clk_set_rate(parent2, DUMMY_CLOCK_RATE_2);
503
+
KUNIT_ASSERT_EQ(test, ret, 0);
504
+
505
+
ret = clk_set_rate_range(clk,
506
+
DUMMY_CLOCK_RATE_1 - 1000,
507
+
DUMMY_CLOCK_RATE_1 + 1000);
508
+
KUNIT_ASSERT_EQ(test, ret, 0);
509
+
510
+
ret = clk_set_parent(clk, parent2);
511
+
KUNIT_ASSERT_EQ(test, ret, 0);
512
+
513
+
rate = clk_get_rate(clk);
514
+
KUNIT_ASSERT_GT(test, rate, 0);
515
+
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1 - 1000);
516
+
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_1 + 1000);
517
+
518
+
clk_put(parent2);
519
+
clk_put(parent1);
520
+
clk_put(clk);
521
+
}
522
+
523
+
static struct kunit_case clk_multiple_parents_mux_test_cases[] = {
524
+
KUNIT_CASE(clk_test_multiple_parents_mux_get_parent),
525
+
KUNIT_CASE(clk_test_multiple_parents_mux_has_parent),
526
+
KUNIT_CASE(clk_test_multiple_parents_mux_set_range_set_parent_get_rate),
527
+
{}
528
+
};
529
+
530
+
/*
531
+
* Test suite for a basic mux clock with two parents, with
532
+
* CLK_SET_RATE_PARENT on the child.
533
+
*
534
+
* These tests exercise the consumer API and check that the state of the
535
+
* child and parents are sane and consistent.
536
+
*/
537
+
static struct kunit_suite
538
+
clk_multiple_parents_mux_test_suite = {
539
+
.name = "clk-multiple-parents-mux-test",
540
+
.init = clk_multiple_parents_mux_test_init,
541
+
.exit = clk_multiple_parents_mux_test_exit,
542
+
.test_cases = clk_multiple_parents_mux_test_cases,
543
+
};
544
+
545
+
static int
546
+
clk_orphan_transparent_multiple_parent_mux_test_init(struct kunit *test)
547
+
{
548
+
struct clk_multiple_parent_ctx *ctx;
549
+
const char *parents[2] = { "missing-parent", "proper-parent"};
550
+
int ret;
551
+
552
+
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
553
+
if (!ctx)
554
+
return -ENOMEM;
555
+
test->priv = ctx;
556
+
557
+
ctx->parents_ctx[1].hw.init = CLK_HW_INIT_NO_PARENT("proper-parent",
558
+
&clk_dummy_rate_ops,
559
+
0);
560
+
ctx->parents_ctx[1].rate = DUMMY_CLOCK_INIT_RATE;
561
+
ret = clk_hw_register(NULL, &ctx->parents_ctx[1].hw);
562
+
if (ret)
563
+
return ret;
564
+
565
+
ctx->hw.init = CLK_HW_INIT_PARENTS("test-orphan-mux", parents,
566
+
&clk_multiple_parents_mux_ops,
567
+
CLK_SET_RATE_PARENT);
568
+
ret = clk_hw_register(NULL, &ctx->hw);
569
+
if (ret)
570
+
return ret;
571
+
572
+
return 0;
573
+
}
574
+
575
+
static void
576
+
clk_orphan_transparent_multiple_parent_mux_test_exit(struct kunit *test)
577
+
{
578
+
struct clk_multiple_parent_ctx *ctx = test->priv;
579
+
580
+
clk_hw_unregister(&ctx->hw);
581
+
clk_hw_unregister(&ctx->parents_ctx[1].hw);
582
+
}
583
+
584
+
/*
585
+
* Test that, for a mux whose current parent hasn't been registered yet and is
586
+
* thus orphan, clk_get_parent() will return NULL.
587
+
*/
588
+
static void
589
+
clk_test_orphan_transparent_multiple_parent_mux_get_parent(struct kunit *test)
590
+
{
591
+
struct clk_multiple_parent_ctx *ctx = test->priv;
592
+
struct clk_hw *hw = &ctx->hw;
593
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
594
+
595
+
KUNIT_EXPECT_PTR_EQ(test, clk_get_parent(clk), NULL);
596
+
597
+
clk_put(clk);
598
+
}
599
+
600
+
/*
601
+
* Test that, for a mux whose current parent hasn't been registered yet,
602
+
* calling clk_set_parent() to a valid parent will properly update the
603
+
* mux parent and its orphan status.
604
+
*/
605
+
static void
606
+
clk_test_orphan_transparent_multiple_parent_mux_set_parent(struct kunit *test)
607
+
{
608
+
struct clk_multiple_parent_ctx *ctx = test->priv;
609
+
struct clk_hw *hw = &ctx->hw;
610
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
611
+
struct clk *parent, *new_parent;
612
+
int ret;
613
+
614
+
parent = clk_hw_get_clk(&ctx->parents_ctx[1].hw, NULL);
615
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent);
616
+
617
+
ret = clk_set_parent(clk, parent);
618
+
KUNIT_ASSERT_EQ(test, ret, 0);
619
+
620
+
new_parent = clk_get_parent(clk);
621
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent);
622
+
KUNIT_EXPECT_TRUE(test, clk_is_match(parent, new_parent));
623
+
624
+
clk_put(parent);
625
+
clk_put(clk);
626
+
}
627
+
628
+
/*
629
+
* Test that, for a mux that started orphan but got switched to a valid
630
+
* parent, calling clk_drop_range() on the mux won't affect the parent
631
+
* rate.
632
+
*/
633
+
static void
634
+
clk_test_orphan_transparent_multiple_parent_mux_set_parent_drop_range(struct kunit *test)
635
+
{
636
+
struct clk_multiple_parent_ctx *ctx = test->priv;
637
+
struct clk_hw *hw = &ctx->hw;
638
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
639
+
struct clk *parent;
640
+
unsigned long parent_rate, new_parent_rate;
641
+
int ret;
642
+
643
+
parent = clk_hw_get_clk(&ctx->parents_ctx[1].hw, NULL);
644
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent);
645
+
646
+
parent_rate = clk_get_rate(parent);
647
+
KUNIT_ASSERT_GT(test, parent_rate, 0);
648
+
649
+
ret = clk_set_parent(clk, parent);
650
+
KUNIT_ASSERT_EQ(test, ret, 0);
651
+
652
+
ret = clk_drop_range(clk);
653
+
KUNIT_ASSERT_EQ(test, ret, 0);
654
+
655
+
new_parent_rate = clk_get_rate(clk);
656
+
KUNIT_ASSERT_GT(test, new_parent_rate, 0);
657
+
KUNIT_EXPECT_EQ(test, parent_rate, new_parent_rate);
658
+
659
+
clk_put(parent);
660
+
clk_put(clk);
661
+
}
662
+
663
+
/*
664
+
* Test that, for a mux that started orphan but got switched to a valid
665
+
* parent, the rate of the mux and its new parent are consistent.
666
+
*/
667
+
static void
668
+
clk_test_orphan_transparent_multiple_parent_mux_set_parent_get_rate(struct kunit *test)
669
+
{
670
+
struct clk_multiple_parent_ctx *ctx = test->priv;
671
+
struct clk_hw *hw = &ctx->hw;
672
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
673
+
struct clk *parent;
674
+
unsigned long parent_rate, rate;
675
+
int ret;
676
+
677
+
parent = clk_hw_get_clk(&ctx->parents_ctx[1].hw, NULL);
678
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent);
679
+
680
+
parent_rate = clk_get_rate(parent);
681
+
KUNIT_ASSERT_GT(test, parent_rate, 0);
682
+
683
+
ret = clk_set_parent(clk, parent);
684
+
KUNIT_ASSERT_EQ(test, ret, 0);
685
+
686
+
rate = clk_get_rate(clk);
687
+
KUNIT_ASSERT_GT(test, rate, 0);
688
+
KUNIT_EXPECT_EQ(test, parent_rate, rate);
689
+
690
+
clk_put(parent);
691
+
clk_put(clk);
692
+
}
693
+
694
+
/*
695
+
* Test that, for a mux that started orphan but got switched to a valid
696
+
* parent, calling clk_put() on the mux won't affect the parent rate.
697
+
*/
698
+
static void
699
+
clk_test_orphan_transparent_multiple_parent_mux_set_parent_put(struct kunit *test)
700
+
{
701
+
struct clk_multiple_parent_ctx *ctx = test->priv;
702
+
struct clk *clk, *parent;
703
+
unsigned long parent_rate, new_parent_rate;
704
+
int ret;
705
+
706
+
parent = clk_hw_get_clk(&ctx->parents_ctx[1].hw, NULL);
707
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent);
708
+
709
+
clk = clk_hw_get_clk(&ctx->hw, NULL);
710
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, clk);
711
+
712
+
parent_rate = clk_get_rate(parent);
713
+
KUNIT_ASSERT_GT(test, parent_rate, 0);
714
+
715
+
ret = clk_set_parent(clk, parent);
716
+
KUNIT_ASSERT_EQ(test, ret, 0);
717
+
718
+
clk_put(clk);
719
+
720
+
new_parent_rate = clk_get_rate(parent);
721
+
KUNIT_ASSERT_GT(test, new_parent_rate, 0);
722
+
KUNIT_EXPECT_EQ(test, parent_rate, new_parent_rate);
723
+
724
+
clk_put(parent);
725
+
}
726
+
727
+
/*
728
+
* Test that, for a mux that started orphan but got switched to a valid
729
+
* parent, calling clk_set_rate_range() will affect the parent state if
730
+
* its rate is out of range.
731
+
*/
732
+
static void
733
+
clk_test_orphan_transparent_multiple_parent_mux_set_parent_set_range_modified(struct kunit *test)
734
+
{
735
+
struct clk_multiple_parent_ctx *ctx = test->priv;
736
+
struct clk_hw *hw = &ctx->hw;
737
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
738
+
struct clk *parent;
739
+
unsigned long rate;
740
+
int ret;
741
+
742
+
parent = clk_hw_get_clk(&ctx->parents_ctx[1].hw, NULL);
743
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent);
744
+
745
+
ret = clk_set_parent(clk, parent);
746
+
KUNIT_ASSERT_EQ(test, ret, 0);
747
+
748
+
ret = clk_set_rate_range(clk, DUMMY_CLOCK_RATE_1, DUMMY_CLOCK_RATE_2);
749
+
KUNIT_ASSERT_EQ(test, ret, 0);
750
+
751
+
rate = clk_get_rate(clk);
752
+
KUNIT_ASSERT_GT(test, rate, 0);
753
+
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1);
754
+
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2);
755
+
756
+
clk_put(parent);
757
+
clk_put(clk);
758
+
}
759
+
760
+
/*
761
+
* Test that, for a mux that started orphan but got switched to a valid
762
+
* parent, calling clk_set_rate_range() won't affect the parent state if
763
+
* its rate is within range.
764
+
*/
765
+
static void
766
+
clk_test_orphan_transparent_multiple_parent_mux_set_parent_set_range_untouched(struct kunit *test)
767
+
{
768
+
struct clk_multiple_parent_ctx *ctx = test->priv;
769
+
struct clk_hw *hw = &ctx->hw;
770
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
771
+
struct clk *parent;
772
+
unsigned long parent_rate, new_parent_rate;
773
+
int ret;
774
+
775
+
parent = clk_hw_get_clk(&ctx->parents_ctx[1].hw, NULL);
776
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent);
777
+
778
+
parent_rate = clk_get_rate(parent);
779
+
KUNIT_ASSERT_GT(test, parent_rate, 0);
780
+
781
+
ret = clk_set_parent(clk, parent);
782
+
KUNIT_ASSERT_EQ(test, ret, 0);
783
+
784
+
ret = clk_set_rate_range(clk,
785
+
DUMMY_CLOCK_INIT_RATE - 1000,
786
+
DUMMY_CLOCK_INIT_RATE + 1000);
787
+
KUNIT_ASSERT_EQ(test, ret, 0);
788
+
789
+
new_parent_rate = clk_get_rate(parent);
790
+
KUNIT_ASSERT_GT(test, new_parent_rate, 0);
791
+
KUNIT_EXPECT_EQ(test, parent_rate, new_parent_rate);
792
+
793
+
clk_put(parent);
794
+
clk_put(clk);
795
+
}
796
+
797
+
/*
798
+
* Test that, for a mux whose current parent hasn't been registered yet,
799
+
* calling clk_set_rate_range() will succeed, and will be taken into
800
+
* account when rounding a rate.
801
+
*/
802
+
static void
803
+
clk_test_orphan_transparent_multiple_parent_mux_set_range_round_rate(struct kunit *test)
804
+
{
805
+
struct clk_multiple_parent_ctx *ctx = test->priv;
806
+
struct clk_hw *hw = &ctx->hw;
807
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
808
+
unsigned long rate;
809
+
int ret;
810
+
811
+
ret = clk_set_rate_range(clk, DUMMY_CLOCK_RATE_1, DUMMY_CLOCK_RATE_2);
812
+
KUNIT_ASSERT_EQ(test, ret, 0);
813
+
814
+
rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_1 - 1000);
815
+
KUNIT_ASSERT_GT(test, rate, 0);
816
+
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1);
817
+
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2);
818
+
819
+
clk_put(clk);
820
+
}
821
+
822
+
/*
823
+
* Test that, for a mux that started orphan, was assigned and rate and
824
+
* then got switched to a valid parent, its rate is eventually within
825
+
* range.
826
+
*
827
+
* FIXME: Even though we update the rate as part of clk_set_parent(), we
828
+
* don't evaluate whether that new rate is within range and needs to be
829
+
* adjusted.
830
+
*/
831
+
static void
832
+
clk_test_orphan_transparent_multiple_parent_mux_set_range_set_parent_get_rate(struct kunit *test)
833
+
{
834
+
struct clk_multiple_parent_ctx *ctx = test->priv;
835
+
struct clk_hw *hw = &ctx->hw;
836
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
837
+
struct clk *parent;
838
+
unsigned long rate;
839
+
int ret;
840
+
841
+
kunit_skip(test, "This needs to be fixed in the core.");
842
+
843
+
clk_hw_set_rate_range(hw, DUMMY_CLOCK_RATE_1, DUMMY_CLOCK_RATE_2);
844
+
845
+
parent = clk_hw_get_clk(&ctx->parents_ctx[1].hw, NULL);
846
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent);
847
+
848
+
ret = clk_set_parent(clk, parent);
849
+
KUNIT_ASSERT_EQ(test, ret, 0);
850
+
851
+
rate = clk_get_rate(clk);
852
+
KUNIT_ASSERT_GT(test, rate, 0);
853
+
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1);
854
+
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2);
855
+
856
+
clk_put(parent);
857
+
clk_put(clk);
858
+
}
859
+
860
+
static struct kunit_case clk_orphan_transparent_multiple_parent_mux_test_cases[] = {
861
+
KUNIT_CASE(clk_test_orphan_transparent_multiple_parent_mux_get_parent),
862
+
KUNIT_CASE(clk_test_orphan_transparent_multiple_parent_mux_set_parent),
863
+
KUNIT_CASE(clk_test_orphan_transparent_multiple_parent_mux_set_parent_drop_range),
864
+
KUNIT_CASE(clk_test_orphan_transparent_multiple_parent_mux_set_parent_get_rate),
865
+
KUNIT_CASE(clk_test_orphan_transparent_multiple_parent_mux_set_parent_put),
866
+
KUNIT_CASE(clk_test_orphan_transparent_multiple_parent_mux_set_parent_set_range_modified),
867
+
KUNIT_CASE(clk_test_orphan_transparent_multiple_parent_mux_set_parent_set_range_untouched),
868
+
KUNIT_CASE(clk_test_orphan_transparent_multiple_parent_mux_set_range_round_rate),
869
+
KUNIT_CASE(clk_test_orphan_transparent_multiple_parent_mux_set_range_set_parent_get_rate),
870
+
{}
871
+
};
872
+
873
+
/*
874
+
* Test suite for a basic mux clock with two parents. The default parent
875
+
* isn't registered, only the second parent is. By default, the clock
876
+
* will thus be orphan.
877
+
*
878
+
* These tests exercise the behaviour of the consumer API when dealing
879
+
* with an orphan clock, and how we deal with the transition to a valid
880
+
* parent.
881
+
*/
882
+
static struct kunit_suite clk_orphan_transparent_multiple_parent_mux_test_suite = {
883
+
.name = "clk-orphan-transparent-multiple-parent-mux-test",
884
+
.init = clk_orphan_transparent_multiple_parent_mux_test_init,
885
+
.exit = clk_orphan_transparent_multiple_parent_mux_test_exit,
886
+
.test_cases = clk_orphan_transparent_multiple_parent_mux_test_cases,
887
+
};
888
+
306
889
struct clk_single_parent_ctx {
307
890
struct clk_dummy_context parent_ctx;
308
891
struct clk_hw hw;
892
+
};
893
+
894
+
static int clk_single_parent_mux_test_init(struct kunit *test)
895
+
{
896
+
struct clk_single_parent_ctx *ctx;
897
+
int ret;
898
+
899
+
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
900
+
if (!ctx)
901
+
return -ENOMEM;
902
+
test->priv = ctx;
903
+
904
+
ctx->parent_ctx.rate = DUMMY_CLOCK_INIT_RATE;
905
+
ctx->parent_ctx.hw.init =
906
+
CLK_HW_INIT_NO_PARENT("parent-clk",
907
+
&clk_dummy_rate_ops,
908
+
0);
909
+
910
+
ret = clk_hw_register(NULL, &ctx->parent_ctx.hw);
911
+
if (ret)
912
+
return ret;
913
+
914
+
ctx->hw.init = CLK_HW_INIT("test-clk", "parent-clk",
915
+
&clk_dummy_single_parent_ops,
916
+
CLK_SET_RATE_PARENT);
917
+
918
+
ret = clk_hw_register(NULL, &ctx->hw);
919
+
if (ret)
920
+
return ret;
921
+
922
+
return 0;
923
+
}
924
+
925
+
static void
926
+
clk_single_parent_mux_test_exit(struct kunit *test)
927
+
{
928
+
struct clk_single_parent_ctx *ctx = test->priv;
929
+
930
+
clk_hw_unregister(&ctx->hw);
931
+
clk_hw_unregister(&ctx->parent_ctx.hw);
932
+
}
933
+
934
+
/*
935
+
* Test that for a clock with a single parent, clk_get_parent() actually
936
+
* returns the parent.
937
+
*/
938
+
static void
939
+
clk_test_single_parent_mux_get_parent(struct kunit *test)
940
+
{
941
+
struct clk_single_parent_ctx *ctx = test->priv;
942
+
struct clk_hw *hw = &ctx->hw;
943
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
944
+
struct clk *parent = clk_hw_get_clk(&ctx->parent_ctx.hw, NULL);
945
+
946
+
KUNIT_EXPECT_TRUE(test, clk_is_match(clk_get_parent(clk), parent));
947
+
948
+
clk_put(parent);
949
+
clk_put(clk);
950
+
}
951
+
952
+
/*
953
+
* Test that for a clock with a single parent, clk_has_parent() actually
954
+
* reports it as a parent.
955
+
*/
956
+
static void
957
+
clk_test_single_parent_mux_has_parent(struct kunit *test)
958
+
{
959
+
struct clk_single_parent_ctx *ctx = test->priv;
960
+
struct clk_hw *hw = &ctx->hw;
961
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
962
+
struct clk *parent = clk_hw_get_clk(&ctx->parent_ctx.hw, NULL);
963
+
964
+
KUNIT_EXPECT_TRUE(test, clk_has_parent(clk, parent));
965
+
966
+
clk_put(parent);
967
+
clk_put(clk);
968
+
}
969
+
970
+
/*
971
+
* Test that for a clock that can't modify its rate and with a single
972
+
* parent, if we set disjoints range on the parent and then the child,
973
+
* the second will return an error.
974
+
*
975
+
* FIXME: clk_set_rate_range() only considers the current clock when
976
+
* evaluating whether ranges are disjoints and not the upstream clocks
977
+
* ranges.
978
+
*/
979
+
static void
980
+
clk_test_single_parent_mux_set_range_disjoint_child_last(struct kunit *test)
981
+
{
982
+
struct clk_single_parent_ctx *ctx = test->priv;
983
+
struct clk_hw *hw = &ctx->hw;
984
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
985
+
struct clk *parent;
986
+
int ret;
987
+
988
+
kunit_skip(test, "This needs to be fixed in the core.");
989
+
990
+
parent = clk_get_parent(clk);
991
+
KUNIT_ASSERT_PTR_NE(test, parent, NULL);
992
+
993
+
ret = clk_set_rate_range(parent, 1000, 2000);
994
+
KUNIT_ASSERT_EQ(test, ret, 0);
995
+
996
+
ret = clk_set_rate_range(clk, 3000, 4000);
997
+
KUNIT_EXPECT_LT(test, ret, 0);
998
+
999
+
clk_put(clk);
1000
+
}
1001
+
1002
+
/*
1003
+
* Test that for a clock that can't modify its rate and with a single
1004
+
* parent, if we set disjoints range on the child and then the parent,
1005
+
* the second will return an error.
1006
+
*
1007
+
* FIXME: clk_set_rate_range() only considers the current clock when
1008
+
* evaluating whether ranges are disjoints and not the downstream clocks
1009
+
* ranges.
1010
+
*/
1011
+
static void
1012
+
clk_test_single_parent_mux_set_range_disjoint_parent_last(struct kunit *test)
1013
+
{
1014
+
struct clk_single_parent_ctx *ctx = test->priv;
1015
+
struct clk_hw *hw = &ctx->hw;
1016
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1017
+
struct clk *parent;
1018
+
int ret;
1019
+
1020
+
kunit_skip(test, "This needs to be fixed in the core.");
1021
+
1022
+
parent = clk_get_parent(clk);
1023
+
KUNIT_ASSERT_PTR_NE(test, parent, NULL);
1024
+
1025
+
ret = clk_set_rate_range(clk, 1000, 2000);
1026
+
KUNIT_ASSERT_EQ(test, ret, 0);
1027
+
1028
+
ret = clk_set_rate_range(parent, 3000, 4000);
1029
+
KUNIT_EXPECT_LT(test, ret, 0);
1030
+
1031
+
clk_put(clk);
1032
+
}
1033
+
1034
+
/*
1035
+
* Test that for a clock that can't modify its rate and with a single
1036
+
* parent, if we set a range on the parent and then call
1037
+
* clk_round_rate(), the boundaries of the parent are taken into
1038
+
* account.
1039
+
*/
1040
+
static void
1041
+
clk_test_single_parent_mux_set_range_round_rate_parent_only(struct kunit *test)
1042
+
{
1043
+
struct clk_single_parent_ctx *ctx = test->priv;
1044
+
struct clk_hw *hw = &ctx->hw;
1045
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1046
+
struct clk *parent;
1047
+
unsigned long rate;
1048
+
int ret;
1049
+
1050
+
parent = clk_get_parent(clk);
1051
+
KUNIT_ASSERT_PTR_NE(test, parent, NULL);
1052
+
1053
+
ret = clk_set_rate_range(parent, DUMMY_CLOCK_RATE_1, DUMMY_CLOCK_RATE_2);
1054
+
KUNIT_ASSERT_EQ(test, ret, 0);
1055
+
1056
+
rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_1 - 1000);
1057
+
KUNIT_ASSERT_GT(test, rate, 0);
1058
+
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1);
1059
+
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2);
1060
+
1061
+
clk_put(clk);
1062
+
}
1063
+
1064
+
/*
1065
+
* Test that for a clock that can't modify its rate and with a single
1066
+
* parent, if we set a range on the parent and a more restrictive one on
1067
+
* the child, and then call clk_round_rate(), the boundaries of the
1068
+
* two clocks are taken into account.
1069
+
*/
1070
+
static void
1071
+
clk_test_single_parent_mux_set_range_round_rate_child_smaller(struct kunit *test)
1072
+
{
1073
+
struct clk_single_parent_ctx *ctx = test->priv;
1074
+
struct clk_hw *hw = &ctx->hw;
1075
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1076
+
struct clk *parent;
1077
+
unsigned long rate;
1078
+
int ret;
1079
+
1080
+
parent = clk_get_parent(clk);
1081
+
KUNIT_ASSERT_PTR_NE(test, parent, NULL);
1082
+
1083
+
ret = clk_set_rate_range(parent, DUMMY_CLOCK_RATE_1, DUMMY_CLOCK_RATE_2);
1084
+
KUNIT_ASSERT_EQ(test, ret, 0);
1085
+
1086
+
ret = clk_set_rate_range(clk, DUMMY_CLOCK_RATE_1 + 1000, DUMMY_CLOCK_RATE_2 - 1000);
1087
+
KUNIT_ASSERT_EQ(test, ret, 0);
1088
+
1089
+
rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_1 - 1000);
1090
+
KUNIT_ASSERT_GT(test, rate, 0);
1091
+
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1 + 1000);
1092
+
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2 - 1000);
1093
+
1094
+
rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_2 + 1000);
1095
+
KUNIT_ASSERT_GT(test, rate, 0);
1096
+
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1 + 1000);
1097
+
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2 - 1000);
1098
+
1099
+
clk_put(clk);
1100
+
}
1101
+
1102
+
/*
1103
+
* Test that for a clock that can't modify its rate and with a single
1104
+
* parent, if we set a range on the child and a more restrictive one on
1105
+
* the parent, and then call clk_round_rate(), the boundaries of the
1106
+
* two clocks are taken into account.
1107
+
*/
1108
+
static void
1109
+
clk_test_single_parent_mux_set_range_round_rate_parent_smaller(struct kunit *test)
1110
+
{
1111
+
struct clk_single_parent_ctx *ctx = test->priv;
1112
+
struct clk_hw *hw = &ctx->hw;
1113
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1114
+
struct clk *parent;
1115
+
unsigned long rate;
1116
+
int ret;
1117
+
1118
+
parent = clk_get_parent(clk);
1119
+
KUNIT_ASSERT_PTR_NE(test, parent, NULL);
1120
+
1121
+
ret = clk_set_rate_range(parent, DUMMY_CLOCK_RATE_1 + 1000, DUMMY_CLOCK_RATE_2 - 1000);
1122
+
KUNIT_ASSERT_EQ(test, ret, 0);
1123
+
1124
+
ret = clk_set_rate_range(clk, DUMMY_CLOCK_RATE_1, DUMMY_CLOCK_RATE_2);
1125
+
KUNIT_ASSERT_EQ(test, ret, 0);
1126
+
1127
+
rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_1 - 1000);
1128
+
KUNIT_ASSERT_GT(test, rate, 0);
1129
+
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1 + 1000);
1130
+
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2 - 1000);
1131
+
1132
+
rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_2 + 1000);
1133
+
KUNIT_ASSERT_GT(test, rate, 0);
1134
+
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1 + 1000);
1135
+
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2 - 1000);
1136
+
1137
+
clk_put(clk);
1138
+
}
1139
+
1140
+
static struct kunit_case clk_single_parent_mux_test_cases[] = {
1141
+
KUNIT_CASE(clk_test_single_parent_mux_get_parent),
1142
+
KUNIT_CASE(clk_test_single_parent_mux_has_parent),
1143
+
KUNIT_CASE(clk_test_single_parent_mux_set_range_disjoint_child_last),
1144
+
KUNIT_CASE(clk_test_single_parent_mux_set_range_disjoint_parent_last),
1145
+
KUNIT_CASE(clk_test_single_parent_mux_set_range_round_rate_child_smaller),
1146
+
KUNIT_CASE(clk_test_single_parent_mux_set_range_round_rate_parent_only),
1147
+
KUNIT_CASE(clk_test_single_parent_mux_set_range_round_rate_parent_smaller),
1148
+
{}
1149
+
};
1150
+
1151
+
/*
1152
+
* Test suite for a basic mux clock with one parent, with
1153
+
* CLK_SET_RATE_PARENT on the child.
1154
+
*
1155
+
* These tests exercise the consumer API and check that the state of the
1156
+
* child and parent are sane and consistent.
1157
+
*/
1158
+
static struct kunit_suite
1159
+
clk_single_parent_mux_test_suite = {
1160
+
.name = "clk-single-parent-mux-test",
1161
+
.init = clk_single_parent_mux_test_init,
1162
+
.exit = clk_single_parent_mux_test_exit,
1163
+
.test_cases = clk_single_parent_mux_test_cases,
309
1164
};
310
1165
311
1166
static int clk_orphan_transparent_single_parent_mux_test_init(struct kunit *test)
···
1245
298
return 0;
1246
299
}
1247
300
1248
-
static void clk_orphan_transparent_single_parent_mux_test_exit(struct kunit *test)
1249
-
{
1250
-
struct clk_single_parent_ctx *ctx = test->priv;
1251
-
1252
-
clk_hw_unregister(&ctx->hw);
1253
-
clk_hw_unregister(&ctx->parent_ctx.hw);
1254
-
}
1255
-
1256
301
/*
1257
302
* Test that a mux-only clock, with an initial rate within a range,
1258
303
* will still have the same rate after the range has been enforced.
304
+
*
305
+
* See:
306
+
* https://lore.kernel.org/linux-clk/7720158d-10a7-a17b-73a4-a8615c9c6d5c@collabora.com/
1259
307
*/
1260
308
static void clk_test_orphan_transparent_parent_mux_set_range(struct kunit *test)
1261
309
{
1262
310
struct clk_single_parent_ctx *ctx = test->priv;
1263
311
struct clk_hw *hw = &ctx->hw;
1264
-
struct clk *clk = hw->clk;
312
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1265
313
unsigned long rate, new_rate;
1266
314
1267
315
rate = clk_get_rate(clk);
···
1271
329
new_rate = clk_get_rate(clk);
1272
330
KUNIT_ASSERT_GT(test, new_rate, 0);
1273
331
KUNIT_EXPECT_EQ(test, rate, new_rate);
332
+
333
+
clk_put(clk);
1274
334
}
1275
335
1276
336
static struct kunit_case clk_orphan_transparent_single_parent_mux_test_cases[] = {
···
1280
336
{}
1281
337
};
1282
338
339
+
/*
340
+
* Test suite for a basic mux clock with one parent. The parent is
341
+
* registered after its child. The clock will thus be an orphan when
342
+
* registered, but will no longer be when the tests run.
343
+
*
344
+
* These tests make sure a clock that used to be orphan has a sane,
345
+
* consistent, behaviour.
346
+
*/
1283
347
static struct kunit_suite clk_orphan_transparent_single_parent_test_suite = {
1284
348
.name = "clk-orphan-transparent-single-parent-test",
1285
349
.init = clk_orphan_transparent_single_parent_mux_test_init,
1286
-
.exit = clk_orphan_transparent_single_parent_mux_test_exit,
350
+
.exit = clk_single_parent_mux_test_exit,
1287
351
.test_cases = clk_orphan_transparent_single_parent_mux_test_cases,
352
+
};
353
+
354
+
struct clk_single_parent_two_lvl_ctx {
355
+
struct clk_dummy_context parent_parent_ctx;
356
+
struct clk_dummy_context parent_ctx;
357
+
struct clk_hw hw;
358
+
};
359
+
360
+
static int
361
+
clk_orphan_two_level_root_last_test_init(struct kunit *test)
362
+
{
363
+
struct clk_single_parent_two_lvl_ctx *ctx;
364
+
int ret;
365
+
366
+
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
367
+
if (!ctx)
368
+
return -ENOMEM;
369
+
test->priv = ctx;
370
+
371
+
ctx->parent_ctx.hw.init =
372
+
CLK_HW_INIT("intermediate-parent",
373
+
"root-parent",
374
+
&clk_dummy_single_parent_ops,
375
+
CLK_SET_RATE_PARENT);
376
+
ret = clk_hw_register(NULL, &ctx->parent_ctx.hw);
377
+
if (ret)
378
+
return ret;
379
+
380
+
ctx->hw.init =
381
+
CLK_HW_INIT("test-clk", "intermediate-parent",
382
+
&clk_dummy_single_parent_ops,
383
+
CLK_SET_RATE_PARENT);
384
+
ret = clk_hw_register(NULL, &ctx->hw);
385
+
if (ret)
386
+
return ret;
387
+
388
+
ctx->parent_parent_ctx.rate = DUMMY_CLOCK_INIT_RATE;
389
+
ctx->parent_parent_ctx.hw.init =
390
+
CLK_HW_INIT_NO_PARENT("root-parent",
391
+
&clk_dummy_rate_ops,
392
+
0);
393
+
ret = clk_hw_register(NULL, &ctx->parent_parent_ctx.hw);
394
+
if (ret)
395
+
return ret;
396
+
397
+
return 0;
398
+
}
399
+
400
+
static void
401
+
clk_orphan_two_level_root_last_test_exit(struct kunit *test)
402
+
{
403
+
struct clk_single_parent_two_lvl_ctx *ctx = test->priv;
404
+
405
+
clk_hw_unregister(&ctx->hw);
406
+
clk_hw_unregister(&ctx->parent_ctx.hw);
407
+
clk_hw_unregister(&ctx->parent_parent_ctx.hw);
408
+
}
409
+
410
+
/*
411
+
* Test that, for a clock whose parent used to be orphan, clk_get_rate()
412
+
* will return the proper rate.
413
+
*/
414
+
static void
415
+
clk_orphan_two_level_root_last_test_get_rate(struct kunit *test)
416
+
{
417
+
struct clk_single_parent_two_lvl_ctx *ctx = test->priv;
418
+
struct clk_hw *hw = &ctx->hw;
419
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
420
+
unsigned long rate;
421
+
422
+
rate = clk_get_rate(clk);
423
+
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_INIT_RATE);
424
+
425
+
clk_put(clk);
426
+
}
427
+
428
+
/*
429
+
* Test that, for a clock whose parent used to be orphan,
430
+
* clk_set_rate_range() won't affect its rate if it is already within
431
+
* range.
432
+
*
433
+
* See (for Exynos 4210):
434
+
* https://lore.kernel.org/linux-clk/366a0232-bb4a-c357-6aa8-636e398e05eb@samsung.com/
435
+
*/
436
+
static void
437
+
clk_orphan_two_level_root_last_test_set_range(struct kunit *test)
438
+
{
439
+
struct clk_single_parent_two_lvl_ctx *ctx = test->priv;
440
+
struct clk_hw *hw = &ctx->hw;
441
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
442
+
unsigned long rate;
443
+
int ret;
444
+
445
+
ret = clk_set_rate_range(clk,
446
+
DUMMY_CLOCK_INIT_RATE - 1000,
447
+
DUMMY_CLOCK_INIT_RATE + 1000);
448
+
KUNIT_ASSERT_EQ(test, ret, 0);
449
+
450
+
rate = clk_get_rate(clk);
451
+
KUNIT_ASSERT_GT(test, rate, 0);
452
+
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_INIT_RATE);
453
+
454
+
clk_put(clk);
455
+
}
456
+
457
+
static struct kunit_case
458
+
clk_orphan_two_level_root_last_test_cases[] = {
459
+
KUNIT_CASE(clk_orphan_two_level_root_last_test_get_rate),
460
+
KUNIT_CASE(clk_orphan_two_level_root_last_test_set_range),
461
+
{}
462
+
};
463
+
464
+
/*
465
+
* Test suite for a basic, transparent, clock with a parent that is also
466
+
* such a clock. The parent's parent is registered last, while the
467
+
* parent and its child are registered in that order. The intermediate
468
+
* and leaf clocks will thus be orphan when registered, but the leaf
469
+
* clock itself will always have its parent and will never be
470
+
* reparented. Indeed, it's only orphan because its parent is.
471
+
*
472
+
* These tests exercise the behaviour of the consumer API when dealing
473
+
* with an orphan clock, and how we deal with the transition to a valid
474
+
* parent.
475
+
*/
476
+
static struct kunit_suite
477
+
clk_orphan_two_level_root_last_test_suite = {
478
+
.name = "clk-orphan-two-level-root-last-test",
479
+
.init = clk_orphan_two_level_root_last_test_init,
480
+
.exit = clk_orphan_two_level_root_last_test_exit,
481
+
.test_cases = clk_orphan_two_level_root_last_test_cases,
1288
482
};
1289
483
1290
484
/*
···
1434
352
{
1435
353
struct clk_dummy_context *ctx = test->priv;
1436
354
struct clk_hw *hw = &ctx->hw;
1437
-
struct clk *clk = hw->clk;
355
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1438
356
unsigned long rate;
1439
357
1440
358
KUNIT_ASSERT_EQ(test,
···
1447
365
KUNIT_ASSERT_GT(test, rate, 0);
1448
366
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1);
1449
367
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2);
368
+
369
+
clk_put(clk);
1450
370
}
1451
371
1452
372
/*
···
1459
375
{
1460
376
struct clk_dummy_context *ctx = test->priv;
1461
377
struct clk_hw *hw = &ctx->hw;
1462
-
struct clk *clk = hw->clk;
378
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1463
379
1464
380
KUNIT_EXPECT_LT(test,
1465
381
clk_set_rate_range(clk,
1466
382
DUMMY_CLOCK_RATE_1 + 1000,
1467
383
DUMMY_CLOCK_RATE_1),
1468
384
0);
385
+
386
+
clk_put(clk);
1469
387
}
1470
388
1471
389
/*
···
1506
420
{
1507
421
struct clk_dummy_context *ctx = test->priv;
1508
422
struct clk_hw *hw = &ctx->hw;
1509
-
struct clk *clk = hw->clk;
423
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1510
424
long rate;
1511
425
1512
426
KUNIT_ASSERT_EQ(test,
···
1519
433
KUNIT_ASSERT_GT(test, rate, 0);
1520
434
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1);
1521
435
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2);
436
+
437
+
clk_put(clk);
1522
438
}
1523
439
1524
440
/*
···
1531
443
{
1532
444
struct clk_dummy_context *ctx = test->priv;
1533
445
struct clk_hw *hw = &ctx->hw;
1534
-
struct clk *clk = hw->clk;
446
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1535
447
unsigned long rate;
1536
448
1537
449
KUNIT_ASSERT_EQ(test,
···
1548
460
KUNIT_ASSERT_GT(test, rate, 0);
1549
461
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1);
1550
462
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2);
463
+
464
+
clk_put(clk);
1551
465
}
1552
466
1553
467
/*
···
1562
472
{
1563
473
struct clk_dummy_context *ctx = test->priv;
1564
474
struct clk_hw *hw = &ctx->hw;
1565
-
struct clk *clk = hw->clk;
475
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1566
476
long rounded;
1567
477
1568
478
KUNIT_ASSERT_EQ(test,
···
1579
489
0);
1580
490
1581
491
KUNIT_EXPECT_EQ(test, rounded, clk_get_rate(clk));
492
+
493
+
clk_put(clk);
1582
494
}
1583
495
1584
496
/*
···
1591
499
{
1592
500
struct clk_dummy_context *ctx = test->priv;
1593
501
struct clk_hw *hw = &ctx->hw;
1594
-
struct clk *clk = hw->clk;
502
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1595
503
long rate;
1596
504
1597
505
KUNIT_ASSERT_EQ(test,
···
1604
512
KUNIT_ASSERT_GT(test, rate, 0);
1605
513
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1);
1606
514
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2);
515
+
516
+
clk_put(clk);
1607
517
}
1608
518
1609
519
/*
···
1616
522
{
1617
523
struct clk_dummy_context *ctx = test->priv;
1618
524
struct clk_hw *hw = &ctx->hw;
1619
-
struct clk *clk = hw->clk;
525
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1620
526
unsigned long rate;
1621
527
1622
528
KUNIT_ASSERT_EQ(test,
···
1633
539
KUNIT_ASSERT_GT(test, rate, 0);
1634
540
KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1);
1635
541
KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2);
542
+
543
+
clk_put(clk);
1636
544
}
1637
545
1638
546
/*
···
1647
551
{
1648
552
struct clk_dummy_context *ctx = test->priv;
1649
553
struct clk_hw *hw = &ctx->hw;
1650
-
struct clk *clk = hw->clk;
554
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1651
555
long rounded;
1652
556
1653
557
KUNIT_ASSERT_EQ(test,
···
1664
568
0);
1665
569
1666
570
KUNIT_EXPECT_EQ(test, rounded, clk_get_rate(clk));
571
+
572
+
clk_put(clk);
1667
573
}
1668
574
1669
575
/*
···
1680
582
{
1681
583
struct clk_dummy_context *ctx = test->priv;
1682
584
struct clk_hw *hw = &ctx->hw;
1683
-
struct clk *clk = hw->clk;
585
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1684
586
unsigned long rate;
1685
587
1686
588
KUNIT_ASSERT_EQ(test,
···
1696
598
rate = clk_get_rate(clk);
1697
599
KUNIT_ASSERT_GT(test, rate, 0);
1698
600
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
601
+
602
+
clk_put(clk);
1699
603
}
1700
604
1701
605
/*
···
1712
612
{
1713
613
struct clk_dummy_context *ctx = test->priv;
1714
614
struct clk_hw *hw = &ctx->hw;
1715
-
struct clk *clk = hw->clk;
615
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1716
616
unsigned long rate;
1717
617
1718
618
KUNIT_ASSERT_EQ(test,
···
1728
628
rate = clk_get_rate(clk);
1729
629
KUNIT_ASSERT_GT(test, rate, 0);
1730
630
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2);
631
+
632
+
clk_put(clk);
1731
633
}
1732
634
1733
635
static struct kunit_case clk_range_test_cases[] = {
···
1747
645
{}
1748
646
};
1749
647
648
+
/*
649
+
* Test suite for a basic rate clock, without any parent.
650
+
*
651
+
* These tests exercise the rate range API: clk_set_rate_range(),
652
+
* clk_set_min_rate(), clk_set_max_rate(), clk_drop_range().
653
+
*/
1750
654
static struct kunit_suite clk_range_test_suite = {
1751
655
.name = "clk-range-test",
1752
656
.init = clk_test_init,
···
1772
664
{
1773
665
struct clk_dummy_context *ctx = test->priv;
1774
666
struct clk_hw *hw = &ctx->hw;
1775
-
struct clk *clk = hw->clk;
667
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1776
668
unsigned long rate;
1777
669
1778
670
KUNIT_ASSERT_EQ(test,
···
1808
700
rate = clk_get_rate(clk);
1809
701
KUNIT_ASSERT_GT(test, rate, 0);
1810
702
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2);
703
+
704
+
clk_put(clk);
1811
705
}
1812
706
1813
707
/*
···
1824
714
{
1825
715
struct clk_dummy_context *ctx = test->priv;
1826
716
struct clk_hw *hw = &ctx->hw;
1827
-
struct clk *clk = hw->clk;
717
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1828
718
struct clk *user1, *user2;
1829
719
unsigned long rate;
1830
720
···
1868
758
1869
759
clk_put(user2);
1870
760
clk_put(user1);
761
+
clk_put(clk);
762
+
}
763
+
764
+
/*
765
+
* Test that if we have several subsequent calls to
766
+
* clk_set_rate_range(), across multiple users, the core will reevaluate
767
+
* whether a new rate is needed, including when a user drop its clock.
768
+
*
769
+
* With clk_dummy_maximize_rate_ops, this means that the rate will
770
+
* trail along the maximum as it evolves.
771
+
*/
772
+
static void clk_range_test_multiple_set_range_rate_put_maximized(struct kunit *test)
773
+
{
774
+
struct clk_dummy_context *ctx = test->priv;
775
+
struct clk_hw *hw = &ctx->hw;
776
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
777
+
struct clk *user1, *user2;
778
+
unsigned long rate;
779
+
780
+
user1 = clk_hw_get_clk(hw, NULL);
781
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user1);
782
+
783
+
user2 = clk_hw_get_clk(hw, NULL);
784
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user2);
785
+
786
+
KUNIT_ASSERT_EQ(test,
787
+
clk_set_rate(clk, DUMMY_CLOCK_RATE_2 + 1000),
788
+
0);
789
+
790
+
KUNIT_ASSERT_EQ(test,
791
+
clk_set_rate_range(user1,
792
+
0,
793
+
DUMMY_CLOCK_RATE_2),
794
+
0);
795
+
796
+
rate = clk_get_rate(clk);
797
+
KUNIT_ASSERT_GT(test, rate, 0);
798
+
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2);
799
+
800
+
KUNIT_ASSERT_EQ(test,
801
+
clk_set_rate_range(user2,
802
+
0,
803
+
DUMMY_CLOCK_RATE_1),
804
+
0);
805
+
806
+
rate = clk_get_rate(clk);
807
+
KUNIT_ASSERT_GT(test, rate, 0);
808
+
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
809
+
810
+
clk_put(user2);
811
+
812
+
rate = clk_get_rate(clk);
813
+
KUNIT_ASSERT_GT(test, rate, 0);
814
+
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2);
815
+
816
+
clk_put(user1);
817
+
clk_put(clk);
1871
818
}
1872
819
1873
820
static struct kunit_case clk_range_maximize_test_cases[] = {
1874
821
KUNIT_CASE(clk_range_test_set_range_rate_maximized),
1875
822
KUNIT_CASE(clk_range_test_multiple_set_range_rate_maximized),
823
+
KUNIT_CASE(clk_range_test_multiple_set_range_rate_put_maximized),
1876
824
{}
1877
825
};
1878
826
827
+
/*
828
+
* Test suite for a basic rate clock, without any parent.
829
+
*
830
+
* These tests exercise the rate range API: clk_set_rate_range(),
831
+
* clk_set_min_rate(), clk_set_max_rate(), clk_drop_range(), with a
832
+
* driver that will always try to run at the highest possible rate.
833
+
*/
1879
834
static struct kunit_suite clk_range_maximize_test_suite = {
1880
835
.name = "clk-range-maximize-test",
1881
836
.init = clk_maximize_test_init,
···
1960
785
{
1961
786
struct clk_dummy_context *ctx = test->priv;
1962
787
struct clk_hw *hw = &ctx->hw;
1963
-
struct clk *clk = hw->clk;
788
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1964
789
unsigned long rate;
1965
790
1966
791
KUNIT_ASSERT_EQ(test,
···
1996
821
rate = clk_get_rate(clk);
1997
822
KUNIT_ASSERT_GT(test, rate, 0);
1998
823
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
824
+
825
+
clk_put(clk);
1999
826
}
2000
827
2001
828
/*
···
2012
835
{
2013
836
struct clk_dummy_context *ctx = test->priv;
2014
837
struct clk_hw *hw = &ctx->hw;
2015
-
struct clk *clk = hw->clk;
838
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
2016
839
struct clk *user1, *user2;
2017
840
unsigned long rate;
2018
841
···
2052
875
2053
876
clk_put(user2);
2054
877
clk_put(user1);
878
+
clk_put(clk);
879
+
}
880
+
881
+
/*
882
+
* Test that if we have several subsequent calls to
883
+
* clk_set_rate_range(), across multiple users, the core will reevaluate
884
+
* whether a new rate is needed, including when a user drop its clock.
885
+
*
886
+
* With clk_dummy_minimize_rate_ops, this means that the rate will
887
+
* trail along the minimum as it evolves.
888
+
*/
889
+
static void clk_range_test_multiple_set_range_rate_put_minimized(struct kunit *test)
890
+
{
891
+
struct clk_dummy_context *ctx = test->priv;
892
+
struct clk_hw *hw = &ctx->hw;
893
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
894
+
struct clk *user1, *user2;
895
+
unsigned long rate;
896
+
897
+
user1 = clk_hw_get_clk(hw, NULL);
898
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user1);
899
+
900
+
user2 = clk_hw_get_clk(hw, NULL);
901
+
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user2);
902
+
903
+
KUNIT_ASSERT_EQ(test,
904
+
clk_set_rate_range(user1,
905
+
DUMMY_CLOCK_RATE_1,
906
+
ULONG_MAX),
907
+
0);
908
+
909
+
rate = clk_get_rate(clk);
910
+
KUNIT_ASSERT_GT(test, rate, 0);
911
+
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
912
+
913
+
KUNIT_ASSERT_EQ(test,
914
+
clk_set_rate_range(user2,
915
+
DUMMY_CLOCK_RATE_2,
916
+
ULONG_MAX),
917
+
0);
918
+
919
+
rate = clk_get_rate(clk);
920
+
KUNIT_ASSERT_GT(test, rate, 0);
921
+
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2);
922
+
923
+
clk_put(user2);
924
+
925
+
rate = clk_get_rate(clk);
926
+
KUNIT_ASSERT_GT(test, rate, 0);
927
+
KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
928
+
929
+
clk_put(user1);
930
+
clk_put(clk);
2055
931
}
2056
932
2057
933
static struct kunit_case clk_range_minimize_test_cases[] = {
2058
934
KUNIT_CASE(clk_range_test_set_range_rate_minimized),
2059
935
KUNIT_CASE(clk_range_test_multiple_set_range_rate_minimized),
936
+
KUNIT_CASE(clk_range_test_multiple_set_range_rate_put_minimized),
2060
937
{}
2061
938
};
2062
939
940
+
/*
941
+
* Test suite for a basic rate clock, without any parent.
942
+
*
943
+
* These tests exercise the rate range API: clk_set_rate_range(),
944
+
* clk_set_min_rate(), clk_set_max_rate(), clk_drop_range(), with a
945
+
* driver that will always try to run at the lowest possible rate.
946
+
*/
2063
947
static struct kunit_suite clk_range_minimize_test_suite = {
2064
948
.name = "clk-range-minimize-test",
2065
949
.init = clk_minimize_test_init,
···
2128
890
.test_cases = clk_range_minimize_test_cases,
2129
891
};
2130
892
893
+
struct clk_leaf_mux_ctx {
894
+
struct clk_multiple_parent_ctx mux_ctx;
895
+
struct clk_hw hw;
896
+
};
897
+
898
+
static int
899
+
clk_leaf_mux_set_rate_parent_test_init(struct kunit *test)
900
+
{
901
+
struct clk_leaf_mux_ctx *ctx;
902
+
const char *top_parents[2] = { "parent-0", "parent-1" };
903
+
int ret;
904
+
905
+
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
906
+
if (!ctx)
907
+
return -ENOMEM;
908
+
test->priv = ctx;
909
+
910
+
ctx->mux_ctx.parents_ctx[0].hw.init = CLK_HW_INIT_NO_PARENT("parent-0",
911
+
&clk_dummy_rate_ops,
912
+
0);
913
+
ctx->mux_ctx.parents_ctx[0].rate = DUMMY_CLOCK_RATE_1;
914
+
ret = clk_hw_register(NULL, &ctx->mux_ctx.parents_ctx[0].hw);
915
+
if (ret)
916
+
return ret;
917
+
918
+
ctx->mux_ctx.parents_ctx[1].hw.init = CLK_HW_INIT_NO_PARENT("parent-1",
919
+
&clk_dummy_rate_ops,
920
+
0);
921
+
ctx->mux_ctx.parents_ctx[1].rate = DUMMY_CLOCK_RATE_2;
922
+
ret = clk_hw_register(NULL, &ctx->mux_ctx.parents_ctx[1].hw);
923
+
if (ret)
924
+
return ret;
925
+
926
+
ctx->mux_ctx.current_parent = 0;
927
+
ctx->mux_ctx.hw.init = CLK_HW_INIT_PARENTS("test-mux", top_parents,
928
+
&clk_multiple_parents_mux_ops,
929
+
0);
930
+
ret = clk_hw_register(NULL, &ctx->mux_ctx.hw);
931
+
if (ret)
932
+
return ret;
933
+
934
+
ctx->hw.init = CLK_HW_INIT_HW("test-clock", &ctx->mux_ctx.hw,
935
+
&clk_dummy_single_parent_ops,
936
+
CLK_SET_RATE_PARENT);
937
+
ret = clk_hw_register(NULL, &ctx->hw);
938
+
if (ret)
939
+
return ret;
940
+
941
+
return 0;
942
+
}
943
+
944
+
static void clk_leaf_mux_set_rate_parent_test_exit(struct kunit *test)
945
+
{
946
+
struct clk_leaf_mux_ctx *ctx = test->priv;
947
+
948
+
clk_hw_unregister(&ctx->hw);
949
+
clk_hw_unregister(&ctx->mux_ctx.hw);
950
+
clk_hw_unregister(&ctx->mux_ctx.parents_ctx[0].hw);
951
+
clk_hw_unregister(&ctx->mux_ctx.parents_ctx[1].hw);
952
+
}
953
+
954
+
/*
955
+
* Test that, for a clock that will forward any rate request to its
956
+
* parent, the rate request structure returned by __clk_determine_rate
957
+
* is sane and will be what we expect.
958
+
*/
959
+
static void clk_leaf_mux_set_rate_parent_determine_rate(struct kunit *test)
960
+
{
961
+
struct clk_leaf_mux_ctx *ctx = test->priv;
962
+
struct clk_hw *hw = &ctx->hw;
963
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
964
+
struct clk_rate_request req;
965
+
unsigned long rate;
966
+
int ret;
967
+
968
+
rate = clk_get_rate(clk);
969
+
KUNIT_ASSERT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
970
+
971
+
clk_hw_init_rate_request(hw, &req, DUMMY_CLOCK_RATE_2);
972
+
973
+
ret = __clk_determine_rate(hw, &req);
974
+
KUNIT_ASSERT_EQ(test, ret, 0);
975
+
976
+
KUNIT_EXPECT_EQ(test, req.rate, DUMMY_CLOCK_RATE_2);
977
+
KUNIT_EXPECT_EQ(test, req.best_parent_rate, DUMMY_CLOCK_RATE_2);
978
+
KUNIT_EXPECT_PTR_EQ(test, req.best_parent_hw, &ctx->mux_ctx.hw);
979
+
980
+
clk_put(clk);
981
+
}
982
+
983
+
static struct kunit_case clk_leaf_mux_set_rate_parent_test_cases[] = {
984
+
KUNIT_CASE(clk_leaf_mux_set_rate_parent_determine_rate),
985
+
{}
986
+
};
987
+
988
+
/*
989
+
* Test suite for a clock whose parent is a mux with multiple parents.
990
+
* The leaf clock has CLK_SET_RATE_PARENT, and will forward rate
991
+
* requests to the mux, which will then select which parent is the best
992
+
* fit for a given rate.
993
+
*
994
+
* These tests exercise the behaviour of muxes, and the proper selection
995
+
* of parents.
996
+
*/
997
+
static struct kunit_suite clk_leaf_mux_set_rate_parent_test_suite = {
998
+
.name = "clk-leaf-mux-set-rate-parent",
999
+
.init = clk_leaf_mux_set_rate_parent_test_init,
1000
+
.exit = clk_leaf_mux_set_rate_parent_test_exit,
1001
+
.test_cases = clk_leaf_mux_set_rate_parent_test_cases,
1002
+
};
1003
+
1004
+
struct clk_mux_notifier_rate_change {
1005
+
bool done;
1006
+
unsigned long old_rate;
1007
+
unsigned long new_rate;
1008
+
wait_queue_head_t wq;
1009
+
};
1010
+
1011
+
struct clk_mux_notifier_ctx {
1012
+
struct clk_multiple_parent_ctx mux_ctx;
1013
+
struct clk *clk;
1014
+
struct notifier_block clk_nb;
1015
+
struct clk_mux_notifier_rate_change pre_rate_change;
1016
+
struct clk_mux_notifier_rate_change post_rate_change;
1017
+
};
1018
+
1019
+
#define NOTIFIER_TIMEOUT_MS 100
1020
+
1021
+
static int clk_mux_notifier_callback(struct notifier_block *nb,
1022
+
unsigned long action, void *data)
1023
+
{
1024
+
struct clk_notifier_data *clk_data = data;
1025
+
struct clk_mux_notifier_ctx *ctx = container_of(nb,
1026
+
struct clk_mux_notifier_ctx,
1027
+
clk_nb);
1028
+
1029
+
if (action & PRE_RATE_CHANGE) {
1030
+
ctx->pre_rate_change.old_rate = clk_data->old_rate;
1031
+
ctx->pre_rate_change.new_rate = clk_data->new_rate;
1032
+
ctx->pre_rate_change.done = true;
1033
+
wake_up_interruptible(&ctx->pre_rate_change.wq);
1034
+
}
1035
+
1036
+
if (action & POST_RATE_CHANGE) {
1037
+
ctx->post_rate_change.old_rate = clk_data->old_rate;
1038
+
ctx->post_rate_change.new_rate = clk_data->new_rate;
1039
+
ctx->post_rate_change.done = true;
1040
+
wake_up_interruptible(&ctx->post_rate_change.wq);
1041
+
}
1042
+
1043
+
return 0;
1044
+
}
1045
+
1046
+
static int clk_mux_notifier_test_init(struct kunit *test)
1047
+
{
1048
+
struct clk_mux_notifier_ctx *ctx;
1049
+
const char *top_parents[2] = { "parent-0", "parent-1" };
1050
+
int ret;
1051
+
1052
+
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
1053
+
if (!ctx)
1054
+
return -ENOMEM;
1055
+
test->priv = ctx;
1056
+
ctx->clk_nb.notifier_call = clk_mux_notifier_callback;
1057
+
init_waitqueue_head(&ctx->pre_rate_change.wq);
1058
+
init_waitqueue_head(&ctx->post_rate_change.wq);
1059
+
1060
+
ctx->mux_ctx.parents_ctx[0].hw.init = CLK_HW_INIT_NO_PARENT("parent-0",
1061
+
&clk_dummy_rate_ops,
1062
+
0);
1063
+
ctx->mux_ctx.parents_ctx[0].rate = DUMMY_CLOCK_RATE_1;
1064
+
ret = clk_hw_register(NULL, &ctx->mux_ctx.parents_ctx[0].hw);
1065
+
if (ret)
1066
+
return ret;
1067
+
1068
+
ctx->mux_ctx.parents_ctx[1].hw.init = CLK_HW_INIT_NO_PARENT("parent-1",
1069
+
&clk_dummy_rate_ops,
1070
+
0);
1071
+
ctx->mux_ctx.parents_ctx[1].rate = DUMMY_CLOCK_RATE_2;
1072
+
ret = clk_hw_register(NULL, &ctx->mux_ctx.parents_ctx[1].hw);
1073
+
if (ret)
1074
+
return ret;
1075
+
1076
+
ctx->mux_ctx.current_parent = 0;
1077
+
ctx->mux_ctx.hw.init = CLK_HW_INIT_PARENTS("test-mux", top_parents,
1078
+
&clk_multiple_parents_mux_ops,
1079
+
0);
1080
+
ret = clk_hw_register(NULL, &ctx->mux_ctx.hw);
1081
+
if (ret)
1082
+
return ret;
1083
+
1084
+
ctx->clk = clk_hw_get_clk(&ctx->mux_ctx.hw, NULL);
1085
+
ret = clk_notifier_register(ctx->clk, &ctx->clk_nb);
1086
+
if (ret)
1087
+
return ret;
1088
+
1089
+
return 0;
1090
+
}
1091
+
1092
+
static void clk_mux_notifier_test_exit(struct kunit *test)
1093
+
{
1094
+
struct clk_mux_notifier_ctx *ctx = test->priv;
1095
+
struct clk *clk = ctx->clk;
1096
+
1097
+
clk_notifier_unregister(clk, &ctx->clk_nb);
1098
+
clk_put(clk);
1099
+
1100
+
clk_hw_unregister(&ctx->mux_ctx.hw);
1101
+
clk_hw_unregister(&ctx->mux_ctx.parents_ctx[0].hw);
1102
+
clk_hw_unregister(&ctx->mux_ctx.parents_ctx[1].hw);
1103
+
}
1104
+
1105
+
/*
1106
+
* Test that if the we have a notifier registered on a mux, the core
1107
+
* will notify us when we switch to another parent, and with the proper
1108
+
* old and new rates.
1109
+
*/
1110
+
static void clk_mux_notifier_set_parent_test(struct kunit *test)
1111
+
{
1112
+
struct clk_mux_notifier_ctx *ctx = test->priv;
1113
+
struct clk_hw *hw = &ctx->mux_ctx.hw;
1114
+
struct clk *clk = clk_hw_get_clk(hw, NULL);
1115
+
struct clk *new_parent = clk_hw_get_clk(&ctx->mux_ctx.parents_ctx[1].hw, NULL);
1116
+
int ret;
1117
+
1118
+
ret = clk_set_parent(clk, new_parent);
1119
+
KUNIT_ASSERT_EQ(test, ret, 0);
1120
+
1121
+
ret = wait_event_interruptible_timeout(ctx->pre_rate_change.wq,
1122
+
ctx->pre_rate_change.done,
1123
+
msecs_to_jiffies(NOTIFIER_TIMEOUT_MS));
1124
+
KUNIT_ASSERT_GT(test, ret, 0);
1125
+
1126
+
KUNIT_EXPECT_EQ(test, ctx->pre_rate_change.old_rate, DUMMY_CLOCK_RATE_1);
1127
+
KUNIT_EXPECT_EQ(test, ctx->pre_rate_change.new_rate, DUMMY_CLOCK_RATE_2);
1128
+
1129
+
ret = wait_event_interruptible_timeout(ctx->post_rate_change.wq,
1130
+
ctx->post_rate_change.done,
1131
+
msecs_to_jiffies(NOTIFIER_TIMEOUT_MS));
1132
+
KUNIT_ASSERT_GT(test, ret, 0);
1133
+
1134
+
KUNIT_EXPECT_EQ(test, ctx->post_rate_change.old_rate, DUMMY_CLOCK_RATE_1);
1135
+
KUNIT_EXPECT_EQ(test, ctx->post_rate_change.new_rate, DUMMY_CLOCK_RATE_2);
1136
+
1137
+
clk_put(new_parent);
1138
+
clk_put(clk);
1139
+
}
1140
+
1141
+
static struct kunit_case clk_mux_notifier_test_cases[] = {
1142
+
KUNIT_CASE(clk_mux_notifier_set_parent_test),
1143
+
{}
1144
+
};
1145
+
1146
+
/*
1147
+
* Test suite for a mux with multiple parents, and a notifier registered
1148
+
* on the mux.
1149
+
*
1150
+
* These tests exercise the behaviour of notifiers.
1151
+
*/
1152
+
static struct kunit_suite clk_mux_notifier_test_suite = {
1153
+
.name = "clk-mux-notifier",
1154
+
.init = clk_mux_notifier_test_init,
1155
+
.exit = clk_mux_notifier_test_exit,
1156
+
.test_cases = clk_mux_notifier_test_cases,
1157
+
};
1158
+
2131
1159
kunit_test_suites(
1160
+
&clk_leaf_mux_set_rate_parent_test_suite,
2132
1161
&clk_test_suite,
1162
+
&clk_multiple_parents_mux_test_suite,
1163
+
&clk_mux_notifier_test_suite,
1164
+
&clk_orphan_transparent_multiple_parent_mux_test_suite,
2133
1165
&clk_orphan_transparent_single_parent_test_suite,
1166
+
&clk_orphan_two_level_root_last_test_suite,
2134
1167
&clk_range_test_suite,
2135
1168
&clk_range_maximize_test_suite,
2136
-
&clk_range_minimize_test_suite
1169
+
&clk_range_minimize_test_suite,
1170
+
&clk_single_parent_mux_test_suite,
1171
+
&clk_uncached_test_suite
2137
1172
);
2138
1173
MODULE_LICENSE("GPL v2");
+10
drivers/clk/mediatek/clk-mux.c
+10
drivers/clk/mediatek/clk-mux.c
···
129
129
return 0;
130
130
}
131
131
132
+
static int mtk_clk_mux_determine_rate(struct clk_hw *hw,
133
+
struct clk_rate_request *req)
134
+
{
135
+
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
136
+
137
+
return clk_mux_determine_rate_flags(hw, req, mux->data->flags);
138
+
}
139
+
132
140
const struct clk_ops mtk_mux_clr_set_upd_ops = {
133
141
.get_parent = mtk_clk_mux_get_parent,
134
142
.set_parent = mtk_clk_mux_set_parent_setclr_lock,
143
+
.determine_rate = mtk_clk_mux_determine_rate,
135
144
};
136
145
EXPORT_SYMBOL_GPL(mtk_mux_clr_set_upd_ops);
137
146
···
150
141
.is_enabled = mtk_clk_mux_is_enabled,
151
142
.get_parent = mtk_clk_mux_get_parent,
152
143
.set_parent = mtk_clk_mux_set_parent_setclr_lock,
144
+
.determine_rate = mtk_clk_mux_determine_rate,
153
145
};
154
146
EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
155
147
+9
drivers/clk/qcom/clk-rcg2.c
+9
drivers/clk/qcom/clk-rcg2.c
···
915
915
req->best_parent_hw = p2;
916
916
}
917
917
918
+
clk_hw_get_rate_range(req->best_parent_hw,
919
+
&parent_req.min_rate, &parent_req.max_rate);
920
+
921
+
if (req->min_rate > parent_req.min_rate)
922
+
parent_req.min_rate = req->min_rate;
923
+
924
+
if (req->max_rate < parent_req.max_rate)
925
+
parent_req.max_rate = req->max_rate;
926
+
918
927
ret = __clk_determine_rate(req->best_parent_hw, &parent_req);
919
928
if (ret)
920
929
return ret;
-11
drivers/clk/qcom/gcc-msm8660.c
-11
drivers/clk/qcom/gcc-msm8660.c
···
2767
2767
2768
2768
static int gcc_msm8660_probe(struct platform_device *pdev)
2769
2769
{
2770
-
int ret;
2771
-
struct device *dev = &pdev->dev;
2772
-
2773
-
ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
2774
-
if (ret)
2775
-
return ret;
2776
-
2777
-
ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
2778
-
if (ret)
2779
-
return ret;
2780
-
2781
2770
return qcom_cc_probe(pdev, &gcc_msm8660_desc);
2782
2771
}
2783
2772
+1
drivers/clk/tegra/clk-tegra114.c
+1
drivers/clk/tegra/clk-tegra114.c
···
1166
1166
{ TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1167
1167
{ TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1168
1168
{ TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1169
+
{ TEGRA114_CLK_PWM, TEGRA114_CLK_PLL_P, 408000000, 0 },
1169
1170
/* must be the last entry */
1170
1171
{ TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
1171
1172
};
+1
drivers/clk/tegra/clk-tegra124.c
+1
drivers/clk/tegra/clk-tegra124.c
···
1330
1330
{ TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1331
1331
{ TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1332
1332
{ TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1333
+
{ TEGRA124_CLK_PWM, TEGRA124_CLK_PLL_P, 408000000, 0 },
1333
1334
/* must be the last entry */
1334
1335
{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1335
1336
};
+1
drivers/clk/tegra/clk-tegra20.c
+1
drivers/clk/tegra/clk-tegra20.c
···
1044
1044
{ TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
1045
1045
{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
1046
1046
{ TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 },
1047
+
{ TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 },
1047
1048
/* must be the last entry */
1048
1049
{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
1049
1050
};
+1
drivers/clk/tegra/clk-tegra210.c
+1
drivers/clk/tegra/clk-tegra210.c
···
3597
3597
{ TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3598
3598
{ TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
3599
3599
{ TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
3600
+
{ TEGRA210_CLK_PWM, TEGRA210_CLK_PLL_P, 48000000, 0 },
3600
3601
/* This MUST be the last entry. */
3601
3602
{ TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
3602
3603
};
+1
drivers/clk/tegra/clk-tegra30.c
+1
drivers/clk/tegra/clk-tegra30.c
···
1237
1237
{ TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1238
1238
{ TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },
1239
1239
{ TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },
1240
+
{ TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 },
1240
1241
/* must be the last entry */
1241
1242
{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
1242
1243
};
+16
-2
include/linux/clk-provider.h
+16
-2
include/linux/clk-provider.h
···
42
42
* struct clk_rate_request - Structure encoding the clk constraints that
43
43
* a clock user might require.
44
44
*
45
+
* Should be initialized by calling clk_hw_init_rate_request().
46
+
*
45
47
* @rate: Requested clock rate. This field will be adjusted by
46
48
* clock drivers according to hardware capabilities.
47
49
* @min_rate: Minimum rate imposed by clk users.
···
61
59
unsigned long best_parent_rate;
62
60
struct clk_hw *best_parent_hw;
63
61
};
62
+
63
+
void clk_hw_init_rate_request(const struct clk_hw *hw,
64
+
struct clk_rate_request *req,
65
+
unsigned long rate);
66
+
void clk_hw_forward_rate_request(const struct clk_hw *core,
67
+
const struct clk_rate_request *old_req,
68
+
const struct clk_hw *parent,
69
+
struct clk_rate_request *req,
70
+
unsigned long parent_rate);
64
71
65
72
/**
66
73
* struct clk_duty - Struture encoding the duty cycle ratio of a clock
···
129
118
*
130
119
* @recalc_rate Recalculate the rate of this clock, by querying hardware. The
131
120
* parent rate is an input parameter. It is up to the caller to
132
-
* ensure that the prepare_mutex is held across this call.
133
-
* Returns the calculated rate. Optional, but recommended - if
121
+
* ensure that the prepare_mutex is held across this call. If the
122
+
* driver cannot figure out a rate for this clock, it must return
123
+
* 0. Returns the calculated rate. Optional, but recommended - if
134
124
* this op is not set then clock rate will be initialized to 0.
135
125
*
136
126
* @round_rate: Given a target rate as input, returns the closest rate actually
···
1315
1303
struct clk_rate_request *req,
1316
1304
unsigned long flags);
1317
1305
void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1306
+
void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate,
1307
+
unsigned long *max_rate);
1318
1308
void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1319
1309
unsigned long max_rate);
1320
1310
+1
-1
include/linux/clk.h
+1
-1
include/linux/clk.h
···
799
799
*
800
800
* Returns true if @parent is a possible parent for @clk, false otherwise.
801
801
*/
802
-
bool clk_has_parent(struct clk *clk, struct clk *parent);
802
+
bool clk_has_parent(const struct clk *clk, const struct clk *parent);
803
803
804
804
/**
805
805
* clk_set_rate_range - set a rate range for a clock source
+4
-2
include/linux/clk/at91_pmc.h
+4
-2
include/linux/clk/at91_pmc.h
···
12
12
#ifndef AT91_PMC_H
13
13
#define AT91_PMC_H
14
14
15
+
#include <linux/bits.h>
16
+
15
17
#define AT91_PMC_V1 (1) /* PMC version 1 */
16
18
#define AT91_PMC_V2 (2) /* PMC version 2 [SAM9X60] */
17
19
···
47
45
#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
48
46
49
47
#define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */
50
-
#define AT91_PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL /* Default PLL ACR value for UPLL */
51
-
#define AT91_PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL /* Default PLL ACR value for PLLA */
48
+
#define AT91_PMC_PLL_ACR_DEFAULT_UPLL UL(0x12020010) /* Default PLL ACR value for UPLL */
49
+
#define AT91_PMC_PLL_ACR_DEFAULT_PLLA UL(0x00020010) /* Default PLL ACR value for PLLA */
52
50
#define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */
53
51
#define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */
54
52