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phy: qcom-qmp-pcie: merge driver data

The PCIe QMP PHY driver only manages a single PHY so merge the old
qcom_qmp and qmp_phy structures and drop the PHY array.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-4-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Johan Hovold and committed by
Vinod Koul 2fdedef3 cebc6ca7

+93 -135
+93 -135
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 1365 1365 unsigned long pipe_clock_rate; 1366 1366 }; 1367 1367 1368 - /** 1369 - * struct qmp_phy - per-lane phy descriptor 1370 - * 1371 - * @phy: generic phy 1372 - * @cfg: phy specific configuration 1373 - * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 1374 - * @tx: iomapped memory space for lane's tx 1375 - * @rx: iomapped memory space for lane's rx 1376 - * @pcs: iomapped memory space for lane's pcs 1377 - * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 1378 - * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 1379 - * @pcs_misc: iomapped memory space for lane's pcs_misc 1380 - * @pipe_clk: pipe clock 1381 - * @qmp: QMP phy to which this lane belongs 1382 - * @mode: currently selected PHY mode 1383 - */ 1384 - struct qmp_phy { 1385 - struct phy *phy; 1386 - const struct qmp_phy_cfg *cfg; 1387 - void __iomem *serdes; 1388 - void __iomem *tx; 1389 - void __iomem *rx; 1390 - void __iomem *pcs; 1391 - void __iomem *tx2; 1392 - void __iomem *rx2; 1393 - void __iomem *pcs_misc; 1394 - struct clk *pipe_clk; 1395 - struct qcom_qmp *qmp; 1396 - int mode; 1397 - }; 1398 - 1399 - /** 1400 - * struct qcom_qmp - structure holding QMP phy block attributes 1401 - * 1402 - * @dev: device 1403 - * 1404 - * @clks: array of clocks required by phy 1405 - * @resets: array of resets required by phy 1406 - * @vregs: regulator supplies bulk data 1407 - * 1408 - * @phys: array of per-lane phy descriptors 1409 - */ 1410 - struct qcom_qmp { 1368 + struct qmp_pcie { 1411 1369 struct device *dev; 1412 1370 1371 + const struct qmp_phy_cfg *cfg; 1372 + 1373 + void __iomem *serdes; 1374 + void __iomem *pcs; 1375 + void __iomem *pcs_misc; 1376 + void __iomem *tx; 1377 + void __iomem *rx; 1378 + void __iomem *tx2; 1379 + void __iomem *rx2; 1380 + 1381 + struct clk *pipe_clk; 1413 1382 struct clk_bulk_data *clks; 1414 1383 struct reset_control_bulk_data *resets; 1415 1384 struct regulator_bulk_data *vregs; 1416 1385 1417 - struct qmp_phy **phys; 1386 + struct phy *phy; 1387 + int mode; 1418 1388 }; 1419 1389 1420 1390 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) ··· 1820 1850 qmp_pcie_configure_lane(base, tbl, num, 0xff); 1821 1851 } 1822 1852 1823 - static void qmp_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1853 + static void qmp_pcie_serdes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables) 1824 1854 { 1825 - void __iomem *serdes = qphy->serdes; 1855 + void __iomem *serdes = qmp->serdes; 1826 1856 1827 1857 if (!tables) 1828 1858 return; ··· 1830 1860 qmp_pcie_configure(serdes, tables->serdes, tables->serdes_num); 1831 1861 } 1832 1862 1833 - static void qmp_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1863 + static void qmp_pcie_lanes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables) 1834 1864 { 1835 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1836 - void __iomem *tx = qphy->tx; 1837 - void __iomem *rx = qphy->rx; 1865 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1866 + void __iomem *tx = qmp->tx; 1867 + void __iomem *rx = qmp->rx; 1838 1868 1839 1869 if (!tables) 1840 1870 return; ··· 1842 1872 qmp_pcie_configure_lane(tx, tables->tx, tables->tx_num, 1); 1843 1873 1844 1874 if (cfg->lanes >= 2) 1845 - qmp_pcie_configure_lane(qphy->tx2, tables->tx, tables->tx_num, 2); 1875 + qmp_pcie_configure_lane(qmp->tx2, tables->tx, tables->tx_num, 2); 1846 1876 1847 1877 qmp_pcie_configure_lane(rx, tables->rx, tables->rx_num, 1); 1848 1878 if (cfg->lanes >= 2) 1849 - qmp_pcie_configure_lane(qphy->rx2, tables->rx, tables->rx_num, 2); 1879 + qmp_pcie_configure_lane(qmp->rx2, tables->rx, tables->rx_num, 2); 1850 1880 } 1851 1881 1852 - static void qmp_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1882 + static void qmp_pcie_pcs_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables) 1853 1883 { 1854 - void __iomem *pcs = qphy->pcs; 1855 - void __iomem *pcs_misc = qphy->pcs_misc; 1884 + void __iomem *pcs = qmp->pcs; 1885 + void __iomem *pcs_misc = qmp->pcs_misc; 1856 1886 1857 1887 if (!tables) 1858 1888 return; ··· 1863 1893 1864 1894 static int qmp_pcie_init(struct phy *phy) 1865 1895 { 1866 - struct qmp_phy *qphy = phy_get_drvdata(phy); 1867 - struct qcom_qmp *qmp = qphy->qmp; 1868 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1896 + struct qmp_pcie *qmp = phy_get_drvdata(phy); 1897 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1869 1898 int ret; 1870 1899 1871 1900 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); ··· 1901 1932 1902 1933 static int qmp_pcie_exit(struct phy *phy) 1903 1934 { 1904 - struct qmp_phy *qphy = phy_get_drvdata(phy); 1905 - struct qcom_qmp *qmp = qphy->qmp; 1906 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1935 + struct qmp_pcie *qmp = phy_get_drvdata(phy); 1936 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1907 1937 1908 1938 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1909 1939 ··· 1915 1947 1916 1948 static int qmp_pcie_power_on(struct phy *phy) 1917 1949 { 1918 - struct qmp_phy *qphy = phy_get_drvdata(phy); 1919 - struct qcom_qmp *qmp = qphy->qmp; 1920 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1950 + struct qmp_pcie *qmp = phy_get_drvdata(phy); 1951 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1921 1952 const struct qmp_phy_cfg_tables *mode_tables; 1922 - void __iomem *pcs = qphy->pcs; 1953 + void __iomem *pcs = qmp->pcs; 1923 1954 void __iomem *status; 1924 1955 unsigned int mask, val; 1925 1956 int ret; ··· 1926 1959 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1927 1960 cfg->pwrdn_ctrl); 1928 1961 1929 - if (qphy->mode == PHY_MODE_PCIE_RC) 1962 + if (qmp->mode == PHY_MODE_PCIE_RC) 1930 1963 mode_tables = cfg->tables_rc; 1931 1964 else 1932 1965 mode_tables = cfg->tables_ep; 1933 1966 1934 - qmp_pcie_serdes_init(qphy, &cfg->tables); 1935 - qmp_pcie_serdes_init(qphy, mode_tables); 1967 + qmp_pcie_serdes_init(qmp, &cfg->tables); 1968 + qmp_pcie_serdes_init(qmp, mode_tables); 1936 1969 1937 - ret = clk_prepare_enable(qphy->pipe_clk); 1970 + ret = clk_prepare_enable(qmp->pipe_clk); 1938 1971 if (ret) { 1939 1972 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1940 1973 return ret; 1941 1974 } 1942 1975 1943 1976 /* Tx, Rx, and PCS configurations */ 1944 - qmp_pcie_lanes_init(qphy, &cfg->tables); 1945 - qmp_pcie_lanes_init(qphy, mode_tables); 1977 + qmp_pcie_lanes_init(qmp, &cfg->tables); 1978 + qmp_pcie_lanes_init(qmp, mode_tables); 1946 1979 1947 - qmp_pcie_pcs_init(qphy, &cfg->tables); 1948 - qmp_pcie_pcs_init(qphy, mode_tables); 1980 + qmp_pcie_pcs_init(qmp, &cfg->tables); 1981 + qmp_pcie_pcs_init(qmp, mode_tables); 1949 1982 1950 1983 /* Pull PHY out of reset state */ 1951 1984 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ··· 1968 2001 return 0; 1969 2002 1970 2003 err_disable_pipe_clk: 1971 - clk_disable_unprepare(qphy->pipe_clk); 2004 + clk_disable_unprepare(qmp->pipe_clk); 1972 2005 1973 2006 return ret; 1974 2007 } 1975 2008 1976 2009 static int qmp_pcie_power_off(struct phy *phy) 1977 2010 { 1978 - struct qmp_phy *qphy = phy_get_drvdata(phy); 1979 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2011 + struct qmp_pcie *qmp = phy_get_drvdata(phy); 2012 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1980 2013 1981 - clk_disable_unprepare(qphy->pipe_clk); 2014 + clk_disable_unprepare(qmp->pipe_clk); 1982 2015 1983 2016 /* PHY reset */ 1984 - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2017 + qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1985 2018 1986 2019 /* stop SerDes and Phy-Coding-Sublayer */ 1987 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], 2020 + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 1988 2021 SERDES_START | PCS_START); 1989 2022 1990 2023 /* Put PHY into POWER DOWN state: active low */ 1991 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2024 + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1992 2025 cfg->pwrdn_ctrl); 1993 2026 1994 2027 return 0; ··· 2022 2055 2023 2056 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2024 2057 { 2025 - struct qmp_phy *qphy = phy_get_drvdata(phy); 2058 + struct qmp_pcie *qmp = phy_get_drvdata(phy); 2026 2059 2027 2060 switch (submode) { 2028 2061 case PHY_MODE_PCIE_RC: 2029 2062 case PHY_MODE_PCIE_EP: 2030 - qphy->mode = submode; 2063 + qmp->mode = submode; 2031 2064 break; 2032 2065 default: 2033 2066 dev_err(&phy->dev, "Unsupported submode %d\n", submode); ··· 2039 2072 2040 2073 static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2041 2074 { 2042 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2075 + struct qmp_pcie *qmp = dev_get_drvdata(dev); 2043 2076 int num = cfg->num_vregs; 2044 2077 int i; 2045 2078 ··· 2055 2088 2056 2089 static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2057 2090 { 2058 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2091 + struct qmp_pcie *qmp = dev_get_drvdata(dev); 2059 2092 int i; 2060 2093 int ret; 2061 2094 ··· 2076 2109 2077 2110 static int qmp_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2078 2111 { 2079 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2112 + struct qmp_pcie *qmp = dev_get_drvdata(dev); 2080 2113 int num = cfg->num_clks; 2081 2114 int i; 2082 2115 ··· 2113 2146 * clk | +-------+ | +-----+ 2114 2147 * +---------------+ 2115 2148 */ 2116 - static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2149 + static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) 2117 2150 { 2118 2151 struct clk_fixed_rate *fixed; 2119 2152 struct clk_init_data init = { }; ··· 2135 2168 * Controllers using QMP PHY-s use 125MHz pipe clock interface 2136 2169 * unless other frequency is specified in the PHY config. 2137 2170 */ 2138 - if (qmp->phys[0]->cfg->pipe_clock_rate) 2139 - fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; 2171 + if (qmp->cfg->pipe_clock_rate) 2172 + fixed->fixed_rate = qmp->cfg->pipe_clock_rate; 2140 2173 else 2141 2174 fixed->fixed_rate = 125000000; 2142 2175 ··· 2164 2197 .owner = THIS_MODULE, 2165 2198 }; 2166 2199 2167 - static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, 2200 + static int qmp_pcie_create(struct device *dev, struct device_node *np, 2168 2201 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2169 2202 { 2170 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2203 + struct qmp_pcie *qmp = dev_get_drvdata(dev); 2171 2204 struct phy *generic_phy; 2172 - struct qmp_phy *qphy; 2173 2205 int ret; 2174 2206 2175 - qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2176 - if (!qphy) 2177 - return -ENOMEM; 2207 + qmp->mode = PHY_MODE_PCIE_RC; 2178 2208 2179 - qphy->mode = PHY_MODE_PCIE_RC; 2209 + qmp->cfg = cfg; 2210 + qmp->serdes = serdes; 2180 2211 2181 - qphy->cfg = cfg; 2182 - qphy->serdes = serdes; 2183 2212 /* 2184 2213 * Get memory resources for the PHY: 2185 2214 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2186 2215 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2187 2216 * For single lane PHYs: pcs_misc (optional) -> 3. 2188 2217 */ 2189 - qphy->tx = devm_of_iomap(dev, np, 0, NULL); 2190 - if (IS_ERR(qphy->tx)) 2191 - return PTR_ERR(qphy->tx); 2218 + qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2219 + if (IS_ERR(qmp->tx)) 2220 + return PTR_ERR(qmp->tx); 2192 2221 2193 2222 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 2194 - qphy->rx = qphy->tx; 2223 + qmp->rx = qmp->tx; 2195 2224 else 2196 - qphy->rx = devm_of_iomap(dev, np, 1, NULL); 2197 - if (IS_ERR(qphy->rx)) 2198 - return PTR_ERR(qphy->rx); 2225 + qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2226 + if (IS_ERR(qmp->rx)) 2227 + return PTR_ERR(qmp->rx); 2199 2228 2200 - qphy->pcs = devm_of_iomap(dev, np, 2, NULL); 2201 - if (IS_ERR(qphy->pcs)) 2202 - return PTR_ERR(qphy->pcs); 2229 + qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 2230 + if (IS_ERR(qmp->pcs)) 2231 + return PTR_ERR(qmp->pcs); 2203 2232 2204 2233 if (cfg->lanes >= 2) { 2205 - qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); 2206 - if (IS_ERR(qphy->tx2)) 2207 - return PTR_ERR(qphy->tx2); 2234 + qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2235 + if (IS_ERR(qmp->tx2)) 2236 + return PTR_ERR(qmp->tx2); 2208 2237 2209 - qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); 2210 - if (IS_ERR(qphy->rx2)) 2211 - return PTR_ERR(qphy->rx2); 2238 + qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2239 + if (IS_ERR(qmp->rx2)) 2240 + return PTR_ERR(qmp->rx2); 2212 2241 2213 - qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2242 + qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2214 2243 } else { 2215 - qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2244 + qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2216 2245 } 2217 2246 2218 - if (IS_ERR(qphy->pcs_misc) && 2247 + if (IS_ERR(qmp->pcs_misc) && 2219 2248 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 2220 - qphy->pcs_misc = qphy->pcs + 0x400; 2249 + qmp->pcs_misc = qmp->pcs + 0x400; 2221 2250 2222 - if (IS_ERR(qphy->pcs_misc)) { 2251 + if (IS_ERR(qmp->pcs_misc)) { 2223 2252 if (cfg->tables.pcs_misc || 2224 2253 (cfg->tables_rc && cfg->tables_rc->pcs_misc) || 2225 - (cfg->tables_ep && cfg->tables_ep->pcs_misc)) 2226 - return PTR_ERR(qphy->pcs_misc); 2254 + (cfg->tables_ep && cfg->tables_ep->pcs_misc)) { 2255 + return PTR_ERR(qmp->pcs_misc); 2256 + } 2227 2257 } 2228 2258 2229 - qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2230 - if (IS_ERR(qphy->pipe_clk)) { 2231 - return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 2232 - "failed to get lane%d pipe clock\n", id); 2259 + qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2260 + if (IS_ERR(qmp->pipe_clk)) { 2261 + return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2262 + "failed to get pipe clock\n"); 2233 2263 } 2234 2264 2235 2265 generic_phy = devm_phy_create(dev, np, &qmp_pcie_ops); 2236 2266 if (IS_ERR(generic_phy)) { 2237 2267 ret = PTR_ERR(generic_phy); 2238 - dev_err(dev, "failed to create qphy %d\n", ret); 2268 + dev_err(dev, "failed to create PHY: %d\n", ret); 2239 2269 return ret; 2240 2270 } 2241 2271 2242 - qphy->phy = generic_phy; 2243 - qphy->qmp = qmp; 2244 - qmp->phys[id] = qphy; 2245 - phy_set_drvdata(generic_phy, qphy); 2272 + qmp->phy = generic_phy; 2273 + phy_set_drvdata(generic_phy, qmp); 2246 2274 2247 2275 return 0; 2248 2276 } 2249 2277 2250 2278 static int qmp_pcie_probe(struct platform_device *pdev) 2251 2279 { 2252 - struct qcom_qmp *qmp; 2253 2280 struct device *dev = &pdev->dev; 2254 2281 struct device_node *child; 2255 2282 struct phy_provider *phy_provider; 2256 2283 void __iomem *serdes; 2257 2284 const struct qmp_phy_cfg *cfg = NULL; 2285 + struct qmp_pcie *qmp; 2258 2286 int num, id; 2259 2287 int ret; 2260 2288 ··· 2288 2326 if (num > 1) 2289 2327 return -EINVAL; 2290 2328 2291 - qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2292 - if (!qmp->phys) 2293 - return -ENOMEM; 2294 - 2295 2329 id = 0; 2296 2330 for_each_available_child_of_node(dev->of_node, child) { 2297 2331 /* Create per-lane phy */ 2298 - ret = qmp_pcie_create(dev, child, id, serdes, cfg); 2332 + ret = qmp_pcie_create(dev, child, serdes, cfg); 2299 2333 if (ret) { 2300 2334 dev_err(dev, "failed to create lane%d phy, %d\n", 2301 2335 id, ret);