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clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS on SM8150

QUPv3 clocks support DFS and thus register the RCGs which require
support for the same.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240111-sm8150-dfs-support-v2-1-6edb44c83d3b@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Satya Priya Kakitapalli and committed by
Bjorn Andersson 2ff787e3 1d9054e3

+209 -140
+209 -140
drivers/clk/qcom/gcc-sm8150.c
··· 453 453 { } 454 454 }; 455 455 456 + static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 457 + .name = "gcc_qupv3_wrap0_s0_clk_src", 458 + .parent_data = gcc_parents_0, 459 + .num_parents = ARRAY_SIZE(gcc_parents_0), 460 + .flags = CLK_SET_RATE_PARENT, 461 + .ops = &clk_rcg2_ops, 462 + }; 463 + 456 464 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 457 465 .cmd_rcgr = 0x17148, 458 466 .mnd_width = 16, 459 467 .hid_width = 5, 460 468 .parent_map = gcc_parent_map_0, 461 469 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 462 - .clkr.hw.init = &(struct clk_init_data){ 463 - .name = "gcc_qupv3_wrap0_s0_clk_src", 464 - .parent_data = gcc_parents_0, 465 - .num_parents = ARRAY_SIZE(gcc_parents_0), 466 - .flags = CLK_SET_RATE_PARENT, 467 - .ops = &clk_rcg2_ops, 468 - }, 470 + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 471 + }; 472 + 473 + static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 474 + .name = "gcc_qupv3_wrap0_s1_clk_src", 475 + .parent_data = gcc_parents_0, 476 + .num_parents = ARRAY_SIZE(gcc_parents_0), 477 + .flags = CLK_SET_RATE_PARENT, 478 + .ops = &clk_rcg2_ops, 469 479 }; 470 480 471 481 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { ··· 484 474 .hid_width = 5, 485 475 .parent_map = gcc_parent_map_0, 486 476 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 487 - .clkr.hw.init = &(struct clk_init_data){ 488 - .name = "gcc_qupv3_wrap0_s1_clk_src", 489 - .parent_data = gcc_parents_0, 490 - .num_parents = ARRAY_SIZE(gcc_parents_0), 491 - .flags = CLK_SET_RATE_PARENT, 492 - .ops = &clk_rcg2_ops, 493 - }, 477 + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 478 + }; 479 + 480 + static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 481 + .name = "gcc_qupv3_wrap0_s2_clk_src", 482 + .parent_data = gcc_parents_0, 483 + .num_parents = ARRAY_SIZE(gcc_parents_0), 484 + .flags = CLK_SET_RATE_PARENT, 485 + .ops = &clk_rcg2_ops, 494 486 }; 495 487 496 488 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { ··· 501 489 .hid_width = 5, 502 490 .parent_map = gcc_parent_map_0, 503 491 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 504 - .clkr.hw.init = &(struct clk_init_data){ 505 - .name = "gcc_qupv3_wrap0_s2_clk_src", 506 - .parent_data = gcc_parents_0, 507 - .num_parents = ARRAY_SIZE(gcc_parents_0), 508 - .flags = CLK_SET_RATE_PARENT, 509 - .ops = &clk_rcg2_ops, 510 - }, 492 + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 493 + }; 494 + 495 + static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 496 + .name = "gcc_qupv3_wrap0_s3_clk_src", 497 + .parent_data = gcc_parents_0, 498 + .num_parents = ARRAY_SIZE(gcc_parents_0), 499 + .flags = CLK_SET_RATE_PARENT, 500 + .ops = &clk_rcg2_ops, 511 501 }; 512 502 513 503 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { ··· 518 504 .hid_width = 5, 519 505 .parent_map = gcc_parent_map_0, 520 506 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 521 - .clkr.hw.init = &(struct clk_init_data){ 522 - .name = "gcc_qupv3_wrap0_s3_clk_src", 523 - .parent_data = gcc_parents_0, 524 - .num_parents = ARRAY_SIZE(gcc_parents_0), 525 - .flags = CLK_SET_RATE_PARENT, 526 - .ops = &clk_rcg2_ops, 527 - }, 507 + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 508 + }; 509 + 510 + static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 511 + .name = "gcc_qupv3_wrap0_s4_clk_src", 512 + .parent_data = gcc_parents_0, 513 + .num_parents = ARRAY_SIZE(gcc_parents_0), 514 + .flags = CLK_SET_RATE_PARENT, 515 + .ops = &clk_rcg2_ops, 528 516 }; 529 517 530 518 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { ··· 535 519 .hid_width = 5, 536 520 .parent_map = gcc_parent_map_0, 537 521 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 538 - .clkr.hw.init = &(struct clk_init_data){ 539 - .name = "gcc_qupv3_wrap0_s4_clk_src", 540 - .parent_data = gcc_parents_0, 541 - .num_parents = ARRAY_SIZE(gcc_parents_0), 542 - .flags = CLK_SET_RATE_PARENT, 543 - .ops = &clk_rcg2_ops, 544 - }, 522 + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 523 + }; 524 + 525 + static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 526 + .name = "gcc_qupv3_wrap0_s5_clk_src", 527 + .parent_data = gcc_parents_0, 528 + .num_parents = ARRAY_SIZE(gcc_parents_0), 529 + .flags = CLK_SET_RATE_PARENT, 530 + .ops = &clk_rcg2_ops, 545 531 }; 546 532 547 533 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { ··· 552 534 .hid_width = 5, 553 535 .parent_map = gcc_parent_map_0, 554 536 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 555 - .clkr.hw.init = &(struct clk_init_data){ 556 - .name = "gcc_qupv3_wrap0_s5_clk_src", 557 - .parent_data = gcc_parents_0, 558 - .num_parents = ARRAY_SIZE(gcc_parents_0), 559 - .flags = CLK_SET_RATE_PARENT, 560 - .ops = &clk_rcg2_ops, 561 - }, 537 + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 538 + }; 539 + 540 + static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 541 + .name = "gcc_qupv3_wrap0_s6_clk_src", 542 + .parent_data = gcc_parents_0, 543 + .num_parents = ARRAY_SIZE(gcc_parents_0), 544 + .flags = CLK_SET_RATE_PARENT, 545 + .ops = &clk_rcg2_ops, 562 546 }; 563 547 564 548 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { ··· 569 549 .hid_width = 5, 570 550 .parent_map = gcc_parent_map_0, 571 551 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 572 - .clkr.hw.init = &(struct clk_init_data){ 573 - .name = "gcc_qupv3_wrap0_s6_clk_src", 574 - .parent_data = gcc_parents_0, 575 - .num_parents = ARRAY_SIZE(gcc_parents_0), 576 - .flags = CLK_SET_RATE_PARENT, 577 - .ops = &clk_rcg2_ops, 578 - }, 552 + .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 553 + }; 554 + 555 + static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 556 + .name = "gcc_qupv3_wrap0_s7_clk_src", 557 + .parent_data = gcc_parents_0, 558 + .num_parents = ARRAY_SIZE(gcc_parents_0), 559 + .flags = CLK_SET_RATE_PARENT, 560 + .ops = &clk_rcg2_ops, 579 561 }; 580 562 581 563 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { ··· 586 564 .hid_width = 5, 587 565 .parent_map = gcc_parent_map_0, 588 566 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 589 - .clkr.hw.init = &(struct clk_init_data){ 590 - .name = "gcc_qupv3_wrap0_s7_clk_src", 591 - .parent_data = gcc_parents_0, 592 - .num_parents = ARRAY_SIZE(gcc_parents_0), 593 - .flags = CLK_SET_RATE_PARENT, 594 - .ops = &clk_rcg2_ops, 595 - }, 567 + .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 568 + }; 569 + 570 + static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 571 + .name = "gcc_qupv3_wrap1_s0_clk_src", 572 + .parent_data = gcc_parents_0, 573 + .num_parents = ARRAY_SIZE(gcc_parents_0), 574 + .flags = CLK_SET_RATE_PARENT, 575 + .ops = &clk_rcg2_ops, 596 576 }; 597 577 598 578 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { ··· 603 579 .hid_width = 5, 604 580 .parent_map = gcc_parent_map_0, 605 581 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 606 - .clkr.hw.init = &(struct clk_init_data){ 607 - .name = "gcc_qupv3_wrap1_s0_clk_src", 608 - .parent_data = gcc_parents_0, 609 - .num_parents = ARRAY_SIZE(gcc_parents_0), 610 - .flags = CLK_SET_RATE_PARENT, 611 - .ops = &clk_rcg2_ops, 612 - }, 582 + .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 583 + }; 584 + 585 + static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 586 + .name = "gcc_qupv3_wrap1_s1_clk_src", 587 + .parent_data = gcc_parents_0, 588 + .num_parents = ARRAY_SIZE(gcc_parents_0), 589 + .flags = CLK_SET_RATE_PARENT, 590 + .ops = &clk_rcg2_ops, 613 591 }; 614 592 615 593 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { ··· 620 594 .hid_width = 5, 621 595 .parent_map = gcc_parent_map_0, 622 596 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 623 - .clkr.hw.init = &(struct clk_init_data){ 624 - .name = "gcc_qupv3_wrap1_s1_clk_src", 625 - .parent_data = gcc_parents_0, 626 - .num_parents = ARRAY_SIZE(gcc_parents_0), 627 - .flags = CLK_SET_RATE_PARENT, 628 - .ops = &clk_rcg2_ops, 629 - }, 597 + .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 598 + }; 599 + 600 + static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 601 + .name = "gcc_qupv3_wrap1_s2_clk_src", 602 + .parent_data = gcc_parents_0, 603 + .num_parents = ARRAY_SIZE(gcc_parents_0), 604 + .flags = CLK_SET_RATE_PARENT, 605 + .ops = &clk_rcg2_ops, 630 606 }; 631 607 632 608 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { ··· 637 609 .hid_width = 5, 638 610 .parent_map = gcc_parent_map_0, 639 611 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 640 - .clkr.hw.init = &(struct clk_init_data){ 641 - .name = "gcc_qupv3_wrap1_s2_clk_src", 642 - .parent_data = gcc_parents_0, 643 - .num_parents = ARRAY_SIZE(gcc_parents_0), 644 - .flags = CLK_SET_RATE_PARENT, 645 - .ops = &clk_rcg2_ops, 646 - }, 612 + .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 613 + }; 614 + 615 + static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 616 + .name = "gcc_qupv3_wrap1_s3_clk_src", 617 + .parent_data = gcc_parents_0, 618 + .num_parents = ARRAY_SIZE(gcc_parents_0), 619 + .flags = CLK_SET_RATE_PARENT, 620 + .ops = &clk_rcg2_ops, 647 621 }; 648 622 649 623 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { ··· 654 624 .hid_width = 5, 655 625 .parent_map = gcc_parent_map_0, 656 626 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 657 - .clkr.hw.init = &(struct clk_init_data){ 658 - .name = "gcc_qupv3_wrap1_s3_clk_src", 659 - .parent_data = gcc_parents_0, 660 - .num_parents = ARRAY_SIZE(gcc_parents_0), 661 - .flags = CLK_SET_RATE_PARENT, 662 - .ops = &clk_rcg2_ops, 663 - }, 627 + .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 628 + }; 629 + 630 + static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 631 + .name = "gcc_qupv3_wrap1_s4_clk_src", 632 + .parent_data = gcc_parents_0, 633 + .num_parents = ARRAY_SIZE(gcc_parents_0), 634 + .flags = CLK_SET_RATE_PARENT, 635 + .ops = &clk_rcg2_ops, 664 636 }; 665 637 666 638 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { ··· 671 639 .hid_width = 5, 672 640 .parent_map = gcc_parent_map_0, 673 641 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 674 - .clkr.hw.init = &(struct clk_init_data){ 675 - .name = "gcc_qupv3_wrap1_s4_clk_src", 676 - .parent_data = gcc_parents_0, 677 - .num_parents = ARRAY_SIZE(gcc_parents_0), 678 - .flags = CLK_SET_RATE_PARENT, 679 - .ops = &clk_rcg2_ops, 680 - }, 642 + .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 643 + }; 644 + 645 + static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 646 + .name = "gcc_qupv3_wrap1_s5_clk_src", 647 + .parent_data = gcc_parents_0, 648 + .num_parents = ARRAY_SIZE(gcc_parents_0), 649 + .flags = CLK_SET_RATE_PARENT, 650 + .ops = &clk_rcg2_ops, 681 651 }; 682 652 683 653 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { ··· 688 654 .hid_width = 5, 689 655 .parent_map = gcc_parent_map_0, 690 656 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 691 - .clkr.hw.init = &(struct clk_init_data){ 692 - .name = "gcc_qupv3_wrap1_s5_clk_src", 693 - .parent_data = gcc_parents_0, 694 - .num_parents = ARRAY_SIZE(gcc_parents_0), 695 - .flags = CLK_SET_RATE_PARENT, 696 - .ops = &clk_rcg2_ops, 697 - }, 657 + .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 658 + }; 659 + 660 + static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 661 + .name = "gcc_qupv3_wrap2_s0_clk_src", 662 + .parent_data = gcc_parents_0, 663 + .num_parents = ARRAY_SIZE(gcc_parents_0), 664 + .flags = CLK_SET_RATE_PARENT, 665 + .ops = &clk_rcg2_ops, 698 666 }; 699 667 700 668 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { ··· 705 669 .hid_width = 5, 706 670 .parent_map = gcc_parent_map_0, 707 671 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 708 - .clkr.hw.init = &(struct clk_init_data){ 709 - .name = "gcc_qupv3_wrap2_s0_clk_src", 710 - .parent_data = gcc_parents_0, 711 - .num_parents = ARRAY_SIZE(gcc_parents_0), 712 - .flags = CLK_SET_RATE_PARENT, 713 - .ops = &clk_rcg2_ops, 714 - }, 672 + .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 673 + }; 674 + 675 + static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 676 + .name = "gcc_qupv3_wrap2_s1_clk_src", 677 + .parent_data = gcc_parents_0, 678 + .num_parents = ARRAY_SIZE(gcc_parents_0), 679 + .flags = CLK_SET_RATE_PARENT, 680 + .ops = &clk_rcg2_ops, 715 681 }; 716 682 717 683 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { ··· 722 684 .hid_width = 5, 723 685 .parent_map = gcc_parent_map_0, 724 686 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 725 - .clkr.hw.init = &(struct clk_init_data){ 726 - .name = "gcc_qupv3_wrap2_s1_clk_src", 727 - .parent_data = gcc_parents_0, 728 - .num_parents = ARRAY_SIZE(gcc_parents_0), 729 - .flags = CLK_SET_RATE_PARENT, 730 - .ops = &clk_rcg2_ops, 731 - }, 687 + .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 688 + }; 689 + 690 + static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 691 + .name = "gcc_qupv3_wrap2_s2_clk_src", 692 + .parent_data = gcc_parents_0, 693 + .num_parents = ARRAY_SIZE(gcc_parents_0), 694 + .flags = CLK_SET_RATE_PARENT, 695 + .ops = &clk_rcg2_ops, 732 696 }; 733 697 734 698 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { ··· 739 699 .hid_width = 5, 740 700 .parent_map = gcc_parent_map_0, 741 701 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 742 - .clkr.hw.init = &(struct clk_init_data){ 743 - .name = "gcc_qupv3_wrap2_s2_clk_src", 744 - .parent_data = gcc_parents_0, 745 - .num_parents = ARRAY_SIZE(gcc_parents_0), 746 - .flags = CLK_SET_RATE_PARENT, 747 - .ops = &clk_rcg2_ops, 748 - }, 702 + .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 703 + }; 704 + 705 + static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 706 + .name = "gcc_qupv3_wrap2_s3_clk_src", 707 + .parent_data = gcc_parents_0, 708 + .num_parents = ARRAY_SIZE(gcc_parents_0), 709 + .flags = CLK_SET_RATE_PARENT, 710 + .ops = &clk_rcg2_ops, 749 711 }; 750 712 751 713 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { ··· 756 714 .hid_width = 5, 757 715 .parent_map = gcc_parent_map_0, 758 716 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 759 - .clkr.hw.init = &(struct clk_init_data){ 760 - .name = "gcc_qupv3_wrap2_s3_clk_src", 761 - .parent_data = gcc_parents_0, 762 - .num_parents = ARRAY_SIZE(gcc_parents_0), 763 - .flags = CLK_SET_RATE_PARENT, 764 - .ops = &clk_rcg2_ops, 765 - }, 717 + .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 718 + }; 719 + 720 + static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 721 + .name = "gcc_qupv3_wrap2_s4_clk_src", 722 + .parent_data = gcc_parents_0, 723 + .num_parents = ARRAY_SIZE(gcc_parents_0), 724 + .flags = CLK_SET_RATE_PARENT, 725 + .ops = &clk_rcg2_ops, 766 726 }; 767 727 768 728 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { ··· 773 729 .hid_width = 5, 774 730 .parent_map = gcc_parent_map_0, 775 731 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 776 - .clkr.hw.init = &(struct clk_init_data){ 777 - .name = "gcc_qupv3_wrap2_s4_clk_src", 778 - .parent_data = gcc_parents_0, 779 - .num_parents = ARRAY_SIZE(gcc_parents_0), 780 - .flags = CLK_SET_RATE_PARENT, 781 - .ops = &clk_rcg2_ops, 782 - }, 732 + .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 733 + }; 734 + 735 + static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 736 + .name = "gcc_qupv3_wrap2_s5_clk_src", 737 + .parent_data = gcc_parents_0, 738 + .num_parents = ARRAY_SIZE(gcc_parents_0), 739 + .flags = CLK_SET_RATE_PARENT, 740 + .ops = &clk_rcg2_ops, 783 741 }; 784 742 785 743 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { ··· 790 744 .hid_width = 5, 791 745 .parent_map = gcc_parent_map_0, 792 746 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 793 - .clkr.hw.init = &(struct clk_init_data){ 794 - .name = "gcc_qupv3_wrap2_s5_clk_src", 795 - .parent_data = gcc_parents_0, 796 - .num_parents = ARRAY_SIZE(gcc_parents_0), 797 - .flags = CLK_SET_RATE_PARENT, 798 - .ops = &clk_rcg2_ops, 799 - }, 747 + .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 800 748 }; 801 749 802 750 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { ··· 3790 3750 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 3791 3751 }; 3792 3752 3753 + static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3754 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3755 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3756 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3757 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3758 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3759 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3760 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 3761 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 3762 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3763 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3764 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3765 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3766 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3767 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3768 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3769 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3770 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3771 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3772 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3773 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3774 + }; 3775 + 3793 3776 static const struct regmap_config gcc_sm8150_regmap_config = { 3794 3777 .reg_bits = 32, 3795 3778 .reg_stride = 4, ··· 3840 3777 static int gcc_sm8150_probe(struct platform_device *pdev) 3841 3778 { 3842 3779 struct regmap *regmap; 3780 + int ret; 3843 3781 3844 3782 regmap = qcom_cc_map(pdev, &gcc_sm8150_desc); 3845 3783 if (IS_ERR(regmap)) ··· 3849 3785 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ 3850 3786 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 3851 3787 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3788 + 3789 + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3790 + ARRAY_SIZE(gcc_dfs_clocks)); 3791 + if (ret) 3792 + dev_err_probe(&pdev->dev, ret, "Failed to register with DFS!\n"); 3852 3793 3853 3794 return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap); 3854 3795 }