Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: stop joining VM PTE updates
This isn't beneficial any more since VRAM allocations are now split
so that they fits into a single page table.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Christian König
and committed by
Alex Deucher
301654a4
53e2e91d
+7
-54
+7
-54
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+7
-54
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
···
1163
1163
struct amdgpu_device *adev = params->adev;
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const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
1165
1165
1166
-
uint64_t cur_pe_start, cur_nptes, cur_dst;
1167
-
uint64_t addr; /* next GPU address to be updated */
1166
+
uint64_t addr, pe_start;
1168
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struct amdgpu_bo *pt;
1169
-
unsigned nptes; /* next number of ptes to be updated */
1170
-
uint64_t next_pe_start;
1171
-
1172
-
/* initialize the variables */
1173
-
addr = start;
1174
-
pt = amdgpu_vm_get_pt(params, addr);
1175
-
if (!pt) {
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-
pr_err("PT not found, aborting update_ptes\n");
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-
return -EINVAL;
1178
-
}
1179
-
1180
-
if (params->shadow) {
1181
-
if (!pt->shadow)
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-
return 0;
1183
-
pt = pt->shadow;
1184
-
}
1185
-
if ((addr & ~mask) == (end & ~mask))
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-
nptes = end - addr;
1187
-
else
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-
nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
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-
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-
cur_pe_start = amdgpu_bo_gpu_offset(pt);
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-
cur_pe_start += (addr & mask) * 8;
1192
-
cur_nptes = nptes;
1193
-
cur_dst = dst;
1194
-
1195
-
/* for next ptb*/
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-
addr += nptes;
1197
-
dst += nptes * AMDGPU_GPU_PAGE_SIZE;
1168
+
unsigned nptes;
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/* walk over the address space and update the page tables */
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-
while (addr < end) {
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+
for (addr = start; addr < end; addr += nptes) {
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pt = amdgpu_vm_get_pt(params, addr);
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if (!pt) {
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pr_err("PT not found, aborting update_ptes\n");
···
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else
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nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
1188
1217
1189
-
next_pe_start = amdgpu_bo_gpu_offset(pt);
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-
next_pe_start += (addr & mask) * 8;
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+
pe_start = amdgpu_bo_gpu_offset(pt);
1219
+
pe_start += (addr & mask) * 8;
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1192
-
if ((cur_pe_start + 8 * cur_nptes) == next_pe_start &&
1193
-
((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) {
1194
-
/* The next ptb is consecutive to current ptb.
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-
* Don't call the update function now.
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-
* Will update two ptbs together in future.
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-
*/
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-
cur_nptes += nptes;
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-
} else {
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-
params->func(params, cur_pe_start, cur_dst, cur_nptes,
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-
AMDGPU_GPU_PAGE_SIZE, flags);
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+
params->func(params, pe_start, dst, nptes,
1222
+
AMDGPU_GPU_PAGE_SIZE, flags);
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1203
-
cur_pe_start = next_pe_start;
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-
cur_nptes = nptes;
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-
cur_dst = dst;
1206
-
}
1207
-
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-
/* for next ptb*/
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-
addr += nptes;
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dst += nptes * AMDGPU_GPU_PAGE_SIZE;
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}
1212
-
1213
-
params->func(params, cur_pe_start, cur_dst, cur_nptes,
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-
AMDGPU_GPU_PAGE_SIZE, flags);
1215
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return 0;
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}