Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'gpio-fixes-for-v6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
Pull gpio fixes from Bartosz Golaszewski:
- fix a regression in pin access control in gpio-tegra186
- make data pointer dereference robust in Intel Tangier driver
* tag 'gpio-fixes-for-v6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux:
gpio: tegra186: Fix tegra186_gpio_is_accessible() check
gpio: tangier: Use correct type for the IRQ chip data
+17
-12
+6
-3
drivers/gpio/gpio-tangier.c
+6
-3
drivers/gpio/gpio-tangier.c
···
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static void tng_irq_ack(struct irq_data *d)
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{
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-
struct tng_gpio *priv = irq_data_get_irq_chip_data(d);
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+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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+
struct tng_gpio *priv = gpiochip_get_data(gc);
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irq_hw_number_t gpio = irqd_to_hwirq(d);
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void __iomem *gisr;
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u8 shift;
···
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static void tng_irq_mask(struct irq_data *d)
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{
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-
struct tng_gpio *priv = irq_data_get_irq_chip_data(d);
230
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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+
struct tng_gpio *priv = gpiochip_get_data(gc);
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irq_hw_number_t gpio = irqd_to_hwirq(d);
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tng_irq_unmask_mask(priv, gpio, false);
···
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static void tng_irq_unmask(struct irq_data *d)
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{
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-
struct tng_gpio *priv = irq_data_get_irq_chip_data(d);
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+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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+
struct tng_gpio *priv = gpiochip_get_data(gc);
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irq_hw_number_t gpio = irqd_to_hwirq(d);
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gpiochip_enable_irq(&priv->chip, gpio);
+11
-9
drivers/gpio/gpio-tegra186.c
+11
-9
drivers/gpio/gpio-tegra186.c
···
36
36
#define TEGRA186_GPIO_SCR_SEC_REN BIT(27)
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#define TEGRA186_GPIO_SCR_SEC_G1W BIT(9)
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#define TEGRA186_GPIO_SCR_SEC_G1R BIT(1)
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-
#define TEGRA186_GPIO_FULL_ACCESS (TEGRA186_GPIO_SCR_SEC_WEN | \
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-
TEGRA186_GPIO_SCR_SEC_REN | \
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-
TEGRA186_GPIO_SCR_SEC_G1R | \
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-
TEGRA186_GPIO_SCR_SEC_G1W)
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-
#define TEGRA186_GPIO_SCR_SEC_ENABLE (TEGRA186_GPIO_SCR_SEC_WEN | \
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-
TEGRA186_GPIO_SCR_SEC_REN)
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39
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40
/* control registers */
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41
#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
···
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value = __raw_readl(secure + TEGRA186_GPIO_SCR);
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-
if ((value & TEGRA186_GPIO_SCR_SEC_ENABLE) == 0)
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-
return true;
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+
/*
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+
* When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the
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+
* registers for given GPIO pin.
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+
* When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying
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+
* SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given
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+
* GPIO pin.
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+
*/
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-
if ((value & TEGRA186_GPIO_FULL_ACCESS) == TEGRA186_GPIO_FULL_ACCESS)
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+
if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 ||
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+
((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) &&
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+
((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 ||
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+
((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W))))
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192
return true;
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return false;