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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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stmmac: intel: Drop duplicate ID in the list of PCI device IDs

The PCI device IDs are defined with a prefix PCI_DEVICE_ID.
There is no need to repeat the ID part at the end of each definition.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Wong Vee Khee <vee.khee.wong@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Andy Shevchenko and committed by
David S. Miller 3036ec03 be107538

+30 -30
+30 -30
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
··· 1048 1048 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, 1049 1049 intel_eth_pci_resume); 1050 1050 1051 - #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937 1052 - #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30 1053 - #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31 1054 - #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32 1051 + #define PCI_DEVICE_ID_INTEL_QUARK 0x0937 1052 + #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30 1053 + #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G 0x4b31 1054 + #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32 1055 1055 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC 1056 1056 * which are named PSE0 and PSE1 1057 1057 */ 1058 - #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0 1059 - #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1 1060 - #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2 1061 - #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0 1062 - #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1 1063 - #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2 1064 - #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID 0x43ac 1065 - #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID 0x43a2 1066 - #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac 1067 - #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0_ID 0x7aac 1068 - #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1_ID 0x7aad 1058 + #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0 1059 + #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1 1060 + #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2 1061 + #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0 1062 + #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1 1063 + #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2 1064 + #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0 0x43ac 1065 + #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1 0x43a2 1066 + #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G 0xa0ac 1067 + #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0 0x7aac 1068 + #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1 0x7aad 1069 1069 1070 1070 static const struct pci_device_id intel_eth_pci_id_table[] = { 1071 - { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) }, 1072 - { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) }, 1073 - { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) }, 1074 - { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) }, 1075 - { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) }, 1076 - { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) }, 1077 - { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) }, 1078 - { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) }, 1079 - { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) }, 1080 - { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) }, 1081 - { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_phy0_info) }, 1082 - { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, &tgl_sgmii1g_phy0_info) }, 1083 - { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, &tgl_sgmii1g_phy1_info) }, 1084 - { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0_ID, &adls_sgmii1g_phy0_info) }, 1085 - { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1_ID, &adls_sgmii1g_phy1_info) }, 1071 + { PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) }, 1072 + { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) }, 1073 + { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) }, 1074 + { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) }, 1075 + { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) }, 1076 + { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) }, 1077 + { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) }, 1078 + { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) }, 1079 + { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) }, 1080 + { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) }, 1081 + { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) }, 1082 + { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) }, 1083 + { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) }, 1084 + { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) }, 1085 + { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) }, 1086 1086 {} 1087 1087 }; 1088 1088 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);