tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm-soc-fixes-v5.10-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
"Another set of patches for devicetree files and Arm SoC specific
drivers:

- A fix for OP-TEE shared memory on non-SMP systems

- multiple code fixes for the OMAP platform, including one regression
for the CPSW network driver and a few runtime warning fixes

- Some DT patches for the Rockchip RK3399 platform, in particular
fixing the MMC device ordering that recently became
nondeterministic with async probe.

- Multiple DT fixes for the Tegra platform, including a regression
fix for suspend/resume on TX2

- A regression fix for a user-triggered fault in the NXP dpio driver

- A regression fix for a bug caused by an earlier bug fix in the
xilinx firmware driver

- Two more DTC warning fixes

- Sylvain Lemieux steps down as maintainer for the NXP LPC32xx
platform"

* tag 'arm-soc-fixes-v5.10-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (24 commits)
arm64: tegra: Fix Tegra234 VDK node names
arm64: tegra: Wrong AON HSP reg property size
arm64: tegra: Fix USB_VBUS_EN0 regulator on Jetson TX1
arm64: tegra: Correct the UART for Jetson Xavier NX
arm64: tegra: Disable the ACONNECT for Jetson TX2
optee: add writeback to valid memory type
firmware: xilinx: Use hash-table for api feature check
firmware: xilinx: Fix SD DLL node reset issue
soc: fsl: dpio: Get the cpumask through cpumask_of(cpu)
ARM: dts: dra76x: m_can: fix order of clocks
bus: ti-sysc: suppress err msg for timers used as clockevent/source
MAINTAINERS: Remove myself as LPC32xx maintainers
arm64: dts: qcom: clear the warnings caused by empty dma-ranges
arm64: dts: broadcom: clear the warnings caused by empty dma-ranges
ARM: dts: am437x-l4: fix compatible for cpsw switch dt node
arm64: dts: rockchip: Reorder LED triggers from mmc devices on rk3399-roc-pc.
arm64: dts: rockchip: Assign a fixed index to mmc devices on rk3399 boards.
arm64: dts: rockchip: Remove system-power-controller from pmic on Odroid Go Advance
arm64: dts: rockchip: fix NanoPi R2S GMAC clock name
ARM: OMAP2+: Manage MPU state properly for omap_enter_idle_coupled()
...

Linus Torvalds 303bc934 79c0c1f0

+150 -119
-1
MAINTAINERS
··· 1995 1995 1996 1996 ARM/LPC32XX SOC SUPPORT 1997 1997 M: Vladimir Zapolskiy <vz@mleia.com> 1998 - M: Sylvain Lemieux <slemieux.tyco@gmail.com> 1999 1998 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 2000 1999 S: Maintained 2001 2000 T: git git://github.com/vzapolskiy/linux-lpc32xx.git
+1 -1
arch/arm/boot/dts/am437x-l4.dtsi
··· 521 521 ranges = <0x0 0x100000 0x8000>; 522 522 523 523 mac_sw: switch@0 { 524 - compatible = "ti,am4372-cpsw","ti,cpsw-switch"; 524 + compatible = "ti,am4372-cpsw-switch", "ti,cpsw-switch"; 525 525 reg = <0x0 0x4000>; 526 526 ranges = <0 0 0x4000>; 527 527 clocks = <&cpsw_125mhz_gclk>, <&dpll_clksel_mac_clk>;
+2 -2
arch/arm/boot/dts/dra76x.dtsi
··· 32 32 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 33 33 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 34 34 interrupt-names = "int0", "int1"; 35 - clocks = <&mcan_clk>, <&l3_iclk_div>; 36 - clock-names = "cclk", "hclk"; 35 + clocks = <&l3_iclk_div>, <&mcan_clk>; 36 + clock-names = "hclk", "cclk"; 37 37 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>; 38 38 }; 39 39 };
+2 -1
arch/arm/mach-omap2/Kconfig
··· 7 7 depends on ARCH_MULTI_V6 8 8 select ARCH_OMAP2PLUS 9 9 select CPU_V6 10 - select PM_GENERIC_DOMAINS if PM 11 10 select SOC_HAS_OMAP2_SDRC 12 11 13 12 config ARCH_OMAP3 ··· 105 106 select OMAP_DM_TIMER 106 107 select OMAP_GPMC 107 108 select PINCTRL 109 + select PM_GENERIC_DOMAINS if PM 110 + select PM_GENERIC_DOMAINS_OF if PM 108 111 select RESET_CONTROLLER 109 112 select SOC_BUS 110 113 select TI_SYSC
+5 -3
arch/arm/mach-omap2/cpuidle44xx.c
··· 175 175 if (mpuss_can_lose_context) { 176 176 error = cpu_cluster_pm_enter(); 177 177 if (error) { 178 - omap_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON); 179 - goto cpu_cluster_pm_out; 178 + index = 0; 179 + cx = state_ptr + index; 180 + pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state); 181 + omap_set_pwrdm_state(mpu_pd, cx->mpu_state); 182 + mpuss_can_lose_context = 0; 180 183 } 181 184 } 182 185 } ··· 187 184 omap4_enter_lowpower(dev->cpu, cx->cpu_state); 188 185 cpu_done[dev->cpu] = true; 189 186 190 - cpu_cluster_pm_out: 191 187 /* Wakeup CPU1 only if it is not offlined */ 192 188 if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) { 193 189
+10 -10
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi
··· 5 5 usb { 6 6 compatible = "simple-bus"; 7 7 dma-ranges; 8 - #address-cells = <1>; 9 - #size-cells = <1>; 10 - ranges = <0x0 0x0 0x68500000 0x00400000>; 8 + #address-cells = <2>; 9 + #size-cells = <2>; 10 + ranges = <0x0 0x0 0x0 0x68500000 0x0 0x00400000>; 11 11 12 12 usbphy0: usb-phy@0 { 13 13 compatible = "brcm,sr-usb-combo-phy"; 14 - reg = <0x00000000 0x100>; 14 + reg = <0x0 0x00000000 0x0 0x100>; 15 15 #phy-cells = <1>; 16 16 status = "disabled"; 17 17 }; 18 18 19 19 xhci0: usb@1000 { 20 20 compatible = "generic-xhci"; 21 - reg = <0x00001000 0x1000>; 21 + reg = <0x0 0x00001000 0x0 0x1000>; 22 22 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 23 23 phys = <&usbphy0 1>, <&usbphy0 0>; 24 24 phy-names = "phy0", "phy1"; ··· 28 28 29 29 bdc0: usb@2000 { 30 30 compatible = "brcm,bdc-v0.16"; 31 - reg = <0x00002000 0x1000>; 31 + reg = <0x0 0x00002000 0x0 0x1000>; 32 32 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 33 33 phys = <&usbphy0 0>, <&usbphy0 1>; 34 34 phy-names = "phy0", "phy1"; ··· 38 38 39 39 usbphy1: usb-phy@10000 { 40 40 compatible = "brcm,sr-usb-combo-phy"; 41 - reg = <0x00010000 0x100>; 41 + reg = <0x0 0x00010000 0x0 0x100>; 42 42 #phy-cells = <1>; 43 43 status = "disabled"; 44 44 }; 45 45 46 46 usbphy2: usb-phy@20000 { 47 47 compatible = "brcm,sr-usb-hs-phy"; 48 - reg = <0x00020000 0x100>; 48 + reg = <0x0 0x00020000 0x0 0x100>; 49 49 #phy-cells = <0>; 50 50 status = "disabled"; 51 51 }; 52 52 53 53 xhci1: usb@11000 { 54 54 compatible = "generic-xhci"; 55 - reg = <0x00011000 0x1000>; 55 + reg = <0x0 0x00011000 0x0 0x1000>; 56 56 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 57 57 phys = <&usbphy1 1>, <&usbphy2>, <&usbphy1 0>; 58 58 phy-names = "phy0", "phy1", "phy2"; ··· 62 62 63 63 bdc1: usb@21000 { 64 64 compatible = "brcm,bdc-v0.16"; 65 - reg = <0x00021000 0x1000>; 65 + reg = <0x0 0x00021000 0x0 0x1000>; 66 66 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 67 67 phys = <&usbphy2>; 68 68 phy-names = "phy0";
-12
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
··· 10 10 model = "NVIDIA Jetson TX2 Developer Kit"; 11 11 compatible = "nvidia,p2771-0000", "nvidia,tegra186"; 12 12 13 - aconnect { 14 - status = "okay"; 15 - 16 - dma-controller@2930000 { 17 - status = "okay"; 18 - }; 19 - 20 - interrupt-controller@2a40000 { 21 - status = "okay"; 22 - }; 23 - }; 24 - 25 13 i2c@3160000 { 26 14 power-monitor@42 { 27 15 compatible = "ti,ina3221";
+1 -1
arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi
··· 54 54 status = "okay"; 55 55 }; 56 56 57 - serial@c280000 { 57 + serial@3100000 { 58 58 status = "okay"; 59 59 }; 60 60
+1 -1
arch/arm64/boot/dts/nvidia/tegra194.dtsi
··· 1161 1161 1162 1162 hsp_aon: hsp@c150000 { 1163 1163 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1164 - reg = <0x0c150000 0xa0000>; 1164 + reg = <0x0c150000 0x90000>; 1165 1165 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1166 1166 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1167 1167 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+10 -10
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
··· 1663 1663 vin-supply = <&vdd_5v0_sys>; 1664 1664 }; 1665 1665 1666 - vdd_usb_vbus_otg: regulator@11 { 1667 - compatible = "regulator-fixed"; 1668 - regulator-name = "USB_VBUS_EN0"; 1669 - regulator-min-microvolt = <5000000>; 1670 - regulator-max-microvolt = <5000000>; 1671 - gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; 1672 - enable-active-high; 1673 - vin-supply = <&vdd_5v0_sys>; 1674 - }; 1675 - 1676 1666 vdd_hdmi: regulator@10 { 1677 1667 compatible = "regulator-fixed"; 1678 1668 regulator-name = "VDD_HDMI_5V0"; ··· 1701 1711 gpio = <&exp2 9 GPIO_ACTIVE_HIGH>; 1702 1712 enable-active-high; 1703 1713 vin-supply = <&vdd_3v3_sys>; 1714 + }; 1715 + 1716 + vdd_usb_vbus_otg: regulator@14 { 1717 + compatible = "regulator-fixed"; 1718 + regulator-name = "USB_VBUS_EN0"; 1719 + regulator-min-microvolt = <5000000>; 1720 + regulator-max-microvolt = <5000000>; 1721 + gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; 1722 + enable-active-high; 1723 + vin-supply = <&vdd_5v0_sys>; 1704 1724 }; 1705 1725 };
+3 -3
arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts
··· 8 8 compatible = "nvidia,tegra234-vdk", "nvidia,tegra234"; 9 9 10 10 aliases { 11 - sdhci3 = "/cbb@0/sdhci@3460000"; 11 + mmc3 = "/bus@0/mmc@3460000"; 12 12 serial0 = &uarta; 13 13 }; 14 14 ··· 17 17 stdout-path = "serial0:115200n8"; 18 18 }; 19 19 20 - cbb@0 { 20 + bus@0 { 21 21 serial@3100000 { 22 22 status = "okay"; 23 23 }; 24 24 25 - sdhci@3460000 { 25 + mmc@3460000 { 26 26 status = "okay"; 27 27 bus-width = <8>; 28 28 non-removable;
+36 -36
arch/arm64/boot/dts/qcom/ipq6018.dtsi
··· 179 179 }; 180 180 181 181 soc: soc { 182 - #address-cells = <1>; 183 - #size-cells = <1>; 184 - ranges = <0 0 0 0xffffffff>; 182 + #address-cells = <2>; 183 + #size-cells = <2>; 184 + ranges = <0 0 0 0 0x0 0xffffffff>; 185 185 dma-ranges; 186 186 compatible = "simple-bus"; 187 187 188 188 prng: qrng@e1000 { 189 189 compatible = "qcom,prng-ee"; 190 - reg = <0xe3000 0x1000>; 190 + reg = <0x0 0xe3000 0x0 0x1000>; 191 191 clocks = <&gcc GCC_PRNG_AHB_CLK>; 192 192 clock-names = "core"; 193 193 }; 194 194 195 195 cryptobam: dma@704000 { 196 196 compatible = "qcom,bam-v1.7.0"; 197 - reg = <0x00704000 0x20000>; 197 + reg = <0x0 0x00704000 0x0 0x20000>; 198 198 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 199 199 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 200 200 clock-names = "bam_clk"; ··· 206 206 207 207 crypto: crypto@73a000 { 208 208 compatible = "qcom,crypto-v5.1"; 209 - reg = <0x0073a000 0x6000>; 209 + reg = <0x0 0x0073a000 0x0 0x6000>; 210 210 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 211 211 <&gcc GCC_CRYPTO_AXI_CLK>, 212 212 <&gcc GCC_CRYPTO_CLK>; ··· 217 217 218 218 tlmm: pinctrl@1000000 { 219 219 compatible = "qcom,ipq6018-pinctrl"; 220 - reg = <0x01000000 0x300000>; 220 + reg = <0x0 0x01000000 0x0 0x300000>; 221 221 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 222 222 gpio-controller; 223 223 #gpio-cells = <2>; ··· 235 235 236 236 gcc: gcc@1800000 { 237 237 compatible = "qcom,gcc-ipq6018"; 238 - reg = <0x01800000 0x80000>; 238 + reg = <0x0 0x01800000 0x0 0x80000>; 239 239 clocks = <&xo>, <&sleep_clk>; 240 240 clock-names = "xo", "sleep_clk"; 241 241 #clock-cells = <1>; ··· 244 244 245 245 tcsr_mutex_regs: syscon@1905000 { 246 246 compatible = "syscon"; 247 - reg = <0x01905000 0x8000>; 247 + reg = <0x0 0x01905000 0x0 0x8000>; 248 248 }; 249 249 250 250 tcsr_q6: syscon@1945000 { 251 251 compatible = "syscon"; 252 - reg = <0x01945000 0xe000>; 252 + reg = <0x0 0x01945000 0x0 0xe000>; 253 253 }; 254 254 255 255 blsp_dma: dma@7884000 { 256 256 compatible = "qcom,bam-v1.7.0"; 257 - reg = <0x07884000 0x2b000>; 257 + reg = <0x0 0x07884000 0x0 0x2b000>; 258 258 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 259 259 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 260 260 clock-names = "bam_clk"; ··· 264 264 265 265 blsp1_uart3: serial@78b1000 { 266 266 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 267 - reg = <0x078b1000 0x200>; 267 + reg = <0x0 0x078b1000 0x0 0x200>; 268 268 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 269 269 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 270 270 <&gcc GCC_BLSP1_AHB_CLK>; ··· 276 276 compatible = "qcom,spi-qup-v2.2.1"; 277 277 #address-cells = <1>; 278 278 #size-cells = <0>; 279 - reg = <0x078b5000 0x600>; 279 + reg = <0x0 0x078b5000 0x0 0x600>; 280 280 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 281 281 spi-max-frequency = <50000000>; 282 282 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, ··· 291 291 compatible = "qcom,spi-qup-v2.2.1"; 292 292 #address-cells = <1>; 293 293 #size-cells = <0>; 294 - reg = <0x078b6000 0x600>; 294 + reg = <0x0 0x078b6000 0x0 0x600>; 295 295 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 296 296 spi-max-frequency = <50000000>; 297 297 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, ··· 306 306 compatible = "qcom,i2c-qup-v2.2.1"; 307 307 #address-cells = <1>; 308 308 #size-cells = <0>; 309 - reg = <0x078b6000 0x600>; 309 + reg = <0x0 0x078b6000 0x0 0x600>; 310 310 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 311 311 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 312 312 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; ··· 321 321 compatible = "qcom,i2c-qup-v2.2.1"; 322 322 #address-cells = <1>; 323 323 #size-cells = <0>; 324 - reg = <0x078b7000 0x600>; 324 + reg = <0x0 0x078b7000 0x0 0x600>; 325 325 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 326 326 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 327 327 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; ··· 336 336 compatible = "qcom,msm-qgic2"; 337 337 interrupt-controller; 338 338 #interrupt-cells = <0x3>; 339 - reg = <0x0b000000 0x1000>, /*GICD*/ 340 - <0x0b002000 0x1000>, /*GICC*/ 341 - <0x0b001000 0x1000>, /*GICH*/ 342 - <0x0b004000 0x1000>; /*GICV*/ 339 + reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ 340 + <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ 341 + <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ 342 + <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ 343 343 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 344 344 }; 345 345 346 346 watchdog@b017000 { 347 347 compatible = "qcom,kpss-wdt"; 348 348 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 349 - reg = <0x0b017000 0x40>; 349 + reg = <0x0 0x0b017000 0x0 0x40>; 350 350 clocks = <&sleep_clk>; 351 351 timeout-sec = <10>; 352 352 }; 353 353 354 354 apcs_glb: mailbox@b111000 { 355 355 compatible = "qcom,ipq6018-apcs-apps-global"; 356 - reg = <0x0b111000 0x1000>; 356 + reg = <0x0 0x0b111000 0x0 0x1000>; 357 357 #clock-cells = <1>; 358 358 clocks = <&a53pll>, <&xo>; 359 359 clock-names = "pll", "xo"; ··· 362 362 363 363 a53pll: clock@b116000 { 364 364 compatible = "qcom,ipq6018-a53pll"; 365 - reg = <0x0b116000 0x40>; 365 + reg = <0x0 0x0b116000 0x0 0x40>; 366 366 #clock-cells = <0>; 367 367 clocks = <&xo>; 368 368 clock-names = "xo"; ··· 377 377 }; 378 378 379 379 timer@b120000 { 380 - #address-cells = <1>; 381 - #size-cells = <1>; 380 + #address-cells = <2>; 381 + #size-cells = <2>; 382 382 ranges; 383 383 compatible = "arm,armv7-timer-mem"; 384 - reg = <0x0b120000 0x1000>; 384 + reg = <0x0 0x0b120000 0x0 0x1000>; 385 385 clock-frequency = <19200000>; 386 386 387 387 frame@b120000 { 388 388 frame-number = <0>; 389 389 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 390 390 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 391 - reg = <0x0b121000 0x1000>, 392 - <0x0b122000 0x1000>; 391 + reg = <0x0 0x0b121000 0x0 0x1000>, 392 + <0x0 0x0b122000 0x0 0x1000>; 393 393 }; 394 394 395 395 frame@b123000 { 396 396 frame-number = <1>; 397 397 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 398 - reg = <0xb123000 0x1000>; 398 + reg = <0x0 0xb123000 0x0 0x1000>; 399 399 status = "disabled"; 400 400 }; 401 401 402 402 frame@b124000 { 403 403 frame-number = <2>; 404 404 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 405 - reg = <0x0b124000 0x1000>; 405 + reg = <0x0 0x0b124000 0x0 0x1000>; 406 406 status = "disabled"; 407 407 }; 408 408 409 409 frame@b125000 { 410 410 frame-number = <3>; 411 411 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 412 - reg = <0x0b125000 0x1000>; 412 + reg = <0x0 0x0b125000 0x0 0x1000>; 413 413 status = "disabled"; 414 414 }; 415 415 416 416 frame@b126000 { 417 417 frame-number = <4>; 418 418 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 419 - reg = <0x0b126000 0x1000>; 419 + reg = <0x0 0x0b126000 0x0 0x1000>; 420 420 status = "disabled"; 421 421 }; 422 422 423 423 frame@b127000 { 424 424 frame-number = <5>; 425 425 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 426 - reg = <0x0b127000 0x1000>; 426 + reg = <0x0 0x0b127000 0x0 0x1000>; 427 427 status = "disabled"; 428 428 }; 429 429 430 430 frame@b128000 { 431 431 frame-number = <6>; 432 432 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 433 - reg = <0x0b128000 0x1000>; 433 + reg = <0x0 0x0b128000 0x0 0x1000>; 434 434 status = "disabled"; 435 435 }; 436 436 }; 437 437 438 438 q6v5_wcss: remoteproc@cd00000 { 439 439 compatible = "qcom,ipq8074-wcss-pil"; 440 - reg = <0x0cd00000 0x4040>, 441 - <0x004ab000 0x20>; 440 + reg = <0x0 0x0cd00000 0x0 0x4040>, 441 + <0x0 0x004ab000 0x0 0x20>; 442 442 reg-names = "qdsp6", 443 443 "rmb"; 444 444 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
-1
arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
··· 243 243 interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>; 244 244 pinctrl-names = "default"; 245 245 pinctrl-0 = <&pmic_int>; 246 - rockchip,system-power-controller; 247 246 wakeup-source; 248 247 #clock-cells = <1>; 249 248 clock-output-names = "rk808-clkout1", "xin32k";
+1 -1
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
··· 20 20 gmac_clk: gmac-clock { 21 21 compatible = "fixed-clock"; 22 22 clock-frequency = <125000000>; 23 - clock-output-names = "gmac_clk"; 23 + clock-output-names = "gmac_clkin"; 24 24 #clock-cells = <0>; 25 25 }; 26 26
+2 -2
arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
··· 74 74 label = "red:diy"; 75 75 gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; 76 76 default-state = "off"; 77 - linux,default-trigger = "mmc1"; 77 + linux,default-trigger = "mmc2"; 78 78 }; 79 79 80 80 yellow_led: led-2 { 81 81 label = "yellow:yellow-led"; 82 82 gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; 83 83 default-state = "off"; 84 - linux,default-trigger = "mmc0"; 84 + linux,default-trigger = "mmc1"; 85 85 }; 86 86 }; 87 87
+3
arch/arm64/boot/dts/rockchip/rk3399.dtsi
··· 29 29 i2c6 = &i2c6; 30 30 i2c7 = &i2c7; 31 31 i2c8 = &i2c8; 32 + mmc0 = &sdio0; 33 + mmc1 = &sdmmc; 34 + mmc2 = &sdhci; 32 35 serial0 = &uart0; 33 36 serial1 = &uart1; 34 37 serial2 = &uart2;
+19 -10
drivers/bus/ti-sysc.c
··· 227 227 u32 sysc_mask, syss_done, rstval; 228 228 int syss_offset, error = 0; 229 229 230 + if (ddata->cap->regbits->srst_shift < 0) 231 + return 0; 232 + 230 233 syss_offset = ddata->offsets[SYSC_SYSSTATUS]; 231 234 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 232 235 ··· 973 970 return error; 974 971 } 975 972 } 976 - error = sysc_wait_softreset(ddata); 977 - if (error) 978 - dev_warn(ddata->dev, "OCP softreset timed out\n"); 973 + /* 974 + * Some modules like i2c and hdq1w have unusable reset status unless 975 + * the module reset quirk is enabled. Skip status check on enable. 976 + */ 977 + if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) { 978 + error = sysc_wait_softreset(ddata); 979 + if (error) 980 + dev_warn(ddata->dev, "OCP softreset timed out\n"); 981 + } 979 982 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) 980 983 sysc_disable_opt_clocks(ddata); 981 984 ··· 1382 1373 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff, 1383 1374 SYSC_QUIRK_OPT_CLKS_NEEDED), 1384 1375 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 1385 - SYSC_MODULE_QUIRK_HDQ1W), 1376 + SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1386 1377 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 1387 - SYSC_MODULE_QUIRK_HDQ1W), 1378 + SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1388 1379 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, 1389 - SYSC_MODULE_QUIRK_I2C), 1380 + SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1390 1381 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, 1391 - SYSC_MODULE_QUIRK_I2C), 1382 + SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1392 1383 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, 1393 - SYSC_MODULE_QUIRK_I2C), 1384 + SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1394 1385 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 1395 - SYSC_MODULE_QUIRK_I2C), 1386 + SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1396 1387 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0), 1397 1388 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 1398 1389 SYSC_MODULE_QUIRK_SGX), ··· 2889 2880 2890 2881 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) && 2891 2882 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)) 2892 - return -EBUSY; 2883 + return -ENXIO; 2893 2884 2894 2885 return 0; 2895 2886 }
+50 -15
drivers/firmware/xilinx/zynqmp.c
··· 20 20 #include <linux/of_platform.h> 21 21 #include <linux/slab.h> 22 22 #include <linux/uaccess.h> 23 + #include <linux/hashtable.h> 23 24 24 25 #include <linux/firmware/xlnx-zynqmp.h> 25 26 #include "zynqmp-debug.h" 26 27 28 + /* Max HashMap Order for PM API feature check (1<<7 = 128) */ 29 + #define PM_API_FEATURE_CHECK_MAX_ORDER 7 30 + 27 31 static bool feature_check_enabled; 28 - static u32 zynqmp_pm_features[PM_API_MAX]; 32 + DEFINE_HASHTABLE(pm_api_features_map, PM_API_FEATURE_CHECK_MAX_ORDER); 33 + 34 + /** 35 + * struct pm_api_feature_data - PM API Feature data 36 + * @pm_api_id: PM API Id, used as key to index into hashmap 37 + * @feature_status: status of PM API feature: valid, invalid 38 + * @hentry: hlist_node that hooks this entry into hashtable 39 + */ 40 + struct pm_api_feature_data { 41 + u32 pm_api_id; 42 + int feature_status; 43 + struct hlist_node hentry; 44 + }; 29 45 30 46 static const struct mfd_cell firmware_devs[] = { 31 47 { ··· 158 142 int ret; 159 143 u32 ret_payload[PAYLOAD_ARG_CNT]; 160 144 u64 smc_arg[2]; 145 + struct pm_api_feature_data *feature_data; 161 146 162 147 if (!feature_check_enabled) 163 148 return 0; 164 149 165 - /* Return value if feature is already checked */ 166 - if (api_id > ARRAY_SIZE(zynqmp_pm_features)) 167 - return PM_FEATURE_INVALID; 150 + /* Check for existing entry in hash table for given api */ 151 + hash_for_each_possible(pm_api_features_map, feature_data, hentry, 152 + api_id) { 153 + if (feature_data->pm_api_id == api_id) 154 + return feature_data->feature_status; 155 + } 168 156 169 - if (zynqmp_pm_features[api_id] != PM_FEATURE_UNCHECKED) 170 - return zynqmp_pm_features[api_id]; 157 + /* Add new entry if not present */ 158 + feature_data = kmalloc(sizeof(*feature_data), GFP_KERNEL); 159 + if (!feature_data) 160 + return -ENOMEM; 171 161 162 + feature_data->pm_api_id = api_id; 172 163 smc_arg[0] = PM_SIP_SVC | PM_FEATURE_CHECK; 173 164 smc_arg[1] = api_id; 174 165 175 166 ret = do_fw_call(smc_arg[0], smc_arg[1], 0, ret_payload); 176 - if (ret) { 177 - zynqmp_pm_features[api_id] = PM_FEATURE_INVALID; 178 - return PM_FEATURE_INVALID; 179 - } 167 + if (ret) 168 + ret = -EOPNOTSUPP; 169 + else 170 + ret = ret_payload[1]; 180 171 181 - zynqmp_pm_features[api_id] = ret_payload[1]; 172 + feature_data->feature_status = ret; 173 + hash_add(pm_api_features_map, &feature_data->hentry, api_id); 182 174 183 - return zynqmp_pm_features[api_id]; 175 + return ret; 184 176 } 185 177 186 178 /** ··· 224 200 * Make sure to stay in x0 register 225 201 */ 226 202 u64 smc_arg[4]; 203 + int ret; 227 204 228 - if (zynqmp_pm_feature(pm_api_id) == PM_FEATURE_INVALID) 229 - return -ENOTSUPP; 205 + /* Check if feature is supported or not */ 206 + ret = zynqmp_pm_feature(pm_api_id); 207 + if (ret < 0) 208 + return ret; 230 209 231 210 smc_arg[0] = PM_SIP_SVC | pm_api_id; 232 211 smc_arg[1] = ((u64)arg1 << 32) | arg0; ··· 642 615 */ 643 616 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) 644 617 { 645 - return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, IOCTL_SET_SD_TAPDELAY, 618 + return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, IOCTL_SD_DLL_RESET, 646 619 type, 0, NULL); 647 620 } 648 621 EXPORT_SYMBOL_GPL(zynqmp_pm_sd_dll_reset); ··· 1279 1252 1280 1253 static int zynqmp_firmware_remove(struct platform_device *pdev) 1281 1254 { 1255 + struct pm_api_feature_data *feature_data; 1256 + int i; 1257 + 1282 1258 mfd_remove_devices(&pdev->dev); 1283 1259 zynqmp_pm_api_debugfs_exit(); 1260 + 1261 + hash_for_each(pm_api_features_map, i, feature_data, hentry) { 1262 + hash_del(&feature_data->hentry); 1263 + kfree(feature_data); 1264 + } 1284 1265 1285 1266 return 0; 1286 1267 }
+1 -4
drivers/soc/fsl/dpio/dpio-driver.c
··· 95 95 { 96 96 int error; 97 97 struct fsl_mc_device_irq *irq; 98 - cpumask_t mask; 99 98 100 99 irq = dpio_dev->irqs[0]; 101 100 error = devm_request_irq(&dpio_dev->dev, ··· 111 112 } 112 113 113 114 /* set the affinity hint */ 114 - cpumask_clear(&mask); 115 - cpumask_set_cpu(cpu, &mask); 116 - if (irq_set_affinity_hint(irq->msi_desc->irq, &mask)) 115 + if (irq_set_affinity_hint(irq->msi_desc->irq, cpumask_of(cpu))) 117 116 dev_err(&dpio_dev->dev, 118 117 "irq_set_affinity failed irq %d cpu %d\n", 119 118 irq->msi_desc->irq, cpu);
+2 -1
drivers/tee/optee/call.c
··· 534 534 static bool is_normal_memory(pgprot_t p) 535 535 { 536 536 #if defined(CONFIG_ARM) 537 - return (pgprot_val(p) & L_PTE_MT_MASK) == L_PTE_MT_WRITEALLOC; 537 + return (((pgprot_val(p) & L_PTE_MT_MASK) == L_PTE_MT_WRITEALLOC) || 538 + ((pgprot_val(p) & L_PTE_MT_MASK) == L_PTE_MT_WRITEBACK)); 538 539 #elif defined(CONFIG_ARM64) 539 540 return (pgprot_val(p) & PTE_ATTRINDX_MASK) == PTE_ATTRINDX(MT_NORMAL); 540 541 #else
-4
include/linux/firmware/xlnx-zynqmp.h
··· 50 50 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U 51 51 #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U 52 52 53 - /* Feature check status */ 54 - #define PM_FEATURE_INVALID -1 55 - #define PM_FEATURE_UNCHECKED 0 56 - 57 53 /* 58 54 * Firmware FPGA Manager flags 59 55 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
+1
include/linux/platform_data/ti-sysc.h
··· 50 50 s8 emufree_shift; 51 51 }; 52 52 53 + #define SYSC_MODULE_QUIRK_ENA_RESETDONE BIT(25) 53 54 #define SYSC_MODULE_QUIRK_PRUSS BIT(24) 54 55 #define SYSC_MODULE_QUIRK_DSS_RESET BIT(23) 55 56 #define SYSC_MODULE_QUIRK_RTC_UNLOCK BIT(22)