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phy: qcom: qmp-combo: Add missing PLL (VCO) configuration on SM8750

Add missing DP PHY status and VCO clock configuration registers to fix
configuring the VCO rate on SM8750. Without proper VCO rate setting, it
works on after-reset half of rate which is not enough for DP over USB to
work as seen on logs:

[drm:msm_dp_ctrl_link_train_1_2] *ERROR* max v_level reached
[drm:msm_dp_ctrl_link_train_1_2] *ERROR* link training #1 on phy 0 failed. ret=-11

Fixes: c4364048baf4 ("phy: qcom: qmp-combo: Add new PHY sequences for SM8750")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250616062541.7167-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Krzysztof Kozlowski and committed by
Vinod Koul 304c102c 2bff9083

+3
+3
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
··· 228 228 [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS, 229 229 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, 230 230 231 + [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 232 + [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 233 + 231 234 [QPHY_TX_TX_POL_INV] = QSERDES_V8_TX_TX_POL_INV, 232 235 [QPHY_TX_TX_DRV_LVL] = QSERDES_V8_TX_TX_DRV_LVL, 233 236 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_TX_TX_EMP_POST1_LVL,