Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: stm32mp1: use stm32mp13 reset driver
STM32MP15 is now using the same reset driver as STM32MP13 as they
have the same binding requirement.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Link: https://lore.kernel.org/r/20231208143700.354785-3-gabriel.fernandez@foss.st.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Gabriel Fernandez
and committed by
Stephen Boyd
30500c2a
3ac7ca59
+42
-128
+1
-1
drivers/clk/stm32/Makefile
+1
-1
drivers/clk/stm32/Makefile
+4
-1
drivers/clk/stm32/clk-stm32-core.c
+4
-1
drivers/clk/stm32/clk-stm32-core.c
···
70
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int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
71
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void __iomem *base)
72
72
{
73
+
const struct stm32_rcc_match_data *rcc_match_data;
73
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const struct of_device_id *match;
74
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int err;
75
76
···
80
79
return -ENODEV;
81
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}
82
81
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+
rcc_match_data = match->data;
83
+
83
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/* RCC Reset Configuration */
84
-
err = stm32_rcc_reset_init(dev, match, base);
85
+
err = stm32_rcc_reset_init(dev, rcc_match_data->reset_data, base);
85
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if (err) {
86
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pr_err("stm32 reset failed to initialize\n");
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return err;
+1
-4
drivers/clk/stm32/clk-stm32-core.h
+1
-4
drivers/clk/stm32/clk-stm32-core.h
···
70
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const struct clock_config *tab_clocks;
71
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unsigned int maxbinding;
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struct clk_stm32_clock_data *clock_data;
73
-
u32 clear_offset;
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+
struct clk_stm32_reset_data *reset_data;
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int (*check_security)(void __iomem *base,
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const struct clock_config *cfg);
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int (*multi_mux)(void __iomem *base, const struct clock_config *cfg);
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};
78
-
79
-
int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
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-
void __iomem *base);
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int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
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void __iomem *base);
+16
-111
drivers/clk/stm32/clk-stm32mp1.c
+16
-111
drivers/clk/stm32/clk-stm32mp1.c
···
20
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21
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#include <dt-bindings/clock/stm32mp1-clks.h>
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+
#include "reset-stm32.h"
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+
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#define STM32MP1_RESET_ID_MASK GENMASK(15, 0)
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+
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static DEFINE_SPINLOCK(rlock);
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#define RCC_OCENSETR 0x0C
···
2141
2137
const struct clock_config *cfg;
2142
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unsigned int num;
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unsigned int maxbinding;
2144
-
u32 clear_offset;
2140
+
struct clk_stm32_reset_data *reset_data;
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bool (*check_security)(const struct clock_config *cfg);
2142
+
};
2143
+
2144
+
static struct clk_stm32_reset_data stm32mp1_reset_data = {
2145
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.nr_lines = STM32MP1_RESET_ID_MASK,
2146
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.clear_offset = RCC_CLR,
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};
2147
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static struct stm32_rcc_match_data stm32mp1_data = {
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.cfg = stm32mp1_clock_cfg,
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.num = ARRAY_SIZE(stm32mp1_clock_cfg),
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.maxbinding = STM32MP1_LAST_CLK,
2152
-
.clear_offset = RCC_CLR,
2153
+
.reset_data = &stm32mp1_reset_data,
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};
2154
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static struct stm32_rcc_match_data stm32mp1_data_secure = {
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.cfg = stm32mp1_clock_cfg,
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.num = ARRAY_SIZE(stm32mp1_clock_cfg),
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.maxbinding = STM32MP1_LAST_CLK,
2159
-
.clear_offset = RCC_CLR,
2160
+
.reset_data = &stm32mp1_reset_data,
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.check_security = &stm32_check_security
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};
2162
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···
2200
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hws[cfg->id] = hw;
2201
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return 0;
2203
-
}
2204
-
2205
-
#define STM32_RESET_ID_MASK GENMASK(15, 0)
2206
-
2207
-
struct stm32_reset_data {
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/* reset lock */
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spinlock_t lock;
2210
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struct reset_controller_dev rcdev;
2211
-
void __iomem *membase;
2212
-
u32 clear_offset;
2213
-
};
2214
-
2215
-
static inline struct stm32_reset_data *
2216
-
to_stm32_reset_data(struct reset_controller_dev *rcdev)
2217
-
{
2218
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return container_of(rcdev, struct stm32_reset_data, rcdev);
2219
-
}
2220
-
2221
-
static int stm32_reset_update(struct reset_controller_dev *rcdev,
2222
-
unsigned long id, bool assert)
2223
-
{
2224
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struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
2225
-
int reg_width = sizeof(u32);
2226
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int bank = id / (reg_width * BITS_PER_BYTE);
2227
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int offset = id % (reg_width * BITS_PER_BYTE);
2228
-
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if (data->clear_offset) {
2230
-
void __iomem *addr;
2231
-
2232
-
addr = data->membase + (bank * reg_width);
2233
-
if (!assert)
2234
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addr += data->clear_offset;
2235
-
2236
-
writel(BIT(offset), addr);
2237
-
2238
-
} else {
2239
-
unsigned long flags;
2240
-
u32 reg;
2241
-
2242
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spin_lock_irqsave(&data->lock, flags);
2243
-
2244
-
reg = readl(data->membase + (bank * reg_width));
2245
-
2246
-
if (assert)
2247
-
reg |= BIT(offset);
2248
-
else
2249
-
reg &= ~BIT(offset);
2250
-
2251
-
writel(reg, data->membase + (bank * reg_width));
2252
-
2253
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spin_unlock_irqrestore(&data->lock, flags);
2254
-
}
2255
-
2256
-
return 0;
2257
-
}
2258
-
2259
-
static int stm32_reset_assert(struct reset_controller_dev *rcdev,
2260
-
unsigned long id)
2261
-
{
2262
-
return stm32_reset_update(rcdev, id, true);
2263
-
}
2264
-
2265
-
static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
2266
-
unsigned long id)
2267
-
{
2268
-
return stm32_reset_update(rcdev, id, false);
2269
-
}
2270
-
2271
-
static int stm32_reset_status(struct reset_controller_dev *rcdev,
2272
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unsigned long id)
2273
-
{
2274
-
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
2275
-
int reg_width = sizeof(u32);
2276
-
int bank = id / (reg_width * BITS_PER_BYTE);
2277
-
int offset = id % (reg_width * BITS_PER_BYTE);
2278
-
u32 reg;
2279
-
2280
-
reg = readl(data->membase + (bank * reg_width));
2281
-
2282
-
return !!(reg & BIT(offset));
2283
-
}
2284
-
2285
-
static const struct reset_control_ops stm32_reset_ops = {
2286
-
.assert = stm32_reset_assert,
2287
-
.deassert = stm32_reset_deassert,
2288
-
.status = stm32_reset_status,
2289
-
};
2290
-
2291
-
static int stm32_rcc_reset_init(struct device *dev, void __iomem *base,
2292
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const struct of_device_id *match)
2293
-
{
2294
-
const struct stm32_rcc_match_data *data = match->data;
2295
-
struct stm32_reset_data *reset_data = NULL;
2296
-
2297
-
reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
2298
-
if (!reset_data)
2299
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return -ENOMEM;
2300
-
2301
-
spin_lock_init(&reset_data->lock);
2302
-
reset_data->membase = base;
2303
-
reset_data->rcdev.owner = THIS_MODULE;
2304
-
reset_data->rcdev.ops = &stm32_reset_ops;
2305
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reset_data->rcdev.of_node = dev_of_node(dev);
2306
-
reset_data->rcdev.nr_resets = STM32_RESET_ID_MASK;
2307
-
reset_data->clear_offset = data->clear_offset;
2308
-
2309
-
return reset_controller_register(&reset_data->rcdev);
2310
2194
}
2311
2195
2312
2196
static int stm32_rcc_clock_init(struct device *dev, void __iomem *base,
···
2244
2342
static int stm32_rcc_init(struct device *dev, void __iomem *base,
2245
2343
const struct of_device_id *match_data)
2246
2344
{
2345
+
const struct stm32_rcc_match_data *rcc_match_data;
2247
2346
const struct of_device_id *match;
2248
2347
int err;
2249
2348
···
2254
2351
return -ENODEV;
2255
2352
}
2256
2353
2354
+
rcc_match_data = match->data;
2355
+
2257
2356
/* RCC Reset Configuration */
2258
-
err = stm32_rcc_reset_init(dev, base, match);
2357
+
err = stm32_rcc_reset_init(dev, rcc_match_data->reset_data, base);
2259
2358
if (err) {
2260
2359
pr_err("stm32mp1 reset failed to initialize\n");
2261
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return err;
+8
-1
drivers/clk/stm32/clk-stm32mp13.c
+8
-1
drivers/clk/stm32/clk-stm32mp13.c
···
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#include <linux/platform_device.h>
11
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#include <dt-bindings/clock/stm32mp13-clks.h>
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#include "clk-stm32-core.h"
13
+
#include "reset-stm32.h"
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#include "stm32mp13_rcc.h"
14
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+
#define STM32MP1_RESET_ID_MASK GENMASK(15, 0)
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#define RCC_CLR_OFFSET 0x4
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/* STM32 Gates definition */
···
1513
1511
.is_multi_mux = stm32mp13_is_multi_mux,
1514
1512
};
1515
1513
1514
+
static struct clk_stm32_reset_data stm32mp13_reset_data = {
1515
+
.nr_lines = STM32MP1_RESET_ID_MASK,
1516
+
.clear_offset = RCC_CLR_OFFSET,
1517
+
};
1518
+
1516
1519
static const struct stm32_rcc_match_data stm32mp13_data = {
1517
1520
.tab_clocks = stm32mp13_clock_cfg,
1518
1521
.num_clocks = ARRAY_SIZE(stm32mp13_clock_cfg),
1519
1522
.clock_data = &stm32mp13_clock_data,
1520
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.check_security = &stm32mp13_clock_is_provided_by_secure,
1521
1524
.maxbinding = STM32MP1_LAST_CLK,
1522
-
.clear_offset = RCC_CLR_OFFSET,
1525
+
.reset_data = &stm32mp13_reset_data,
1523
1526
};
1524
1527
1525
1528
static const struct of_device_id stm32mp13_match_data[] = {
+5
-9
drivers/clk/stm32/reset-stm32.c
+5
-9
drivers/clk/stm32/reset-stm32.c
···
11
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#include <linux/slab.h>
12
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#include <linux/spinlock.h>
13
13
14
-
#include "clk-stm32-core.h"
15
-
16
-
#define STM32_RESET_ID_MASK GENMASK(15, 0)
14
+
#include "reset-stm32.h"
17
15
18
16
struct stm32_reset_data {
19
17
/* reset lock */
···
97
99
.status = stm32_reset_status,
98
100
};
99
101
100
-
int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
102
+
int stm32_rcc_reset_init(struct device *dev, struct clk_stm32_reset_data *data,
101
103
void __iomem *base)
102
104
{
103
-
const struct stm32_rcc_match_data *data = match->data;
104
-
struct stm32_reset_data *reset_data = NULL;
105
-
106
-
data = match->data;
105
+
struct stm32_reset_data *reset_data;
107
106
108
107
reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
109
108
if (!reset_data)
110
109
return -ENOMEM;
111
110
112
111
spin_lock_init(&reset_data->lock);
112
+
113
113
reset_data->membase = base;
114
114
reset_data->rcdev.owner = THIS_MODULE;
115
115
reset_data->rcdev.ops = &stm32_reset_ops;
116
116
reset_data->rcdev.of_node = dev_of_node(dev);
117
-
reset_data->rcdev.nr_resets = STM32_RESET_ID_MASK;
117
+
reset_data->rcdev.nr_resets = data->nr_lines;
118
118
reset_data->clear_offset = data->clear_offset;
119
119
120
120
return reset_controller_register(&reset_data->rcdev);
+7
-1
drivers/clk/stm32/reset-stm32.h
+7
-1
drivers/clk/stm32/reset-stm32.h
···
4
4
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
5
5
*/
6
6
7
-
int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
7
+
struct clk_stm32_reset_data {
8
+
const struct reset_control_ops *ops;
9
+
unsigned int nr_lines;
10
+
u32 clear_offset;
11
+
};
12
+
13
+
int stm32_rcc_reset_init(struct device *dev, struct clk_stm32_reset_data *data,
8
14
void __iomem *base);