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dt-bindings: pwm: fsl-ftm: Convert to yaml format

Convert dt-bindings pwm-fsl-ftm.txt to yaml format.

Additional change during convert:
- "big-endian" is not required property.
- Add "sleep" to pinctrl-names.
- Change pinctrl-NNN to pinctrl-0 and pinctrl-1.
- Remove label "pwm0" in example.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240528202025.2919358-1-Frank.Li@nxp.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>

authored by

Frank Li and committed by
Uwe Kleine-König
307d0a70 37f77070

+92 -55
+92
Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pwm/fsl,vf610-ftm-pwm.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale FlexTimer Module (FTM) PWM controller 8 + 9 + description: | 10 + The same FTM PWM device can have a different endianness on different SoCs. The 11 + device tree provides a property to describing this so that an operating system 12 + device driver can handle all variants of the device. Refer to the table below 13 + for the endianness of the FTM PWM block as integrated into the existing SoCs: 14 + 15 + SoC | FTM-PWM endianness 16 + --------+------------------- 17 + Vybrid | LE 18 + LS1 | BE 19 + LS2 | LE 20 + 21 + Please see ../regmap/regmap.txt for more detail about how to specify endian 22 + modes in device tree. 23 + 24 + maintainers: 25 + - Frank Li <Frank.Li@nxp.com> 26 + 27 + properties: 28 + compatible: 29 + enum: 30 + - fsl,vf610-ftm-pwm 31 + - fsl,imx8qm-ftm-pwm 32 + 33 + reg: 34 + maxItems: 1 35 + 36 + "#pwm-cells": 37 + const: 3 38 + 39 + clocks: 40 + minItems: 4 41 + maxItems: 4 42 + 43 + clock-names: 44 + items: 45 + - const: ftm_sys 46 + - const: ftm_ext 47 + - const: ftm_fix 48 + - const: ftm_cnt_clk_en 49 + 50 + pinctrl-0: true 51 + pinctrl-1: true 52 + 53 + pinctrl-names: 54 + minItems: 1 55 + items: 56 + - const: default 57 + - const: sleep 58 + 59 + big-endian: 60 + $ref: /schemas/types.yaml#/definitions/flag 61 + description: 62 + Boolean property, required if the FTM PWM registers use a big- 63 + endian rather than little-endian layout. 64 + 65 + required: 66 + - compatible 67 + - reg 68 + - clocks 69 + - clock-names 70 + 71 + allOf: 72 + - $ref: pwm.yaml# 73 + 74 + unevaluatedProperties: false 75 + 76 + examples: 77 + - | 78 + #include <dt-bindings/clock/vf610-clock.h> 79 + 80 + pwm@40038000 { 81 + compatible = "fsl,vf610-ftm-pwm"; 82 + reg = <0x40038000 0x1000>; 83 + #pwm-cells = <3>; 84 + clocks = <&clks VF610_CLK_FTM0>, 85 + <&clks VF610_CLK_FTM0_EXT_SEL>, 86 + <&clks VF610_CLK_FTM0_FIX_SEL>, 87 + <&clks VF610_CLK_FTM0_EXT_FIX_EN>; 88 + clock-names = "ftm_sys", "ftm_ext", "ftm_fix", "ftm_cnt_clk_en"; 89 + pinctrl-names = "default"; 90 + pinctrl-0 = <&pinctrl_pwm0_1>; 91 + big-endian; 92 + };
-55
Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
··· 1 - Freescale FlexTimer Module (FTM) PWM controller 2 - 3 - The same FTM PWM device can have a different endianness on different SoCs. The 4 - device tree provides a property to describing this so that an operating system 5 - device driver can handle all variants of the device. Refer to the table below 6 - for the endianness of the FTM PWM block as integrated into the existing SoCs: 7 - 8 - SoC | FTM-PWM endianness 9 - --------+------------------- 10 - Vybrid | LE 11 - LS1 | BE 12 - LS2 | LE 13 - 14 - Please see ../regmap/regmap.txt for more detail about how to specify endian 15 - modes in device tree. 16 - 17 - 18 - Required properties: 19 - - compatible : should be "fsl,<soc>-ftm-pwm" and one of the following 20 - compatible strings: 21 - - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610 22 - - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM 23 - - reg: Physical base address and length of the controller's registers 24 - - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of 25 - the cells format. 26 - - clock-names: Should include the following module clock source entries: 27 - "ftm_sys" (module clock, also can be used as counter clock), 28 - "ftm_ext" (external counter clock), 29 - "ftm_fix" (fixed counter clock), 30 - "ftm_cnt_clk_en" (external and fixed counter clock enable/disable). 31 - - clocks: Must contain a phandle and clock specifier for each entry in 32 - clock-names, please see clock/clock-bindings.txt for details of the property 33 - values. 34 - - pinctrl-names: Must contain a "default" entry. 35 - - pinctrl-NNN: One property must exist for each entry in pinctrl-names. 36 - See pinctrl/pinctrl-bindings.txt for details of the property values. 37 - - big-endian: Boolean property, required if the FTM PWM registers use a big- 38 - endian rather than little-endian layout. 39 - 40 - Example: 41 - 42 - pwm0: pwm@40038000 { 43 - compatible = "fsl,vf610-ftm-pwm"; 44 - reg = <0x40038000 0x1000>; 45 - #pwm-cells = <3>; 46 - clock-names = "ftm_sys", "ftm_ext", 47 - "ftm_fix", "ftm_cnt_clk_en"; 48 - clocks = <&clks VF610_CLK_FTM0>, 49 - <&clks VF610_CLK_FTM0_EXT_SEL>, 50 - <&clks VF610_CLK_FTM0_FIX_SEL>, 51 - <&clks VF610_CLK_FTM0_EXT_FIX_EN>; 52 - pinctrl-names = "default"; 53 - pinctrl-0 = <&pinctrl_pwm0_1>; 54 - big-endian; 55 - };