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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge branch 'net-dsa-mxl-gsw1xx-setup-polarities-and-validate-chip'
Daniel Golle says:
====================
net: dsa: mxl-gsw1xx: setup polarities and validate chip
Now that common PHY properties make it easy to configure the SerDes RX
and TX polarities, use that for the SGMII/1000Base-X/2500Base-X port of
the MaxLinear GSW1xx switches.
Also, validate hardware in probe() function to make sure the switch is
actually present and MDIO communication works properly.
====================
Link: https://patch.msgid.link/cover.1769916962.git.daniel@makrotopia.org
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+68
-12
+4
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
+4
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
···
105
105
patternProperties:
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"^(ethernet-)?port@[0-6]$":
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$ref: dsa-port.yaml#
108
+
allOf:
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+
- $ref: /schemas/phy/phy-common-props.yaml#
108
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unevaluatedProperties: false
109
111
110
112
properties:
···
290
288
291
289
- |
292
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#include <dt-bindings/leds/common.h>
291
+
#include <dt-bindings/phy/phy.h>
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294
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mdio {
295
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#address-cells = <1>;
···
323
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label = "wan";
324
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phy-mode = "1000base-x";
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managed = "in-band-status";
323
+
tx-polarity = <PHY_POL_INVERT>;
326
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};
327
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port@5 {
+1
drivers/net/dsa/lantiq/Kconfig
+1
drivers/net/dsa/lantiq/Kconfig
+54
-12
drivers/net/dsa/lantiq/mxl-gsw1xx.c
+54
-12
drivers/net/dsa/lantiq/mxl-gsw1xx.c
···
15
15
#include <linux/module.h>
16
16
#include <linux/of_device.h>
17
17
#include <linux/of_mdio.h>
18
+
#include <linux/phy/phy-common-props.h>
19
+
#include <linux/property.h>
18
20
#include <linux/regmap.h>
19
21
#include <linux/workqueue.h>
20
22
#include <net/dsa.h>
···
231
229
1000, 100000);
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}
233
231
234
-
static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv)
232
+
static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv, phy_interface_t interface)
235
233
{
234
+
struct dsa_port *sgmii_port;
235
+
unsigned int pol;
236
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int ret;
237
237
u16 val;
238
+
239
+
sgmii_port = dsa_to_port(priv->gswip.ds, GSW1XX_SGMII_PORT);
240
+
if (!sgmii_port)
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+
return -EINVAL;
238
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/* Assert and deassert SGMII shell reset */
240
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ret = regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ,
···
268
260
FIELD_PREP(GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT,
269
261
GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT_DEF);
270
262
263
+
ret = phy_get_manual_rx_polarity(of_fwnode_handle(sgmii_port->dn),
264
+
phy_modes(interface), &pol);
265
+
if (ret)
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+
return ret;
267
+
271
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/* RX lane seems to be inverted internally, so bit
272
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* GSW1XX_SGMII_PHY_RX0_CFG2_INVERT needs to be set for normal
273
-
* (ie. non-inverted) operation.
274
-
*
275
-
* TODO: Take care of inverted RX pair once generic property is
276
-
* available
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+
* (ie. non-inverted) operation matching the chips external pins as
271
+
* described in datasheets dated 2023-11-08, ie. pin B20 (RX0_P) being
272
+
* the positive signal and pin B21 (RX0_M) being the negative signal of
273
+
* the differential input pair.
277
274
*/
278
-
279
-
val |= GSW1XX_SGMII_PHY_RX0_CFG2_INVERT;
275
+
if (pol == PHY_POL_NORMAL)
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+
val |= GSW1XX_SGMII_PHY_RX0_CFG2_INVERT;
280
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ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_RX0_CFG2, val);
282
279
if (ret < 0)
···
290
277
val = FIELD_PREP(GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL,
291
278
GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL_DEF);
292
279
293
-
/* TODO: Take care of inverted TX pair once generic property is
294
-
* available
295
-
*/
280
+
ret = phy_get_manual_tx_polarity(of_fwnode_handle(sgmii_port->dn),
281
+
phy_modes(interface), &pol);
282
+
if (ret)
283
+
return ret;
284
+
285
+
if (pol == PHY_POL_INVERT)
286
+
val |= GSW1XX_SGMII_PHY_TX0_CFG3_INVERT;
296
287
297
288
ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_TX0_CFG3, val);
298
289
if (ret < 0)
···
353
336
priv->tbi_interface = PHY_INTERFACE_MODE_NA;
354
337
355
338
if (!reconf)
356
-
ret = gsw1xx_pcs_reset(priv);
339
+
ret = gsw1xx_pcs_reset(priv, interface);
357
340
358
341
if (ret)
359
342
return ret;
···
688
671
{
689
672
struct device *dev = &mdiodev->dev;
690
673
struct gsw1xx_priv *priv;
691
-
u32 version;
674
+
u32 version, val;
675
+
u8 shellver;
676
+
u16 pnum;
692
677
int ret;
693
678
694
679
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
···
738
719
if (IS_ERR(priv->shell))
739
720
return PTR_ERR(priv->shell);
740
721
722
+
ret = regmap_read(priv->shell, GSW1XX_SHELL_MANU_ID, &val);
723
+
if (ret < 0)
724
+
return ret;
725
+
726
+
/* validate chip ID */
727
+
if (FIELD_GET(GSW1XX_SHELL_MANU_ID_FIX1, val) != 1)
728
+
return -ENODEV;
729
+
730
+
if (FIELD_GET(GSW1XX_SHELL_MANU_ID_MANID, val) !=
731
+
GSW1XX_SHELL_MANU_ID_MANID_VAL)
732
+
return -ENODEV;
733
+
734
+
pnum = FIELD_GET(GSW1XX_SHELL_MANU_ID_PNUML, val);
735
+
736
+
ret = regmap_read(priv->shell, GSW1XX_SHELL_PNUM_ID, &val);
737
+
if (ret < 0)
738
+
return ret;
739
+
740
+
pnum |= FIELD_GET(GSW1XX_SHELL_PNUM_ID_PNUMM, val) << 4;
741
+
shellver = FIELD_GET(GSW1XX_SHELL_PNUM_ID_VER, val);
742
+
741
743
ret = gsw1xx_serdes_pcs_init(priv);
742
744
if (ret < 0)
743
745
return ret;
···
778
738
ret = gswip_probe_common(&priv->gswip, version);
779
739
if (ret)
780
740
return ret;
741
+
742
+
dev_info(dev, "standalone switch part number 0x%x v1.%u\n", pnum, shellver);
781
743
782
744
dev_set_drvdata(dev, &priv->gswip);
783
745
+9
drivers/net/dsa/lantiq/mxl-gsw1xx.h
+9
drivers/net/dsa/lantiq/mxl-gsw1xx.h
···
110
110
#define GSW1XX_SHELL_BASE 0xfa00
111
111
#define GSW1XX_SHELL_RST_REQ 0x01
112
112
#define GSW1XX_RST_REQ_SGMII_SHELL BIT(5)
113
+
#define GSW1XX_SHELL_MANU_ID 0x10
114
+
#define GSW1XX_SHELL_MANU_ID_PNUML GENMASK(15, 12)
115
+
#define GSW1XX_SHELL_MANU_ID_MANID GENMASK(11, 1)
116
+
#define GSW1XX_SHELL_MANU_ID_MANID_VAL 0x389
117
+
#define GSW1XX_SHELL_MANU_ID_FIX1 BIT(0)
118
+
#define GSW1XX_SHELL_PNUM_ID 0x11
119
+
#define GSW1XX_SHELL_PNUM_ID_VER GENMASK(15, 12)
120
+
#define GSW1XX_SHELL_PNUM_ID_PNUMM GENMASK(11, 0)
121
+
113
122
/* RGMII PAD Slew Control Register */
114
123
#define GSW1XX_SHELL_RGMII_SLEW_CFG 0x78
115
124
#define RGMII_SLEW_CFG_DRV_TXC BIT(2)