Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-5.6-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
- Fix __ALIGN_STR and __ALIGN to not use default junk padding
- Misc Kconfig cleanups, header updates
* tag 'arc-5.6-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: define __ALIGN_STR and __ALIGN symbols for ARC
ARC: show_regs: reduce lines of output
ARC: Replace <linux/clk-provider.h> by <linux/of_clk.h>
ARC: fpu: fix randconfig build error reported by 0-day test service
ARC: fix some Kconfig typos
ARC: Cleanup old Kconfig IO scheduler options
+19
-26
+2
-2
arch/arc/Kconfig
+2
-2
arch/arc/Kconfig
···
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help
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Support for ARC HS38x Cores based on ARCv2 ISA
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The notable features are:
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-
- SMP configurations of upto 4 core with coherency
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+
- SMP configurations of up to 4 cores with coherency
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- Optional L2 Cache and IO-Coherency
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- Revised Interrupt Architecture (multiple priorites, reg banks,
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auto stack switch, auto regfile save/restore)
···
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help
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In SMP configuration cores can be configured as Halt-on-reset
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or they could all start at same time. For Halt-on-reset, non
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masters are parked until Master kicks them so they can start of
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+
masters are parked until Master kicks them so they can start off
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at designated entry point. For other case, all jump to common
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entry point and spin wait for Master's signal.
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-2
arch/arc/configs/nps_defconfig
-2
arch/arc/configs/nps_defconfig
-2
arch/arc/configs/nsimosci_defconfig
-2
arch/arc/configs/nsimosci_defconfig
-2
arch/arc/configs/nsimosci_hs_defconfig
-2
arch/arc/configs/nsimosci_hs_defconfig
-2
arch/arc/configs/nsimosci_hs_smp_defconfig
-2
arch/arc/configs/nsimosci_hs_smp_defconfig
+2
arch/arc/include/asm/fpu.h
+2
arch/arc/include/asm/fpu.h
+2
arch/arc/include/asm/linkage.h
+2
arch/arc/include/asm/linkage.h
+1
-1
arch/arc/kernel/setup.c
+1
-1
arch/arc/kernel/setup.c
···
8
8
#include <linux/delay.h>
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9
#include <linux/root_dev.h>
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10
#include <linux/clk.h>
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-
#include <linux/clk-provider.h>
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11
#include <linux/clocksource.h>
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#include <linux/console.h>
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#include <linux/module.h>
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#include <linux/cpu.h>
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+
#include <linux/of_clk.h>
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#include <linux/of_fdt.h>
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#include <linux/of.h>
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#include <linux/cache.h>
+12
-15
arch/arc/kernel/troubleshoot.c
+12
-15
arch/arc/kernel/troubleshoot.c
···
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if (IS_ERR(nm))
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nm = "?";
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}
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-
pr_info(" @off 0x%lx in [%s]\n"
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" VMA: 0x%08lx to 0x%08lx\n",
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+
pr_info(" @off 0x%lx in [%s] VMA: 0x%08lx to 0x%08lx\n",
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vma->vm_start < TASK_UNMAPPED_BASE ?
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address : address - vma->vm_start,
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nm, vma->vm_start, vma->vm_end);
···
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unsigned int vec, cause_code;
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unsigned long address;
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pr_info("\n[ECR ]: 0x%08lx => ", regs->event);
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-
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/* For Data fault, this is data address not instruction addr */
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address = current->thread.fault_address;
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···
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/* For DTLB Miss or ProtV, display the memory involved too */
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if (vec == ECR_V_DTLB_MISS) {
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pr_cont("Invalid %s @ 0x%08lx by insn @ 0x%08lx\n",
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+
pr_cont("Invalid %s @ 0x%08lx by insn @ %pS\n",
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(cause_code == 0x01) ? "Read" :
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((cause_code == 0x02) ? "Write" : "EX"),
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address, regs->ret);
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address, (void *)regs->ret);
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} else if (vec == ECR_V_ITLB_MISS) {
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pr_cont("Insn could not be fetched\n");
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} else if (vec == ECR_V_MACH_CHK) {
···
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show_ecr_verbose(regs);
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pr_info("[EFA ]: 0x%08lx\n[BLINK ]: %pS\n[ERET ]: %pS\n",
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current->thread.fault_address,
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(void *)regs->blink, (void *)regs->ret);
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-
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if (user_mode(regs))
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show_faulting_vma(regs->ret); /* faulting code, not data */
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-
pr_info("[STAT32]: 0x%08lx", regs->status32);
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+
pr_info("ECR: 0x%08lx EFA: 0x%08lx ERET: 0x%08lx\n",
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+
regs->event, current->thread.fault_address, regs->ret);
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+
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+
pr_info("STAT32: 0x%08lx", regs->status32);
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#define STS_BIT(r, bit) r->status32 & STATUS_##bit##_MASK ? #bit" " : ""
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#ifdef CONFIG_ISA_ARCOMPACT
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pr_cont(" : %2s%2s%2s%2s%2s%2s%2s\n",
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+
pr_cont(" [%2s%2s%2s%2s%2s%2s%2s]",
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(regs->status32 & STATUS_U_MASK) ? "U " : "K ",
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STS_BIT(regs, DE), STS_BIT(regs, AE),
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STS_BIT(regs, A2), STS_BIT(regs, A1),
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STS_BIT(regs, E2), STS_BIT(regs, E1));
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#else
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pr_cont(" : %2s%2s%2s%2s\n",
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+
pr_cont(" [%2s%2s%2s%2s]",
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STS_BIT(regs, IE),
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(regs->status32 & STATUS_U_MASK) ? "U " : "K ",
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STS_BIT(regs, DE), STS_BIT(regs, AE));
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#endif
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pr_info("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n",
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regs->bta, regs->sp, regs->fp);
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+
pr_cont(" BTA: 0x%08lx\n", regs->bta);
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+
pr_info("BLK: %pS\n SP: 0x%08lx FP: 0x%08lx\n",
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+
(void *)regs->blink, regs->sp, regs->fp);
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pr_info("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n",
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regs->lp_start, regs->lp_end, regs->lp_count);
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