Merge tag 'x86-urgent-2025-04-18' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

+4 -1

arch/x86/boot/compressed/mem.c

··· 34 34 35 35 void arch_accept_memory(phys_addr_t start, phys_addr_t end) 36 36 { 37 + static bool sevsnp; 38 + 37 39 /* Platform-specific memory-acceptance call goes here */ 38 40 if (early_is_tdx_guest()) { 39 41 if (!tdx_accept_memory(start, end)) 40 42 panic("TDX: Failed to accept memory\n"); 41 - } else if (sev_snp_enabled()) { 43 + } else if (sevsnp || (sev_get_status() & MSR_AMD64_SEV_SNP_ENABLED)) { 44 + sevsnp = true; 42 45 snp_accept_memory(start, end); 43 46 } else { 44 47 error("Cannot accept memory: unknown platform\n");

+15 -52

arch/x86/boot/compressed/sev.c

··· 164 164 165 165 static void __page_state_change(unsigned long paddr, enum psc_op op) 166 166 { 167 - u64 val; 168 - 169 - if (!sev_snp_enabled()) 170 - return; 167 + u64 val, msr; 171 168 172 169 /* 173 170 * If private -> shared then invalidate the page before requesting the ··· 172 175 */ 173 176 if (op == SNP_PAGE_STATE_SHARED) 174 177 pvalidate_4k_page(paddr, paddr, false); 178 + 179 + /* Save the current GHCB MSR value */ 180 + msr = sev_es_rd_ghcb_msr(); 175 181 176 182 /* Issue VMGEXIT to change the page state in RMP table. */ 177 183 sev_es_wr_ghcb_msr(GHCB_MSR_PSC_REQ_GFN(paddr >> PAGE_SHIFT, op)); ··· 184 184 val = sev_es_rd_ghcb_msr(); 185 185 if ((GHCB_RESP_CODE(val) != GHCB_MSR_PSC_RESP) || GHCB_MSR_PSC_RESP_VAL(val)) 186 186 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PSC); 187 + 188 + /* Restore the GHCB MSR value */ 189 + sev_es_wr_ghcb_msr(msr); 187 190 188 191 /* 189 192 * Now that page state is changed in the RMP table, validate it so that it is ··· 198 195 199 196 void snp_set_page_private(unsigned long paddr) 200 197 { 198 + if (!sev_snp_enabled()) 199 + return; 200 + 201 201 __page_state_change(paddr, SNP_PAGE_STATE_PRIVATE); 202 202 } 203 203 204 204 void snp_set_page_shared(unsigned long paddr) 205 205 { 206 + if (!sev_snp_enabled()) 207 + return; 208 + 206 209 __page_state_change(paddr, SNP_PAGE_STATE_SHARED); 207 210 } 208 211 ··· 232 223 return true; 233 224 } 234 225 235 - static phys_addr_t __snp_accept_memory(struct snp_psc_desc *desc, 236 - phys_addr_t pa, phys_addr_t pa_end) 237 - { 238 - struct psc_hdr *hdr; 239 - struct psc_entry *e; 240 - unsigned int i; 241 - 242 - hdr = &desc->hdr; 243 - memset(hdr, 0, sizeof(*hdr)); 244 - 245 - e = desc->entries; 246 - 247 - i = 0; 248 - while (pa < pa_end && i < VMGEXIT_PSC_MAX_ENTRY) { 249 - hdr->end_entry = i; 250 - 251 - e->gfn = pa >> PAGE_SHIFT; 252 - e->operation = SNP_PAGE_STATE_PRIVATE; 253 - if (IS_ALIGNED(pa, PMD_SIZE) && (pa_end - pa) >= PMD_SIZE) { 254 - e->pagesize = RMP_PG_SIZE_2M; 255 - pa += PMD_SIZE; 256 - } else { 257 - e->pagesize = RMP_PG_SIZE_4K; 258 - pa += PAGE_SIZE; 259 - } 260 - 261 - e++; 262 - i++; 263 - } 264 - 265 - if (vmgexit_psc(boot_ghcb, desc)) 266 - sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PSC); 267 - 268 - pvalidate_pages(desc); 269 - 270 - return pa; 271 - } 272 - 273 226 void snp_accept_memory(phys_addr_t start, phys_addr_t end) 274 227 { 275 - struct snp_psc_desc desc = {}; 276 - unsigned int i; 277 - phys_addr_t pa; 278 - 279 - if (!boot_ghcb && !early_setup_ghcb()) 280 - sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PSC); 281 - 282 - pa = start; 283 - while (pa < end) 284 - pa = __snp_accept_memory(&desc, pa, end); 228 + for (phys_addr_t pa = start; pa < end; pa += PAGE_SIZE) 229 + __page_state_change(pa, SNP_PAGE_STATE_PRIVATE); 285 230 } 286 231 287 232 void sev_es_shutdown_ghcb(void)

+2

arch/x86/boot/compressed/sev.h

··· 12 12 13 13 bool sev_snp_enabled(void); 14 14 void snp_accept_memory(phys_addr_t start, phys_addr_t end); 15 + u64 sev_get_status(void); 15 16 16 17 #else 17 18 18 19 static inline bool sev_snp_enabled(void) { return false; } 19 20 static inline void snp_accept_memory(phys_addr_t start, phys_addr_t end) { } 21 + static inline u64 sev_get_status(void) { return 0; } 20 22 21 23 #endif 22 24

+2

arch/x86/include/asm/intel-family.h

··· 126 126 #define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) /* Redwood Cove */ 127 127 #define INTEL_GRANITERAPIDS_D IFM(6, 0xAE) 128 128 129 + #define INTEL_BARTLETTLAKE IFM(6, 0xD7) /* Raptor Cove */ 130 + 129 131 /* "Hybrid" Processors (P-Core/E-Core) */ 130 132 131 133 #define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */

+12 -7

arch/x86/kernel/cpu/amd.c

··· 869 869 870 870 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n"); 871 871 setup_force_cpu_bug(X86_BUG_DIV0); 872 + 873 + /* 874 + * Turn off the Instructions Retired free counter on machines that are 875 + * susceptible to erratum #1054 "Instructions Retired Performance 876 + * Counter May Be Inaccurate". 877 + */ 878 + if (c->x86_model < 0x30) { 879 + msr_clear_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 880 + clear_cpu_cap(c, X86_FEATURE_IRPERF); 881 + } 872 882 } 873 883 874 884 static bool cpu_has_zenbleed_microcode(void) ··· 1062 1052 if (!cpu_feature_enabled(X86_FEATURE_XENPV)) 1063 1053 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 1064 1054 1065 - /* 1066 - * Turn on the Instructions Retired free counter on machines not 1067 - * susceptible to erratum #1054 "Instructions Retired Performance 1068 - * Counter May Be Inaccurate". 1069 - */ 1070 - if (cpu_has(c, X86_FEATURE_IRPERF) && 1071 - (boot_cpu_has(X86_FEATURE_ZEN1) && c->x86_model > 0x2f)) 1055 + /* Enable the Instructions Retired free counter */ 1056 + if (cpu_has(c, X86_FEATURE_IRPERF)) 1072 1057 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 1073 1058 1074 1059 check_null_seg_clears_base(c);

+7 -2

arch/x86/kernel/cpu/microcode/amd.c

··· 199 199 case 0xa70c0: return cur_rev <= 0xa70C009; break; 200 200 case 0xaa001: return cur_rev <= 0xaa00116; break; 201 201 case 0xaa002: return cur_rev <= 0xaa00218; break; 202 + case 0xb0021: return cur_rev <= 0xb002146; break; 203 + case 0xb1010: return cur_rev <= 0xb101046; break; 204 + case 0xb2040: return cur_rev <= 0xb204031; break; 205 + case 0xb4040: return cur_rev <= 0xb404031; break; 206 + case 0xb6000: return cur_rev <= 0xb600031; break; 207 + case 0xb7000: return cur_rev <= 0xb700031; break; 202 208 default: break; 203 209 } 204 210 ··· 220 214 struct sha256_state s; 221 215 int i; 222 216 223 - if (x86_family(bsp_cpuid_1_eax) < 0x17 || 224 - x86_family(bsp_cpuid_1_eax) > 0x19) 217 + if (x86_family(bsp_cpuid_1_eax) < 0x17) 225 218 return true; 226 219 227 220 if (!need_sha_check(cur_rev))

+1 -6

arch/x86/xen/enlighten.c

··· 103 103 void (*func)(void); 104 104 105 105 /* 106 - * Xen is supported only on CPUs with CPUID, so testing for 107 - * X86_FEATURE_CPUID is a test for early_cpu_init() having been 108 - * run. 109 - * 110 106 * Note that __xen_hypercall_setfunc() is noinstr only due to a nasty 111 107 * dependency chain: it is being called via the xen_hypercall static 112 108 * call when running as a PVH or HVM guest. Hypercalls need to be ··· 114 118 */ 115 119 instrumentation_begin(); 116 120 117 - if (!boot_cpu_has(X86_FEATURE_CPUID)) 118 - xen_get_vendor(); 121 + xen_get_vendor(); 119 122 120 123 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 121 124 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON))

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