Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-intel-next-fixes-2019-11-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
- Includes gvt-next-fixes-2019-11-12
- Fix Bugzilla #112051: Fix detection for a CMP-V PCH
- Fix Bugzilla #112256: Corrupted page table at address on plymouth splash
- Fix Bugzilla #111594: Avoid losing RC6 when HuC authentication is used
- Fix for OA/perf metric coherency, restore GT coarse power gating workaround
- Avoid atomic context on error capture
- Avoid MST bitmask overflowing to EDP/DPI input select
- Fixes to CI found dmesg splats
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191120204035.GA14908@jlahtine-desk.ger.corp.intel.com
+89
-53
+5
-4
drivers/gpu/drm/i915/display/intel_fbdev.c
+5
-4
drivers/gpu/drm/i915/display/intel_fbdev.c
···
234
234
info->apertures->ranges[0].base = ggtt->gmadr.start;
235
235
info->apertures->ranges[0].size = ggtt->mappable_end;
236
236
237
+
/* Our framebuffer is the entirety of fbdev's system memory */
238
+
info->fix.smem_start =
239
+
(unsigned long)(ggtt->gmadr.start + vma->node.start);
240
+
info->fix.smem_len = vma->node.size;
241
+
237
242
vaddr = i915_vma_pin_iomap(vma);
238
243
if (IS_ERR(vaddr)) {
239
244
DRM_ERROR("Failed to remap framebuffer into virtual memory\n");
···
247
242
}
248
243
info->screen_base = vaddr;
249
244
info->screen_size = vma->node.size;
250
-
251
-
/* Our framebuffer is the entirety of fbdev's system memory */
252
-
info->fix.smem_start = (unsigned long)info->screen_base;
253
-
info->fix.smem_len = info->screen_size;
254
245
255
246
drm_fb_helper_fill_info(info, &ifbdev->helper, sizes);
256
247
+1
-1
drivers/gpu/drm/i915/display/intel_sprite.c
+1
-1
drivers/gpu/drm/i915/display/intel_sprite.c
···
2885
2885
skl_universal_plane_create(struct drm_i915_private *dev_priv,
2886
2886
enum pipe pipe, enum plane_id plane_id)
2887
2887
{
2888
-
static const struct drm_plane_funcs *plane_funcs;
2888
+
const struct drm_plane_funcs *plane_funcs;
2889
2889
struct intel_plane *plane;
2890
2890
enum drm_plane_type plane_type;
2891
2891
unsigned int supported_rotations;
+1
drivers/gpu/drm/i915/gem/i915_gem_context.c
+1
drivers/gpu/drm/i915/gem/i915_gem_context.c
+3
-8
drivers/gpu/drm/i915/gt/intel_gt_requests.c
+3
-8
drivers/gpu/drm/i915/gt/intel_gt_requests.c
···
33
33
{
34
34
struct intel_gt_timelines *timelines = >->timelines;
35
35
struct intel_timeline *tl, *tn;
36
-
unsigned long active_count = 0;
37
36
unsigned long flags;
38
37
bool interruptible;
39
38
LIST_HEAD(free);
···
45
46
46
47
spin_lock_irqsave(&timelines->lock, flags);
47
48
list_for_each_entry_safe(tl, tn, &timelines->active_list, link) {
48
-
if (!mutex_trylock(&tl->mutex)) {
49
-
active_count++; /* report busy to caller, try again? */
49
+
if (!mutex_trylock(&tl->mutex))
50
50
continue;
51
-
}
52
51
53
52
intel_timeline_get(tl);
54
53
GEM_BUG_ON(!tl->active_count);
···
71
74
72
75
/* Resume iteration after dropping lock */
73
76
list_safe_reset_next(tl, tn, link);
74
-
if (--tl->active_count)
75
-
active_count += !!rcu_access_pointer(tl->last_request.fence);
76
-
else
77
+
if (!--tl->active_count)
77
78
list_del(&tl->link);
78
79
79
80
mutex_unlock(&tl->mutex);
···
87
92
list_for_each_entry_safe(tl, tn, &free, link)
88
93
__intel_timeline_free(&tl->kref);
89
94
90
-
return active_count ? timeout : 0;
95
+
return list_empty(&timelines->active_list) ? 0 : timeout;
91
96
}
92
97
93
98
int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
+7
-2
drivers/gpu/drm/i915/gt/intel_rc6.c
+7
-2
drivers/gpu/drm/i915/gt/intel_rc6.c
···
178
178
GEN6_RC_CTL_RC6_ENABLE |
179
179
rc6_mode);
180
180
181
-
set(uncore, GEN9_PG_ENABLE,
182
-
GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
181
+
/*
182
+
* WaRsDisableCoarsePowerGating:skl,cnl
183
+
* - Render/Media PG need to be disabled with RC6.
184
+
*/
185
+
if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6)))
186
+
set(uncore, GEN9_PG_ENABLE,
187
+
GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
183
188
}
184
189
185
190
static void gen8_rc6_enable(struct intel_rc6 *rc6)
+15
drivers/gpu/drm/i915/gt/uc/intel_guc.c
+15
drivers/gpu/drm/i915/gt/uc/intel_guc.c
···
554
554
};
555
555
556
556
/*
557
+
* If GuC communication is enabled but submission is not supported,
558
+
* we do not need to suspend the GuC.
559
+
*/
560
+
if (!intel_guc_submission_is_enabled(guc))
561
+
return 0;
562
+
563
+
/*
557
564
* The ENTER_S_STATE action queues the save/restore operation in GuC FW
558
565
* and then returns, so waiting on the H2G is not enough to guarantee
559
566
* GuC is done. When all the processing is done, GuC writes
···
616
609
INTEL_GUC_ACTION_EXIT_S_STATE,
617
610
GUC_POWER_D0,
618
611
};
612
+
613
+
/*
614
+
* If GuC communication is enabled but submission is not supported,
615
+
* we do not need to resume the GuC but we do need to enable the
616
+
* GuC communication on resume (above).
617
+
*/
618
+
if (!intel_guc_submission_is_enabled(guc))
619
+
return 0;
619
620
620
621
return intel_guc_send(guc, action, ARRAY_SIZE(action));
621
622
}
+4
drivers/gpu/drm/i915/gvt/handlers.c
+4
drivers/gpu/drm/i915/gvt/handlers.c
···
3420
3420
}
3421
3421
3422
3422
for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
3423
+
/* pvinfo data doesn't come from hw mmio */
3424
+
if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE)
3425
+
continue;
3426
+
3423
3427
for (j = 0; j < block->size; j += 4) {
3424
3428
ret = handler(gvt,
3425
3429
i915_mmio_reg_offset(block->offset) + j,
+28
-29
drivers/gpu/drm/i915/i915_active.c
+28
-29
drivers/gpu/drm/i915/i915_active.c
···
91
91
92
92
static void debug_active_activate(struct i915_active *ref)
93
93
{
94
-
lockdep_assert_held(&ref->mutex);
94
+
spin_lock_irq(&ref->tree_lock);
95
95
if (!atomic_read(&ref->count)) /* before the first inc */
96
96
debug_object_activate(ref, &active_debug_desc);
97
+
spin_unlock_irq(&ref->tree_lock);
97
98
}
98
99
99
100
static void debug_active_deactivate(struct i915_active *ref)
100
101
{
101
-
lockdep_assert_held(&ref->mutex);
102
+
lockdep_assert_held(&ref->tree_lock);
102
103
if (!atomic_read(&ref->count)) /* after the last dec */
103
104
debug_object_deactivate(ref, &active_debug_desc);
104
105
}
···
129
128
{
130
129
struct active_node *it, *n;
131
130
struct rb_root root;
132
-
bool retire = false;
131
+
unsigned long flags;
133
132
134
-
lockdep_assert_held(&ref->mutex);
135
133
GEM_BUG_ON(i915_active_is_idle(ref));
136
134
137
135
/* return the unused nodes to our slabcache -- flushing the allocator */
138
-
if (atomic_dec_and_test(&ref->count)) {
139
-
debug_active_deactivate(ref);
140
-
root = ref->tree;
141
-
ref->tree = RB_ROOT;
142
-
ref->cache = NULL;
143
-
retire = true;
144
-
}
145
-
146
-
mutex_unlock(&ref->mutex);
147
-
if (!retire)
136
+
if (!atomic_dec_and_lock_irqsave(&ref->count, &ref->tree_lock, flags))
148
137
return;
149
138
150
139
GEM_BUG_ON(rcu_access_pointer(ref->excl.fence));
151
-
rbtree_postorder_for_each_entry_safe(it, n, &root, node) {
152
-
GEM_BUG_ON(i915_active_fence_isset(&it->base));
153
-
kmem_cache_free(global.slab_cache, it);
154
-
}
140
+
debug_active_deactivate(ref);
141
+
142
+
root = ref->tree;
143
+
ref->tree = RB_ROOT;
144
+
ref->cache = NULL;
145
+
146
+
spin_unlock_irqrestore(&ref->tree_lock, flags);
155
147
156
148
/* After the final retire, the entire struct may be freed */
157
149
if (ref->retire)
···
152
158
153
159
/* ... except if you wait on it, you must manage your own references! */
154
160
wake_up_var(ref);
161
+
162
+
rbtree_postorder_for_each_entry_safe(it, n, &root, node) {
163
+
GEM_BUG_ON(i915_active_fence_isset(&it->base));
164
+
kmem_cache_free(global.slab_cache, it);
165
+
}
155
166
}
156
167
157
168
static void
···
168
169
if (atomic_add_unless(&ref->count, -1, 1))
169
170
return;
170
171
171
-
mutex_lock(&ref->mutex);
172
172
__active_retire(ref);
173
173
}
174
174
···
178
180
if (atomic_add_unless(&ref->count, -1, 1))
179
181
return;
180
182
181
-
/* If we are inside interrupt context (fence signaling), defer */
182
-
if (ref->flags & I915_ACTIVE_RETIRE_SLEEPS ||
183
-
!mutex_trylock(&ref->mutex)) {
183
+
if (ref->flags & I915_ACTIVE_RETIRE_SLEEPS) {
184
184
queue_work(system_unbound_wq, &ref->work);
185
185
return;
186
186
}
···
223
227
if (!prealloc)
224
228
return NULL;
225
229
226
-
mutex_lock(&ref->mutex);
230
+
spin_lock_irq(&ref->tree_lock);
227
231
GEM_BUG_ON(i915_active_is_idle(ref));
228
232
229
233
parent = NULL;
···
253
257
254
258
out:
255
259
ref->cache = node;
256
-
mutex_unlock(&ref->mutex);
260
+
spin_unlock_irq(&ref->tree_lock);
257
261
258
262
BUILD_BUG_ON(offsetof(typeof(*node), base));
259
263
return &node->base;
···
274
278
if (bits & I915_ACTIVE_MAY_SLEEP)
275
279
ref->flags |= I915_ACTIVE_RETIRE_SLEEPS;
276
280
281
+
spin_lock_init(&ref->tree_lock);
277
282
ref->tree = RB_ROOT;
278
283
ref->cache = NULL;
284
+
279
285
init_llist_head(&ref->preallocated_barriers);
280
286
atomic_set(&ref->count, 0);
281
287
__mutex_init(&ref->mutex, "i915_active", key);
···
508
510
if (RB_EMPTY_ROOT(&ref->tree))
509
511
return NULL;
510
512
511
-
mutex_lock(&ref->mutex);
513
+
spin_lock_irq(&ref->tree_lock);
512
514
GEM_BUG_ON(i915_active_is_idle(ref));
513
515
514
516
/*
···
573
575
goto match;
574
576
}
575
577
576
-
mutex_unlock(&ref->mutex);
578
+
spin_unlock_irq(&ref->tree_lock);
577
579
578
580
return NULL;
579
581
···
581
583
rb_erase(p, &ref->tree); /* Hide from waits and sibling allocations */
582
584
if (p == &ref->cache->node)
583
585
ref->cache = NULL;
584
-
mutex_unlock(&ref->mutex);
586
+
spin_unlock_irq(&ref->tree_lock);
585
587
586
588
return rb_entry(p, struct active_node, node);
587
589
}
···
662
664
void i915_active_acquire_barrier(struct i915_active *ref)
663
665
{
664
666
struct llist_node *pos, *next;
667
+
unsigned long flags;
665
668
666
669
GEM_BUG_ON(i915_active_is_idle(ref));
667
670
···
672
673
* populated by i915_request_add_active_barriers() to point to the
673
674
* request that will eventually release them.
674
675
*/
675
-
mutex_lock_nested(&ref->mutex, SINGLE_DEPTH_NESTING);
676
+
spin_lock_irqsave_nested(&ref->tree_lock, flags, SINGLE_DEPTH_NESTING);
676
677
llist_for_each_safe(pos, next, take_preallocated_barriers(ref)) {
677
678
struct active_node *node = barrier_from_ll(pos);
678
679
struct intel_engine_cs *engine = barrier_to_engine(node);
···
698
699
llist_add(barrier_to_ll(node), &engine->barrier_tasks);
699
700
intel_engine_pm_put(engine);
700
701
}
701
-
mutex_unlock(&ref->mutex);
702
+
spin_unlock_irqrestore(&ref->tree_lock, flags);
702
703
}
703
704
704
705
void i915_request_add_active_barriers(struct i915_request *rq)
+1
drivers/gpu/drm/i915/i915_active_types.h
+1
drivers/gpu/drm/i915/i915_active_types.h
+6
drivers/gpu/drm/i915/i915_drv.h
+6
drivers/gpu/drm/i915/i915_drv.h
+4
-4
drivers/gpu/drm/i915/i915_gpu_error.c
+4
-4
drivers/gpu/drm/i915/i915_gpu_error.c
···
1029
1029
for_each_sgt_daddr(dma, iter, vma->pages) {
1030
1030
void __iomem *s;
1031
1031
1032
-
s = io_mapping_map_atomic_wc(&mem->iomap, dma);
1032
+
s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE);
1033
1033
ret = compress_page(compress, (void __force *)s, dst);
1034
-
io_mapping_unmap_atomic(s);
1034
+
io_mapping_unmap(s);
1035
1035
if (ret)
1036
1036
break;
1037
1037
}
···
1043
1043
1044
1044
drm_clflush_pages(&page, 1);
1045
1045
1046
-
s = kmap_atomic(page);
1046
+
s = kmap(page);
1047
1047
ret = compress_page(compress, s, dst);
1048
-
kunmap_atomic(s);
1048
+
kunmap(s);
1049
1049
1050
1050
drm_clflush_pages(&page, 1);
1051
1051
+7
-2
drivers/gpu/drm/i915/i915_perf.c
+7
-2
drivers/gpu/drm/i915/i915_perf.c
···
1870
1870
config_length += num_lri_dwords(oa_config->mux_regs_len);
1871
1871
config_length += num_lri_dwords(oa_config->b_counter_regs_len);
1872
1872
config_length += num_lri_dwords(oa_config->flex_regs_len);
1873
-
config_length++; /* MI_BATCH_BUFFER_END */
1873
+
config_length += 3; /* MI_BATCH_BUFFER_START */
1874
1874
config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE);
1875
1875
1876
1876
obj = i915_gem_object_create_shmem(stream->perf->i915, config_length);
···
1895
1895
oa_config->flex_regs,
1896
1896
oa_config->flex_regs_len);
1897
1897
1898
-
*cs++ = MI_BATCH_BUFFER_END;
1898
+
/* Jump into the active wait. */
1899
+
*cs++ = (INTEL_GEN(stream->perf->i915) < 8 ?
1900
+
MI_BATCH_BUFFER_START :
1901
+
MI_BATCH_BUFFER_START_GEN8);
1902
+
*cs++ = i915_ggtt_offset(stream->noa_wait);
1903
+
*cs++ = 0;
1899
1904
1900
1905
i915_gem_object_flush_map(obj);
1901
1906
i915_gem_object_unpin_map(obj);
+1
-1
drivers/gpu/drm/i915/i915_reg.h
+1
-1
drivers/gpu/drm/i915/i915_reg.h
···
9671
9671
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
9672
9672
#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
9673
9673
#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
9674
-
#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(12, 10)
9674
+
#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
9675
9675
#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
9676
9676
REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
9677
9677
#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
+5
-1
drivers/gpu/drm/i915/intel_pch.c
+5
-1
drivers/gpu/drm/i915/intel_pch.c
···
62
62
/* KBP is SPT compatible */
63
63
return PCH_SPT;
64
64
case INTEL_PCH_CNP_DEVICE_ID_TYPE:
65
-
case INTEL_PCH_CNP2_DEVICE_ID_TYPE:
66
65
DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
67
66
WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
68
67
return PCH_CNP;
···
75
76
WARN_ON(!IS_COFFEELAKE(dev_priv));
76
77
/* CometPoint is CNP Compatible */
77
78
return PCH_CNP;
79
+
case INTEL_PCH_CMP_V_DEVICE_ID_TYPE:
80
+
DRM_DEBUG_KMS("Found Comet Lake V PCH (CMP-V)\n");
81
+
WARN_ON(!IS_COFFEELAKE(dev_priv));
82
+
/* Comet Lake V PCH is based on KBP, which is SPT compatible */
83
+
return PCH_SPT;
78
84
case INTEL_PCH_ICP_DEVICE_ID_TYPE:
79
85
DRM_DEBUG_KMS("Found Ice Lake PCH\n");
80
86
WARN_ON(!IS_ICELAKE(dev_priv));
+1
-1
drivers/gpu/drm/i915/intel_pch.h
+1
-1
drivers/gpu/drm/i915/intel_pch.h
···
40
40
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
41
41
#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
42
42
#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
43
-
#define INTEL_PCH_CNP2_DEVICE_ID_TYPE 0xA380
44
43
#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
45
44
#define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
46
45
#define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680
46
+
#define INTEL_PCH_CMP_V_DEVICE_ID_TYPE 0xA380
47
47
#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
48
48
#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
49
49
#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080