Merge tag 'pci-v6.18-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

+2 -2

arch/mips/mti-malta/malta-setup.c

··· 47 47 .name = "keyboard", 48 48 .start = 0x60, 49 49 .end = 0x6f, 50 - .flags = IORESOURCE_IO | IORESOURCE_BUSY 50 + .flags = IORESOURCE_IO 51 51 }, 52 52 { 53 53 .name = "dma page reg", ··· 213 213 214 214 /* Request I/O space for devices used on the Malta board. */ 215 215 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) 216 - request_resource(&ioport_resource, standard_io_resources+i); 216 + insert_resource(&ioport_resource, standard_io_resources + i); 217 217 218 218 /* 219 219 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.

+1 -2

arch/mips/pci/pci-malta.c

··· 230 230 } 231 231 232 232 /* PIIX4 ACPI starts at 0x1000 */ 233 - if (controller->io_resource->start < 0x00001000UL) 234 - controller->io_resource->start = 0x00001000UL; 233 + PCIBIOS_MIN_IO = 0x1000; 235 234 236 235 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ 237 236 ioport_resource.end = controller->io_resource->end;

+24 -4

drivers/pci/controller/dwc/pcie-designware-host.c

··· 23 23 #include "pcie-designware.h" 24 24 25 25 static struct pci_ops dw_pcie_ops; 26 + static struct pci_ops dw_pcie_ecam_ops; 26 27 static struct pci_ops dw_child_pcie_ops; 27 28 28 29 #define DW_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ ··· 472 471 if (IS_ERR(pp->cfg)) 473 472 return PTR_ERR(pp->cfg); 474 473 475 - pci->dbi_base = pp->cfg->win; 476 - pci->dbi_phys_addr = res->start; 477 - 478 474 return 0; 479 475 } 480 476 ··· 527 529 if (ret) 528 530 return ret; 529 531 530 - pp->bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; 532 + pp->bridge->ops = &dw_pcie_ecam_ops; 531 533 pp->bridge->sysdata = pp->cfg; 532 534 pp->cfg->priv = pp; 533 535 } else { ··· 840 842 } 841 843 EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); 842 844 845 + static void __iomem *dw_pcie_ecam_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) 846 + { 847 + struct pci_config_window *cfg = bus->sysdata; 848 + struct dw_pcie_rp *pp = cfg->priv; 849 + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 850 + unsigned int busn = bus->number; 851 + 852 + if (busn > 0) 853 + return pci_ecam_map_bus(bus, devfn, where); 854 + 855 + if (PCI_SLOT(devfn) > 0) 856 + return NULL; 857 + 858 + return pci->dbi_base + where; 859 + } 860 + 843 861 static struct pci_ops dw_pcie_ops = { 844 862 .map_bus = dw_pcie_own_conf_map_bus, 863 + .read = pci_generic_config_read, 864 + .write = pci_generic_config_write, 865 + }; 866 + 867 + static struct pci_ops dw_pcie_ecam_ops = { 868 + .map_bus = dw_pcie_ecam_conf_map_bus, 845 869 .read = pci_generic_config_read, 846 870 .write = pci_generic_config_write, 847 871 };

-68

drivers/pci/controller/dwc/pcie-qcom.c

··· 55 55 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 56 56 #define PARF_Q2A_FLUSH 0x1ac 57 57 #define PARF_LTSSM 0x1b0 58 - #define PARF_SLV_DBI_ELBI 0x1b4 59 58 #define PARF_INT_ALL_STATUS 0x224 60 59 #define PARF_INT_ALL_CLEAR 0x228 61 60 #define PARF_INT_ALL_MASK 0x22c ··· 64 65 #define PARF_DBI_BASE_ADDR_V2_HI 0x354 65 66 #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 66 67 #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c 67 - #define PARF_BLOCK_SLV_AXI_WR_BASE 0x360 68 - #define PARF_BLOCK_SLV_AXI_WR_BASE_HI 0x364 69 - #define PARF_BLOCK_SLV_AXI_WR_LIMIT 0x368 70 - #define PARF_BLOCK_SLV_AXI_WR_LIMIT_HI 0x36c 71 - #define PARF_BLOCK_SLV_AXI_RD_BASE 0x370 72 - #define PARF_BLOCK_SLV_AXI_RD_BASE_HI 0x374 73 - #define PARF_BLOCK_SLV_AXI_RD_LIMIT 0x378 74 - #define PARF_BLOCK_SLV_AXI_RD_LIMIT_HI 0x37c 75 - #define PARF_ECAM_BASE 0x380 76 - #define PARF_ECAM_BASE_HI 0x384 77 68 #define PARF_NO_SNOOP_OVERRIDE 0x3d4 78 69 #define PARF_ATU_BASE_ADDR 0x634 79 70 #define PARF_ATU_BASE_ADDR_HI 0x638 ··· 87 98 88 99 /* PARF_SYS_CTRL register fields */ 89 100 #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) 90 - #define PCIE_ECAM_BLOCKER_EN BIT(26) 91 101 #define MST_WAKEUP_EN BIT(13) 92 102 #define SLV_WAKEUP_EN BIT(12) 93 103 #define MSTR_ACLK_CGC_DIS BIT(10) ··· 133 145 134 146 /* PARF_LTSSM register fields */ 135 147 #define LTSSM_EN BIT(8) 136 - 137 - /* PARF_SLV_DBI_ELBI */ 138 - #define SLV_DBI_ELBI_ADDR_BASE GENMASK(11, 0) 139 148 140 149 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ 141 150 #define PARF_INT_ALL_LINK_UP BIT(13) ··· 309 324 /* Ensure that PERST has been asserted for at least 100 ms */ 310 325 msleep(PCIE_T_PVPERL_MS); 311 326 qcom_perst_assert(pcie, false); 312 - } 313 - 314 - static void qcom_pci_config_ecam(struct dw_pcie_rp *pp) 315 - { 316 - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 317 - struct qcom_pcie *pcie = to_qcom_pcie(pci); 318 - u64 addr, addr_end; 319 - u32 val; 320 - 321 - writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE); 322 - writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI); 323 - 324 - /* 325 - * The only device on the root bus is a single Root Port. If we try to 326 - * access any devices other than Device/Function 00.0 on Bus 0, the TLP 327 - * will go outside of the controller to the PCI bus. But with CFG Shift 328 - * Feature (ECAM) enabled in iATU, there is no guarantee that the 329 - * response is going to be all F's. Hence, to make sure that the 330 - * requester gets all F's response for accesses other than the Root 331 - * Port, configure iATU to block the transactions starting from 332 - * function 1 of the root bus to the end of the root bus (i.e., from 333 - * dbi_base + 4KB to dbi_base + 1MB). 334 - */ 335 - addr = pci->dbi_phys_addr + SZ_4K; 336 - writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE); 337 - writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI); 338 - 339 - writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE); 340 - writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI); 341 - 342 - addr_end = pci->dbi_phys_addr + SZ_1M - 1; 343 - 344 - writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT); 345 - writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI); 346 - 347 - writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT); 348 - writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI); 349 - 350 - val = readl_relaxed(pcie->parf + PARF_SYS_CTRL); 351 - val |= PCIE_ECAM_BLOCKER_EN; 352 - writel_relaxed(val, pcie->parf + PARF_SYS_CTRL); 353 327 } 354 328 355 329 static int qcom_pcie_start_link(struct dw_pcie *pci) ··· 1264 1320 { 1265 1321 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1266 1322 struct qcom_pcie *pcie = to_qcom_pcie(pci); 1267 - u16 offset; 1268 1323 int ret; 1269 1324 1270 1325 qcom_ep_reset_assert(pcie); ··· 1271 1328 ret = pcie->cfg->ops->init(pcie); 1272 1329 if (ret) 1273 1330 return ret; 1274 - 1275 - if (pp->ecam_enabled) { 1276 - /* 1277 - * Override ELBI when ECAM is enabled, as when ECAM is enabled, 1278 - * ELBI moves under the 'config' space. 1279 - */ 1280 - offset = FIELD_GET(SLV_DBI_ELBI_ADDR_BASE, readl(pcie->parf + PARF_SLV_DBI_ELBI)); 1281 - pci->elbi_base = pci->dbi_base + offset; 1282 - 1283 - qcom_pci_config_ecam(pp); 1284 - } 1285 1331 1286 1332 ret = qcom_pcie_phy_power_on(pcie); 1287 1333 if (ret)

+9 -25

drivers/pci/pcie/aspm.c

··· 243 243 /* Clock PM state */ 244 244 u32 clkpm_capable:1; /* Clock PM capable? */ 245 245 u32 clkpm_enabled:1; /* Current Clock PM state */ 246 - u32 clkpm_default:1; /* Default Clock PM state by BIOS or 247 - override */ 246 + u32 clkpm_default:1; /* Default Clock PM state by BIOS */ 248 247 u32 clkpm_disable:1; /* Clock PM disabled */ 249 248 }; 250 249 ··· 375 376 pcie_set_clkpm_nocheck(link, enable); 376 377 } 377 378 378 - static void pcie_clkpm_override_default_link_state(struct pcie_link_state *link, 379 - int enabled) 380 - { 381 - struct pci_dev *pdev = link->downstream; 382 - 383 - /* For devicetree platforms, enable ClockPM by default */ 384 - if (of_have_populated_dt() && !enabled) { 385 - link->clkpm_default = 1; 386 - pci_info(pdev, "ASPM: DT platform, enabling ClockPM\n"); 387 - } 388 - } 389 - 390 379 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) 391 380 { 392 381 int capable = 1, enabled = 1; ··· 397 410 } 398 411 link->clkpm_enabled = enabled; 399 412 link->clkpm_default = enabled; 400 - pcie_clkpm_override_default_link_state(link, enabled); 401 413 link->clkpm_capable = capable; 402 414 link->clkpm_disable = blacklist ? 1 : 0; 403 415 } ··· 797 811 struct pci_dev *pdev = link->downstream; 798 812 u32 override; 799 813 800 - /* For devicetree platforms, enable all ASPM states by default */ 814 + /* For devicetree platforms, enable L0s and L1 by default */ 801 815 if (of_have_populated_dt()) { 802 - link->aspm_default = PCIE_LINK_STATE_ASPM_ALL; 816 + if (link->aspm_support & PCIE_LINK_STATE_L0S) 817 + link->aspm_default |= PCIE_LINK_STATE_L0S; 818 + if (link->aspm_support & PCIE_LINK_STATE_L1) 819 + link->aspm_default |= PCIE_LINK_STATE_L1; 803 820 override = link->aspm_default & ~link->aspm_enabled; 804 821 if (override) 805 - pci_info(pdev, "ASPM: DT platform, enabling%s%s%s%s%s%s%s\n", 806 - FLAG(override, L0S_UP, " L0s-up"), 807 - FLAG(override, L0S_DW, " L0s-dw"), 808 - FLAG(override, L1, " L1"), 809 - FLAG(override, L1_1, " ASPM-L1.1"), 810 - FLAG(override, L1_2, " ASPM-L1.2"), 811 - FLAG(override, L1_1_PCIPM, " PCI-PM-L1.1"), 812 - FLAG(override, L1_2_PCIPM, " PCI-PM-L1.2")); 822 + pci_info(pdev, "ASPM: default states%s%s\n", 823 + FLAG(override, L0S, " L0s"), 824 + FLAG(override, L1, " L1")); 813 825 } 814 826 } 815 827

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