tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-for-v4.12-rc7' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"A varied bunch of fixes, one for an API regression with connectors.

Otherwise amdgpu and i915 have a bunch of varied fixes, the shrinker
ones being the most important"

* tag 'drm-fixes-for-v4.12-rc7' of git://people.freedesktop.org/~airlied/linux:
drm: Fix GETCONNECTOR regression
drm/radeon: add a quirk for Toshiba Satellite L20-183
drm/radeon: add a PX quirk for another K53TK variant
drm/amdgpu: adjust default display clock
drm/amdgpu/atom: fix ps allocation size for EnableDispPowerGating
drm/amdgpu: add Polaris12 DID
drm/i915: Don't enable backlight at setup time.
drm/i915: Plumb the correct acquire ctx into intel_crtc_disable_noatomic()
drm/i915: Fix deadlock witha the pipe A quirk during resume
drm/i915: Remove __GFP_NORETRY from our buffer allocator
drm/i915: Encourage our shrinker more when our shmemfs allocations fails
drm/i915: Differentiate between sw write location into ring and last hw read

Linus Torvalds 311548f1 7139a06b

+144 -79
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
··· 693 693 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", 694 694 adev->clock.default_dispclk / 100); 695 695 adev->clock.default_dispclk = 60000; 696 + } else if (adev->clock.default_dispclk <= 60000) { 697 + DRM_INFO("Changing default dispclk from %dMhz to 625Mhz\n", 698 + adev->clock.default_dispclk / 100); 699 + adev->clock.default_dispclk = 62500; 696 700 } 697 701 adev->clock.dp_extclk = 698 702 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 449 449 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 450 450 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 451 451 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 452 + {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 452 453 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 453 454 /* Vega 10 */ 454 455 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
+2 -2
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
··· 165 165 struct drm_device *dev = crtc->dev; 166 166 struct amdgpu_device *adev = dev->dev_private; 167 167 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); 168 - ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; 168 + ENABLE_DISP_POWER_GATING_PS_ALLOCATION args; 169 169 170 170 memset(&args, 0, sizeof(args)); 171 171 ··· 178 178 void amdgpu_atombios_crtc_powergate_init(struct amdgpu_device *adev) 179 179 { 180 180 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); 181 - ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; 181 + ENABLE_DISP_POWER_GATING_PS_ALLOCATION args; 182 182 183 183 memset(&args, 0, sizeof(args)); 184 184
+20 -18
drivers/gpu/drm/drm_connector.c
··· 1229 1229 if (!connector) 1230 1230 return -ENOENT; 1231 1231 1232 - drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1233 - encoder = drm_connector_get_encoder(connector); 1234 - if (encoder) 1235 - out_resp->encoder_id = encoder->base.id; 1236 - else 1237 - out_resp->encoder_id = 0; 1238 - 1239 - ret = drm_mode_object_get_properties(&connector->base, file_priv->atomic, 1240 - (uint32_t __user *)(unsigned long)(out_resp->props_ptr), 1241 - (uint64_t __user *)(unsigned long)(out_resp->prop_values_ptr), 1242 - &out_resp->count_props); 1243 - drm_modeset_unlock(&dev->mode_config.connection_mutex); 1244 - if (ret) 1245 - goto out_unref; 1246 - 1247 1232 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) 1248 1233 if (connector->encoder_ids[i] != 0) 1249 1234 encoders_count++; ··· 1241 1256 if (put_user(connector->encoder_ids[i], 1242 1257 encoder_ptr + copied)) { 1243 1258 ret = -EFAULT; 1244 - goto out_unref; 1259 + goto out; 1245 1260 } 1246 1261 copied++; 1247 1262 } ··· 1285 1300 if (copy_to_user(mode_ptr + copied, 1286 1301 &u_mode, sizeof(u_mode))) { 1287 1302 ret = -EFAULT; 1303 + mutex_unlock(&dev->mode_config.mutex); 1304 + 1288 1305 goto out; 1289 1306 } 1290 1307 copied++; 1291 1308 } 1292 1309 } 1293 1310 out_resp->count_modes = mode_count; 1294 - out: 1295 1311 mutex_unlock(&dev->mode_config.mutex); 1296 - out_unref: 1312 + 1313 + drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1314 + encoder = drm_connector_get_encoder(connector); 1315 + if (encoder) 1316 + out_resp->encoder_id = encoder->base.id; 1317 + else 1318 + out_resp->encoder_id = 0; 1319 + 1320 + /* Only grab properties after probing, to make sure EDID and other 1321 + * properties reflect the latest status. */ 1322 + ret = drm_mode_object_get_properties(&connector->base, file_priv->atomic, 1323 + (uint32_t __user *)(unsigned long)(out_resp->props_ptr), 1324 + (uint64_t __user *)(unsigned long)(out_resp->prop_values_ptr), 1325 + &out_resp->count_props); 1326 + drm_modeset_unlock(&dev->mode_config.connection_mutex); 1327 + 1328 + out: 1297 1329 drm_connector_put(connector); 1298 1330 1299 1331 return ret;
+41 -20
drivers/gpu/drm/i915/i915_gem.c
··· 2285 2285 struct page *page; 2286 2286 unsigned long last_pfn = 0; /* suppress gcc warning */ 2287 2287 unsigned int max_segment; 2288 + gfp_t noreclaim; 2288 2289 int ret; 2289 - gfp_t gfp; 2290 2290 2291 2291 /* Assert that the object is not currently in any GPU domain. As it 2292 2292 * wasn't in the GTT, there shouldn't be any way it could have been in ··· 2315 2315 * Fail silently without starting the shrinker 2316 2316 */ 2317 2317 mapping = obj->base.filp->f_mapping; 2318 - gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); 2319 - gfp |= __GFP_NORETRY | __GFP_NOWARN; 2318 + noreclaim = mapping_gfp_constraint(mapping, 2319 + ~(__GFP_IO | __GFP_RECLAIM)); 2320 + noreclaim |= __GFP_NORETRY | __GFP_NOWARN; 2321 + 2320 2322 sg = st->sgl; 2321 2323 st->nents = 0; 2322 2324 for (i = 0; i < page_count; i++) { 2323 - page = shmem_read_mapping_page_gfp(mapping, i, gfp); 2324 - if (unlikely(IS_ERR(page))) { 2325 - i915_gem_shrink(dev_priv, 2326 - page_count, 2327 - I915_SHRINK_BOUND | 2328 - I915_SHRINK_UNBOUND | 2329 - I915_SHRINK_PURGEABLE); 2325 + const unsigned int shrink[] = { 2326 + I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE, 2327 + 0, 2328 + }, *s = shrink; 2329 + gfp_t gfp = noreclaim; 2330 + 2331 + do { 2330 2332 page = shmem_read_mapping_page_gfp(mapping, i, gfp); 2331 - } 2332 - if (unlikely(IS_ERR(page))) { 2333 - gfp_t reclaim; 2333 + if (likely(!IS_ERR(page))) 2334 + break; 2335 + 2336 + if (!*s) { 2337 + ret = PTR_ERR(page); 2338 + goto err_sg; 2339 + } 2340 + 2341 + i915_gem_shrink(dev_priv, 2 * page_count, *s++); 2342 + cond_resched(); 2334 2343 2335 2344 /* We've tried hard to allocate the memory by reaping 2336 2345 * our own buffer, now let the real VM do its job and ··· 2349 2340 * defer the oom here by reporting the ENOMEM back 2350 2341 * to userspace. 2351 2342 */ 2352 - reclaim = mapping_gfp_mask(mapping); 2353 - reclaim |= __GFP_NORETRY; /* reclaim, but no oom */ 2343 + if (!*s) { 2344 + /* reclaim and warn, but no oom */ 2345 + gfp = mapping_gfp_mask(mapping); 2354 2346 2355 - page = shmem_read_mapping_page_gfp(mapping, i, reclaim); 2356 - if (IS_ERR(page)) { 2357 - ret = PTR_ERR(page); 2358 - goto err_sg; 2347 + /* Our bo are always dirty and so we require 2348 + * kswapd to reclaim our pages (direct reclaim 2349 + * does not effectively begin pageout of our 2350 + * buffers on its own). However, direct reclaim 2351 + * only waits for kswapd when under allocation 2352 + * congestion. So as a result __GFP_RECLAIM is 2353 + * unreliable and fails to actually reclaim our 2354 + * dirty pages -- unless you try over and over 2355 + * again with !__GFP_NORETRY. However, we still 2356 + * want to fail this allocation rather than 2357 + * trigger the out-of-memory killer and for 2358 + * this we want the future __GFP_MAYFAIL. 2359 + */ 2359 2360 } 2360 - } 2361 + } while (1); 2362 + 2361 2363 if (!i || 2362 2364 sg->length >= max_segment || 2363 2365 page_to_pfn(page) != last_pfn + 1) { ··· 4242 4222 4243 4223 mapping = obj->base.filp->f_mapping; 4244 4224 mapping_set_gfp_mask(mapping, mask); 4225 + GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM)); 4245 4226 4246 4227 i915_gem_object_init(obj, &i915_gem_object_ops); 4247 4228
+1 -1
drivers/gpu/drm/i915/i915_gem_request.c
··· 623 623 * GPU processing the request, we never over-estimate the 624 624 * position of the head. 625 625 */ 626 - req->head = req->ring->tail; 626 + req->head = req->ring->emit; 627 627 628 628 /* Check that we didn't interrupt ourselves with a new request */ 629 629 GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
+1 -3
drivers/gpu/drm/i915/i915_guc_submission.c
··· 480 480 GEM_BUG_ON(freespace < wqi_size); 481 481 482 482 /* The GuC firmware wants the tail index in QWords, not bytes */ 483 - tail = rq->tail; 484 - assert_ring_tail_valid(rq->ring, rq->tail); 485 - tail >>= 3; 483 + tail = intel_ring_set_tail(rq->ring, rq->tail) >> 3; 486 484 GEM_BUG_ON(tail > WQ_RING_TAIL_MAX); 487 485 488 486 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
+17 -13
drivers/gpu/drm/i915/intel_display.c
··· 120 120 static void skylake_pfit_enable(struct intel_crtc *crtc); 121 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); 122 122 static void ironlake_pfit_enable(struct intel_crtc *crtc); 123 - static void intel_modeset_setup_hw_state(struct drm_device *dev); 123 + static void intel_modeset_setup_hw_state(struct drm_device *dev, 124 + struct drm_modeset_acquire_ctx *ctx); 124 125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); 125 126 126 127 struct intel_limit { ··· 3450 3449 struct drm_crtc *crtc; 3451 3450 int i, ret; 3452 3451 3453 - intel_modeset_setup_hw_state(dev); 3452 + intel_modeset_setup_hw_state(dev, ctx); 3454 3453 i915_redisable_vga(to_i915(dev)); 3455 3454 3456 3455 if (!state) ··· 5826 5825 intel_update_watermarks(intel_crtc); 5827 5826 } 5828 5827 5829 - static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) 5828 + static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, 5829 + struct drm_modeset_acquire_ctx *ctx) 5830 5830 { 5831 5831 struct intel_encoder *encoder; 5832 5832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ··· 5857 5855 return; 5858 5856 } 5859 5857 5860 - state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; 5858 + state->acquire_ctx = ctx; 5861 5859 5862 5860 /* Everything's already locked, -EDEADLK can't happen. */ 5863 5861 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); ··· 15032 15030 intel_setup_outputs(dev_priv); 15033 15031 15034 15032 drm_modeset_lock_all(dev); 15035 - intel_modeset_setup_hw_state(dev); 15033 + intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); 15036 15034 drm_modeset_unlock_all(dev); 15037 15035 15038 15036 for_each_intel_crtc(dev, crtc) { ··· 15069 15067 return 0; 15070 15068 } 15071 15069 15072 - static void intel_enable_pipe_a(struct drm_device *dev) 15070 + static void intel_enable_pipe_a(struct drm_device *dev, 15071 + struct drm_modeset_acquire_ctx *ctx) 15073 15072 { 15074 15073 struct intel_connector *connector; 15075 15074 struct drm_connector_list_iter conn_iter; 15076 15075 struct drm_connector *crt = NULL; 15077 15076 struct intel_load_detect_pipe load_detect_temp; 15078 - struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; 15079 15077 int ret; 15080 15078 15081 15079 /* We can't just switch on the pipe A, we need to set things up with a ··· 15147 15145 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); 15148 15146 } 15149 15147 15150 - static void intel_sanitize_crtc(struct intel_crtc *crtc) 15148 + static void intel_sanitize_crtc(struct intel_crtc *crtc, 15149 + struct drm_modeset_acquire_ctx *ctx) 15151 15150 { 15152 15151 struct drm_device *dev = crtc->base.dev; 15153 15152 struct drm_i915_private *dev_priv = to_i915(dev); ··· 15194 15191 plane = crtc->plane; 15195 15192 crtc->base.primary->state->visible = true; 15196 15193 crtc->plane = !plane; 15197 - intel_crtc_disable_noatomic(&crtc->base); 15194 + intel_crtc_disable_noatomic(&crtc->base, ctx); 15198 15195 crtc->plane = plane; 15199 15196 } 15200 15197 ··· 15204 15201 * resume. Force-enable the pipe to fix this, the update_dpms 15205 15202 * call below we restore the pipe to the right state, but leave 15206 15203 * the required bits on. */ 15207 - intel_enable_pipe_a(dev); 15204 + intel_enable_pipe_a(dev, ctx); 15208 15205 } 15209 15206 15210 15207 /* Adjust the state of the output pipe according to whether we 15211 15208 * have active connectors/encoders. */ 15212 15209 if (crtc->active && !intel_crtc_has_encoders(crtc)) 15213 - intel_crtc_disable_noatomic(&crtc->base); 15210 + intel_crtc_disable_noatomic(&crtc->base, ctx); 15214 15211 15215 15212 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { 15216 15213 /* ··· 15508 15505 * and sanitizes it to the current state 15509 15506 */ 15510 15507 static void 15511 - intel_modeset_setup_hw_state(struct drm_device *dev) 15508 + intel_modeset_setup_hw_state(struct drm_device *dev, 15509 + struct drm_modeset_acquire_ctx *ctx) 15512 15510 { 15513 15511 struct drm_i915_private *dev_priv = to_i915(dev); 15514 15512 enum pipe pipe; ··· 15529 15525 for_each_pipe(dev_priv, pipe) { 15530 15526 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 15531 15527 15532 - intel_sanitize_crtc(crtc); 15528 + intel_sanitize_crtc(crtc, ctx); 15533 15529 intel_dump_pipe_config(crtc, crtc->config, 15534 15530 "[setup_hw_state]"); 15535 15531 }
-2
drivers/gpu/drm/i915/intel_dp_aux_backlight.c
··· 119 119 struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); 120 120 struct intel_panel *panel = &connector->panel; 121 121 122 - intel_dp_aux_enable_backlight(connector); 123 - 124 122 if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) 125 123 panel->backlight.max = 0xFFFF; 126 124 else
+2 -4
drivers/gpu/drm/i915/intel_lrc.c
··· 326 326 rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; 327 327 u32 *reg_state = ce->lrc_reg_state; 328 328 329 - assert_ring_tail_valid(rq->ring, rq->tail); 330 - reg_state[CTX_RING_TAIL+1] = rq->tail; 329 + reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail); 331 330 332 331 /* True 32b PPGTT with dynamic page allocation: update PDP 333 332 * registers and point the unallocated PDPs to scratch page. ··· 2035 2036 ce->state->obj->mm.dirty = true; 2036 2037 i915_gem_object_unpin_map(ce->state->obj); 2037 2038 2038 - ce->ring->head = ce->ring->tail = 0; 2039 - intel_ring_update_space(ce->ring); 2039 + intel_ring_reset(ce->ring, 0); 2040 2040 } 2041 2041 } 2042 2042 }
+27 -14
drivers/gpu/drm/i915/intel_ringbuffer.c
··· 49 49 50 50 void intel_ring_update_space(struct intel_ring *ring) 51 51 { 52 - ring->space = __intel_ring_space(ring->head, ring->tail, ring->size); 52 + ring->space = __intel_ring_space(ring->head, ring->emit, ring->size); 53 53 } 54 54 55 55 static int ··· 774 774 775 775 i915_gem_request_submit(request); 776 776 777 - assert_ring_tail_valid(request->ring, request->tail); 778 - I915_WRITE_TAIL(request->engine, request->tail); 777 + I915_WRITE_TAIL(request->engine, 778 + intel_ring_set_tail(request->ring, request->tail)); 779 779 } 780 780 781 781 static void i9xx_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs) ··· 1316 1316 return PTR_ERR(addr); 1317 1317 } 1318 1318 1319 + void intel_ring_reset(struct intel_ring *ring, u32 tail) 1320 + { 1321 + GEM_BUG_ON(!list_empty(&ring->request_list)); 1322 + ring->tail = tail; 1323 + ring->head = tail; 1324 + ring->emit = tail; 1325 + intel_ring_update_space(ring); 1326 + } 1327 + 1319 1328 void intel_ring_unpin(struct intel_ring *ring) 1320 1329 { 1321 1330 GEM_BUG_ON(!ring->vma); 1322 1331 GEM_BUG_ON(!ring->vaddr); 1332 + 1333 + /* Discard any unused bytes beyond that submitted to hw. */ 1334 + intel_ring_reset(ring, ring->tail); 1323 1335 1324 1336 if (i915_vma_is_map_and_fenceable(ring->vma)) 1325 1337 i915_vma_unpin_iomap(ring->vma); ··· 1574 1562 struct intel_engine_cs *engine; 1575 1563 enum intel_engine_id id; 1576 1564 1565 + /* Restart from the beginning of the rings for convenience */ 1577 1566 for_each_engine(engine, dev_priv, id) 1578 - engine->buffer->head = engine->buffer->tail; 1567 + intel_ring_reset(engine->buffer, 0); 1579 1568 } 1580 1569 1581 1570 static int ring_request_alloc(struct drm_i915_gem_request *request) ··· 1629 1616 unsigned space; 1630 1617 1631 1618 /* Would completion of this request free enough space? */ 1632 - space = __intel_ring_space(target->postfix, ring->tail, 1619 + space = __intel_ring_space(target->postfix, ring->emit, 1633 1620 ring->size); 1634 1621 if (space >= bytes) 1635 1622 break; ··· 1654 1641 u32 *intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) 1655 1642 { 1656 1643 struct intel_ring *ring = req->ring; 1657 - int remain_actual = ring->size - ring->tail; 1658 - int remain_usable = ring->effective_size - ring->tail; 1644 + int remain_actual = ring->size - ring->emit; 1645 + int remain_usable = ring->effective_size - ring->emit; 1659 1646 int bytes = num_dwords * sizeof(u32); 1660 1647 int total_bytes, wait_bytes; 1661 1648 bool need_wrap = false; ··· 1691 1678 1692 1679 if (unlikely(need_wrap)) { 1693 1680 GEM_BUG_ON(remain_actual > ring->space); 1694 - GEM_BUG_ON(ring->tail + remain_actual > ring->size); 1681 + GEM_BUG_ON(ring->emit + remain_actual > ring->size); 1695 1682 1696 1683 /* Fill the tail with MI_NOOP */ 1697 - memset(ring->vaddr + ring->tail, 0, remain_actual); 1698 - ring->tail = 0; 1684 + memset(ring->vaddr + ring->emit, 0, remain_actual); 1685 + ring->emit = 0; 1699 1686 ring->space -= remain_actual; 1700 1687 } 1701 1688 1702 - GEM_BUG_ON(ring->tail > ring->size - bytes); 1703 - cs = ring->vaddr + ring->tail; 1704 - ring->tail += bytes; 1689 + GEM_BUG_ON(ring->emit > ring->size - bytes); 1690 + cs = ring->vaddr + ring->emit; 1691 + ring->emit += bytes; 1705 1692 ring->space -= bytes; 1706 1693 GEM_BUG_ON(ring->space < 0); 1707 1694 ··· 1712 1699 int intel_ring_cacheline_align(struct drm_i915_gem_request *req) 1713 1700 { 1714 1701 int num_dwords = 1715 - (req->ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); 1702 + (req->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); 1716 1703 u32 *cs; 1717 1704 1718 1705 if (num_dwords == 0)
+17 -2
drivers/gpu/drm/i915/intel_ringbuffer.h
··· 145 145 146 146 u32 head; 147 147 u32 tail; 148 + u32 emit; 148 149 149 150 int space; 150 151 int size; ··· 489 488 struct intel_ring * 490 489 intel_engine_create_ring(struct intel_engine_cs *engine, int size); 491 490 int intel_ring_pin(struct intel_ring *ring, unsigned int offset_bias); 491 + void intel_ring_reset(struct intel_ring *ring, u32 tail); 492 + void intel_ring_update_space(struct intel_ring *ring); 492 493 void intel_ring_unpin(struct intel_ring *ring); 493 494 void intel_ring_free(struct intel_ring *ring); 494 495 ··· 514 511 * reserved for the command packet (i.e. the value passed to 515 512 * intel_ring_begin()). 516 513 */ 517 - GEM_BUG_ON((req->ring->vaddr + req->ring->tail) != cs); 514 + GEM_BUG_ON((req->ring->vaddr + req->ring->emit) != cs); 518 515 } 519 516 520 517 static inline u32 ··· 543 540 GEM_BUG_ON(tail >= ring->size); 544 541 } 545 542 546 - void intel_ring_update_space(struct intel_ring *ring); 543 + static inline unsigned int 544 + intel_ring_set_tail(struct intel_ring *ring, unsigned int tail) 545 + { 546 + /* Whilst writes to the tail are strictly order, there is no 547 + * serialisation between readers and the writers. The tail may be 548 + * read by i915_gem_request_retire() just as it is being updated 549 + * by execlists, as although the breadcrumb is complete, the context 550 + * switch hasn't been seen. 551 + */ 552 + assert_ring_tail_valid(ring, tail); 553 + ring->tail = tail; 554 + return tail; 555 + } 547 556 548 557 void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno); 549 558
+7
drivers/gpu/drm/radeon/radeon_combios.c
··· 3393 3393 rdev->pdev->subsystem_vendor == 0x103c && 3394 3394 rdev->pdev->subsystem_device == 0x280a) 3395 3395 return; 3396 + /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume 3397 + * - it hangs on resume inside the dynclk 1 table. 3398 + */ 3399 + if (rdev->family == CHIP_RS400 && 3400 + rdev->pdev->subsystem_vendor == 0x1179 && 3401 + rdev->pdev->subsystem_device == 0xff31) 3402 + return; 3396 3403 3397 3404 /* DYN CLK 1 */ 3398 3405 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
+4
drivers/gpu/drm/radeon/radeon_device.c
··· 136 136 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 137 137 */ 138 138 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 139 + /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 140 + * https://bugs.freedesktop.org/show_bug.cgi?id=101491 141 + */ 142 + { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 139 143 /* macbook pro 8.2 */ 140 144 { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, 141 145 { 0, 0, 0, 0, 0 },