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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: gcc: Remove CPUSS clocks control for SC7280
The CPUSS clocks are kept always ON and at a fixed frequency of 100MHZ
from the bootloader and no longer required to be controlled from HLOS.
Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1633579571-25475-1-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Taniya Das
and committed by
Stephen Boyd
3165d1e3
30ecef23
-79
-79
drivers/clk/qcom/gcc-sc7280.c
-79
drivers/clk/qcom/gcc-sc7280.c
···
479
479
},
480
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},
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};
482
-
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
483
-
F(19200000, P_BI_TCXO, 1, 0, 0),
484
-
{ }
485
-
};
486
-
487
-
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
488
-
.cmd_rcgr = 0x4800c,
489
-
.mnd_width = 0,
490
-
.hid_width = 5,
491
-
.parent_map = gcc_parent_map_0,
492
-
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
493
-
.clkr.hw.init = &(struct clk_init_data){
494
-
.name = "gcc_cpuss_ahb_clk_src",
495
-
.parent_data = gcc_parent_data_0_ao,
496
-
.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
497
-
.ops = &clk_rcg2_ops,
498
-
},
499
-
};
500
482
501
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static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
502
484
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
···
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1239
},
1222
1240
};
1223
1241
1224
-
static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
1225
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.reg = 0x48024,
1226
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.shift = 0,
1227
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.width = 4,
1228
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "gcc_cpuss_ahb_postdiv_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&gcc_cpuss_ahb_clk_src.clkr.hw,
1232
-
},
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.num_parents = 1,
1234
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
1236
-
},
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-
};
1238
-
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static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
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.reg = 0xf050,
1241
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.shift = 0,
···
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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-
.ops = &clk_branch2_ops,
1466
-
},
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-
},
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-
};
1469
-
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/* For CPUSS functionality the AHB clock needs to be left enabled */
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static struct clk_branch gcc_cpuss_ahb_clk = {
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.halt_reg = 0x48000,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x48000,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x52000,
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.enable_mask = BIT(21),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_cpuss_ahb_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
···
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},
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};
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-
/* For CPUSS functionality the AHB clock needs to be left enabled */
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static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2559
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.halt_reg = 0x48178,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x48178,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x52000,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_sys_noc_cpuss_ahb_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
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-
},
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-
.num_parents = 1,
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.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
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-
.ops = &clk_branch2_ops,
2574
-
},
2575
-
},
2576
-
};
2577
-
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static struct clk_branch gcc_throttle_pcie_ahb_clk = {
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.halt_reg = 0x9001c,
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.halt_check = BRANCH_HALT,
···
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[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3220
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[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
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[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3222
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[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3223
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[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3224
-
[GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
3225
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[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3226
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[GCC_DDRSS_PCIE_SF_CLK] = &gcc_ddrss_pcie_sf_clk.clkr,
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[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
···
3325
3403
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3326
3404
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3327
3405
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3328
-
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3329
3406
[GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
3330
3407
[GCC_TITAN_NRT_THROTTLE_CORE_CLK] =
3331
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&gcc_titan_nrt_throttle_core_clk.clkr,