Merge branch 'phy-mediatek-reorg' · tjh.dev/kernel@31a1f87

+4 -2

MAINTAINERS

··· 14439 14439 M: SkyLake Huang <SkyLake.Huang@mediatek.com> 14440 14440 L: netdev@vger.kernel.org 14441 14441 S: Maintained 14442 - F: drivers/net/phy/mediatek-ge-soc.c 14443 - F: drivers/net/phy/mediatek-ge.c 14442 + F: drivers/net/phy/mediatek/mtk-ge-soc.c 14443 + F: drivers/net/phy/mediatek/mtk-phy-lib.c 14444 + F: drivers/net/phy/mediatek/mtk-ge.c 14445 + F: drivers/net/phy/mediatek/mtk.h 14444 14446 F: drivers/phy/mediatek/phy-mtk-xfi-tphy.c 14445 14447 14446 14448 MEDIATEK I2C CONTROLLER DRIVER

+1 -16

drivers/net/phy/Kconfig

··· 266 266 Support for the Maxlinear GPY115, GPY211, GPY212, GPY215, 267 267 GPY241, GPY245 PHYs. 268 268 269 - config MEDIATEK_GE_PHY 270 - tristate "MediaTek Gigabit Ethernet PHYs" 271 - help 272 - Supports the MediaTek Gigabit Ethernet PHYs. 273 - 274 - config MEDIATEK_GE_SOC_PHY 275 - tristate "MediaTek SoC Ethernet PHYs" 276 - depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST 277 - depends on NVMEM_MTK_EFUSE 278 - help 279 - Supports MediaTek SoC built-in Gigabit Ethernet PHYs. 280 - 281 - Include support for built-in Ethernet PHYs which are present in 282 - the MT7981 and MT7988 SoCs. These PHYs need calibration data 283 - present in the SoCs efuse and will dynamically calibrate VCM 284 - (common-mode voltage) during startup. 269 + source "drivers/net/phy/mediatek/Kconfig" 285 270 286 271 config MICREL_PHY 287 272 tristate "Micrel PHYs"

+1 -2

drivers/net/phy/Makefile

··· 74 74 obj-$(CONFIG_MARVELL_88Q2XXX_PHY) += marvell-88q2xxx.o 75 75 obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o 76 76 obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o 77 - obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o 78 - obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o 77 + obj-y += mediatek/ 79 78 obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o 80 79 obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o 81 80 obj-$(CONFIG_MICREL_PHY) += micrel.o

+29 -269

drivers/net/phy/mediatek-ge-soc.c drivers/net/phy/mediatek/mtk-ge-soc.c

··· 8 8 #include <linux/phy.h> 9 9 #include <linux/regmap.h> 10 10 11 + #include "mtk.h" 12 + 11 13 #define MTK_GPHY_ID_MT7981 0x03a29461 12 14 #define MTK_GPHY_ID_MT7988 0x03a29481 13 15 ··· 212 210 #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 213 211 214 212 /* Registers on MDIO_MMD_VEND2 */ 215 - #define MTK_PHY_LED0_ON_CTRL 0x24 216 - #define MTK_PHY_LED1_ON_CTRL 0x26 217 - #define MTK_PHY_LED_ON_MASK GENMASK(6, 0) 218 - #define MTK_PHY_LED_ON_LINK1000 BIT(0) 219 - #define MTK_PHY_LED_ON_LINK100 BIT(1) 220 - #define MTK_PHY_LED_ON_LINK10 BIT(2) 221 - #define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\ 222 - MTK_PHY_LED_ON_LINK100 |\ 223 - MTK_PHY_LED_ON_LINK1000) 224 - #define MTK_PHY_LED_ON_LINKDOWN BIT(3) 225 - #define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ 226 - #define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ 227 - #define MTK_PHY_LED_ON_FORCE_ON BIT(6) 228 - #define MTK_PHY_LED_ON_POLARITY BIT(14) 229 - #define MTK_PHY_LED_ON_ENABLE BIT(15) 230 - 231 - #define MTK_PHY_LED0_BLINK_CTRL 0x25 232 - #define MTK_PHY_LED1_BLINK_CTRL 0x27 233 - #define MTK_PHY_LED_BLINK_1000TX BIT(0) 234 - #define MTK_PHY_LED_BLINK_1000RX BIT(1) 235 - #define MTK_PHY_LED_BLINK_100TX BIT(2) 236 - #define MTK_PHY_LED_BLINK_100RX BIT(3) 237 - #define MTK_PHY_LED_BLINK_10TX BIT(4) 238 - #define MTK_PHY_LED_BLINK_10RX BIT(5) 239 - #define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\ 240 - MTK_PHY_LED_BLINK_100RX |\ 241 - MTK_PHY_LED_BLINK_1000RX) 242 - #define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\ 243 - MTK_PHY_LED_BLINK_100TX |\ 244 - MTK_PHY_LED_BLINK_1000TX) 245 - #define MTK_PHY_LED_BLINK_COLLISION BIT(6) 246 - #define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) 247 - #define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) 248 - #define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) 249 - 250 213 #define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) 251 214 252 215 #define MTK_PHY_RG_BG_RASEL 0x115 ··· 266 299 SW_M 267 300 }; 268 301 269 - #define MTK_PHY_LED_STATE_FORCE_ON 0 270 - #define MTK_PHY_LED_STATE_FORCE_BLINK 1 271 - #define MTK_PHY_LED_STATE_NETDEV 2 272 - 273 - struct mtk_socphy_priv { 274 - unsigned long led_state; 275 - }; 276 - 277 302 struct mtk_socphy_shared { 278 303 u32 boottrap; 279 304 struct mtk_socphy_priv priv[4]; 280 305 }; 281 - 282 - static int mtk_socphy_read_page(struct phy_device *phydev) 283 - { 284 - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); 285 - } 286 - 287 - static int mtk_socphy_write_page(struct phy_device *phydev, int page) 288 - { 289 - return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); 290 - } 291 306 292 307 /* One calibration cycle consists of: 293 308 * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high ··· 1121 1172 return mt798x_phy_calibration(phydev); 1122 1173 } 1123 1174 1124 - static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index, 1125 - bool on) 1126 - { 1127 - unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); 1128 - struct mtk_socphy_priv *priv = phydev->priv; 1129 - bool changed; 1130 - 1131 - if (on) 1132 - changed = !test_and_set_bit(bit_on, &priv->led_state); 1133 - else 1134 - changed = !!test_and_clear_bit(bit_on, &priv->led_state); 1135 - 1136 - changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + 1137 - (index ? 16 : 0), &priv->led_state); 1138 - if (changed) 1139 - return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1140 - MTK_PHY_LED1_ON_CTRL : 1141 - MTK_PHY_LED0_ON_CTRL, 1142 - MTK_PHY_LED_ON_MASK, 1143 - on ? MTK_PHY_LED_ON_FORCE_ON : 0); 1144 - else 1145 - return 0; 1146 - } 1147 - 1148 - static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, 1149 - bool blinking) 1150 - { 1151 - unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + 1152 - (index ? 16 : 0); 1153 - struct mtk_socphy_priv *priv = phydev->priv; 1154 - bool changed; 1155 - 1156 - if (blinking) 1157 - changed = !test_and_set_bit(bit_blink, &priv->led_state); 1158 - else 1159 - changed = !!test_and_clear_bit(bit_blink, &priv->led_state); 1160 - 1161 - changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV + 1162 - (index ? 16 : 0), &priv->led_state); 1163 - if (changed) 1164 - return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? 1165 - MTK_PHY_LED1_BLINK_CTRL : 1166 - MTK_PHY_LED0_BLINK_CTRL, 1167 - blinking ? 1168 - MTK_PHY_LED_BLINK_FORCE_BLINK : 0); 1169 - else 1170 - return 0; 1171 - } 1172 - 1173 1175 static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, 1174 1176 unsigned long *delay_on, 1175 1177 unsigned long *delay_off) 1176 1178 { 1177 1179 bool blinking = false; 1178 - int err = 0; 1180 + int err; 1179 1181 1180 - if (index > 1) 1181 - return -EINVAL; 1182 + err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking); 1183 + if (err < 0) 1184 + return err; 1182 1185 1183 - if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { 1184 - blinking = true; 1185 - *delay_on = 50; 1186 - *delay_off = 50; 1187 - } 1188 - 1189 - err = mt798x_phy_hw_led_blink_set(phydev, index, blinking); 1186 + err = mtk_phy_hw_led_blink_set(phydev, index, blinking); 1190 1187 if (err) 1191 1188 return err; 1192 1189 1193 - return mt798x_phy_hw_led_on_set(phydev, index, false); 1190 + return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, 1191 + false); 1194 1192 } 1195 1193 1196 1194 static int mt798x_phy_led_brightness_set(struct phy_device *phydev, ··· 1145 1249 { 1146 1250 int err; 1147 1251 1148 - err = mt798x_phy_hw_led_blink_set(phydev, index, false); 1252 + err = mtk_phy_hw_led_blink_set(phydev, index, false); 1149 1253 if (err) 1150 1254 return err; 1151 1255 1152 - return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF)); 1256 + return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, 1257 + (value != LED_OFF)); 1153 1258 } 1154 1259 1155 1260 static const unsigned long supported_triggers = ··· 1166 1269 static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, 1167 1270 unsigned long rules) 1168 1271 { 1169 - if (index > 1) 1170 - return -EINVAL; 1171 - 1172 - /* All combinations of the supported triggers are allowed */ 1173 - if (rules & ~supported_triggers) 1174 - return -EOPNOTSUPP; 1175 - 1176 - return 0; 1177 - }; 1272 + return mtk_phy_led_hw_is_supported(phydev, index, rules, 1273 + supported_triggers); 1274 + } 1178 1275 1179 1276 static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, 1180 1277 unsigned long *rules) 1181 1278 { 1182 - unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + 1183 - (index ? 16 : 0); 1184 - unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); 1185 - unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); 1186 - struct mtk_socphy_priv *priv = phydev->priv; 1187 - int on, blink; 1188 - 1189 - if (index > 1) 1190 - return -EINVAL; 1191 - 1192 - on = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1193 - index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); 1194 - 1195 - if (on < 0) 1196 - return -EIO; 1197 - 1198 - blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1199 - index ? MTK_PHY_LED1_BLINK_CTRL : 1200 - MTK_PHY_LED0_BLINK_CTRL); 1201 - if (blink < 0) 1202 - return -EIO; 1203 - 1204 - if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX | 1205 - MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) || 1206 - (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX))) 1207 - set_bit(bit_netdev, &priv->led_state); 1208 - else 1209 - clear_bit(bit_netdev, &priv->led_state); 1210 - 1211 - if (on & MTK_PHY_LED_ON_FORCE_ON) 1212 - set_bit(bit_on, &priv->led_state); 1213 - else 1214 - clear_bit(bit_on, &priv->led_state); 1215 - 1216 - if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) 1217 - set_bit(bit_blink, &priv->led_state); 1218 - else 1219 - clear_bit(bit_blink, &priv->led_state); 1220 - 1221 - if (!rules) 1222 - return 0; 1223 - 1224 - if (on & MTK_PHY_LED_ON_LINK) 1225 - *rules |= BIT(TRIGGER_NETDEV_LINK); 1226 - 1227 - if (on & MTK_PHY_LED_ON_LINK10) 1228 - *rules |= BIT(TRIGGER_NETDEV_LINK_10); 1229 - 1230 - if (on & MTK_PHY_LED_ON_LINK100) 1231 - *rules |= BIT(TRIGGER_NETDEV_LINK_100); 1232 - 1233 - if (on & MTK_PHY_LED_ON_LINK1000) 1234 - *rules |= BIT(TRIGGER_NETDEV_LINK_1000); 1235 - 1236 - if (on & MTK_PHY_LED_ON_FDX) 1237 - *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX); 1238 - 1239 - if (on & MTK_PHY_LED_ON_HDX) 1240 - *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX); 1241 - 1242 - if (blink & MTK_PHY_LED_BLINK_RX) 1243 - *rules |= BIT(TRIGGER_NETDEV_RX); 1244 - 1245 - if (blink & MTK_PHY_LED_BLINK_TX) 1246 - *rules |= BIT(TRIGGER_NETDEV_TX); 1247 - 1248 - return 0; 1279 + return mtk_phy_led_hw_ctrl_get(phydev, index, rules, 1280 + MTK_GPHY_LED_ON_SET, 1281 + MTK_GPHY_LED_RX_BLINK_SET, 1282 + MTK_GPHY_LED_TX_BLINK_SET); 1249 1283 }; 1250 1284 1251 1285 static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, 1252 1286 unsigned long rules) 1253 1287 { 1254 - unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); 1255 - struct mtk_socphy_priv *priv = phydev->priv; 1256 - u16 on = 0, blink = 0; 1257 - int ret; 1258 - 1259 - if (index > 1) 1260 - return -EINVAL; 1261 - 1262 - if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) 1263 - on |= MTK_PHY_LED_ON_FDX; 1264 - 1265 - if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) 1266 - on |= MTK_PHY_LED_ON_HDX; 1267 - 1268 - if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) 1269 - on |= MTK_PHY_LED_ON_LINK10; 1270 - 1271 - if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) 1272 - on |= MTK_PHY_LED_ON_LINK100; 1273 - 1274 - if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) 1275 - on |= MTK_PHY_LED_ON_LINK1000; 1276 - 1277 - if (rules & BIT(TRIGGER_NETDEV_RX)) { 1278 - blink |= (on & MTK_PHY_LED_ON_LINK) ? 1279 - (((on & MTK_PHY_LED_ON_LINK10) ? 1280 - MTK_PHY_LED_BLINK_10RX : 0) | 1281 - ((on & MTK_PHY_LED_ON_LINK100) ? 1282 - MTK_PHY_LED_BLINK_100RX : 0) | 1283 - ((on & MTK_PHY_LED_ON_LINK1000) ? 1284 - MTK_PHY_LED_BLINK_1000RX : 0)) : 1285 - MTK_PHY_LED_BLINK_RX; 1286 - } 1287 - 1288 - if (rules & BIT(TRIGGER_NETDEV_TX)) { 1289 - blink |= (on & MTK_PHY_LED_ON_LINK) ? 1290 - (((on & MTK_PHY_LED_ON_LINK10) ? 1291 - MTK_PHY_LED_BLINK_10TX : 0) | 1292 - ((on & MTK_PHY_LED_ON_LINK100) ? 1293 - MTK_PHY_LED_BLINK_100TX : 0) | 1294 - ((on & MTK_PHY_LED_ON_LINK1000) ? 1295 - MTK_PHY_LED_BLINK_1000TX : 0)) : 1296 - MTK_PHY_LED_BLINK_TX; 1297 - } 1298 - 1299 - if (blink || on) 1300 - set_bit(bit_netdev, &priv->led_state); 1301 - else 1302 - clear_bit(bit_netdev, &priv->led_state); 1303 - 1304 - ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1305 - MTK_PHY_LED1_ON_CTRL : 1306 - MTK_PHY_LED0_ON_CTRL, 1307 - MTK_PHY_LED_ON_FDX | 1308 - MTK_PHY_LED_ON_HDX | 1309 - MTK_PHY_LED_ON_LINK, 1310 - on); 1311 - 1312 - if (ret) 1313 - return ret; 1314 - 1315 - return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? 1316 - MTK_PHY_LED1_BLINK_CTRL : 1317 - MTK_PHY_LED0_BLINK_CTRL, blink); 1288 + return mtk_phy_led_hw_ctrl_set(phydev, index, rules, 1289 + MTK_GPHY_LED_ON_SET, 1290 + MTK_GPHY_LED_RX_BLINK_SET, 1291 + MTK_GPHY_LED_TX_BLINK_SET); 1318 1292 }; 1319 1293 1320 1294 static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) ··· 1260 1492 return 0; 1261 1493 } 1262 1494 1263 - static void mt798x_phy_leds_state_init(struct phy_device *phydev) 1264 - { 1265 - int i; 1266 - 1267 - for (i = 0; i < 2; ++i) 1268 - mt798x_phy_led_hw_control_get(phydev, i, NULL); 1269 - } 1270 - 1271 1495 static int mt7988_phy_probe(struct phy_device *phydev) 1272 1496 { 1273 1497 struct mtk_socphy_shared *shared; ··· 1285 1525 1286 1526 phydev->priv = priv; 1287 1527 1288 - mt798x_phy_leds_state_init(phydev); 1528 + mtk_phy_leds_state_init(phydev); 1289 1529 1290 1530 err = mt7988_phy_fix_leds_polarities(phydev); 1291 1531 if (err) ··· 1312 1552 1313 1553 phydev->priv = priv; 1314 1554 1315 - mt798x_phy_leds_state_init(phydev); 1555 + mtk_phy_leds_state_init(phydev); 1316 1556 1317 1557 return mt798x_phy_calibration(phydev); 1318 1558 } ··· 1327 1567 .probe = mt7981_phy_probe, 1328 1568 .suspend = genphy_suspend, 1329 1569 .resume = genphy_resume, 1330 - .read_page = mtk_socphy_read_page, 1331 - .write_page = mtk_socphy_write_page, 1570 + .read_page = mtk_phy_read_page, 1571 + .write_page = mtk_phy_write_page, 1332 1572 .led_blink_set = mt798x_phy_led_blink_set, 1333 1573 .led_brightness_set = mt798x_phy_led_brightness_set, 1334 1574 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, ··· 1344 1584 .probe = mt7988_phy_probe, 1345 1585 .suspend = genphy_suspend, 1346 1586 .resume = genphy_resume, 1347 - .read_page = mtk_socphy_read_page, 1348 - .write_page = mtk_socphy_write_page, 1587 + .read_page = mtk_phy_read_page, 1588 + .write_page = mtk_phy_write_page, 1349 1589 .led_blink_set = mt798x_phy_led_blink_set, 1350 1590 .led_brightness_set = mt798x_phy_led_brightness_set, 1351 1591 .led_hw_is_supported = mt798x_phy_led_hw_is_supported,

+13 -18

drivers/net/phy/mediatek-ge.c drivers/net/phy/mediatek/mtk-ge.c

··· 3 3 #include <linux/module.h> 4 4 #include <linux/phy.h> 5 5 6 + #include "mtk.h" 7 + 8 + #define MTK_GPHY_ID_MT7530 0x03a29412 9 + #define MTK_GPHY_ID_MT7531 0x03a29441 10 + 6 11 #define MTK_EXT_PAGE_ACCESS 0x1f 7 12 #define MTK_PHY_PAGE_STANDARD 0x0000 8 13 #define MTK_PHY_PAGE_EXTENDED 0x0001 ··· 15 10 #define MTK_PHY_PAGE_EXTENDED_3 0x0003 16 11 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 17 12 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 18 - 19 - static int mtk_gephy_read_page(struct phy_device *phydev) 20 - { 21 - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); 22 - } 23 - 24 - static int mtk_gephy_write_page(struct phy_device *phydev, int page) 25 - { 26 - return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); 27 - } 28 13 29 14 static void mtk_gephy_config_init(struct phy_device *phydev) 30 15 { ··· 62 67 63 68 static struct phy_driver mtk_gephy_driver[] = { 64 69 { 65 - PHY_ID_MATCH_EXACT(0x03a29412), 70 + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530), 66 71 .name = "MediaTek MT7530 PHY", 67 72 .config_init = mt7530_phy_config_init, 68 73 /* Interrupts are handled by the switch, not the PHY ··· 72 77 .handle_interrupt = genphy_handle_interrupt_no_ack, 73 78 .suspend = genphy_suspend, 74 79 .resume = genphy_resume, 75 - .read_page = mtk_gephy_read_page, 76 - .write_page = mtk_gephy_write_page, 80 + .read_page = mtk_phy_read_page, 81 + .write_page = mtk_phy_write_page, 77 82 }, 78 83 { 79 - PHY_ID_MATCH_EXACT(0x03a29441), 84 + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531), 80 85 .name = "MediaTek MT7531 PHY", 81 86 .config_init = mt7531_phy_config_init, 82 87 /* Interrupts are handled by the switch, not the PHY ··· 86 91 .handle_interrupt = genphy_handle_interrupt_no_ack, 87 92 .suspend = genphy_suspend, 88 93 .resume = genphy_resume, 89 - .read_page = mtk_gephy_read_page, 90 - .write_page = mtk_gephy_write_page, 94 + .read_page = mtk_phy_read_page, 95 + .write_page = mtk_phy_write_page, 91 96 }, 92 97 }; 93 98 94 99 module_phy_driver(mtk_gephy_driver); 95 100 96 101 static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { 97 - { PHY_ID_MATCH_EXACT(0x03a29441) }, 98 - { PHY_ID_MATCH_EXACT(0x03a29412) }, 102 + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530) }, 103 + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531) }, 99 104 { } 100 105 }; 101 106

+27

drivers/net/phy/mediatek/Kconfig

··· 1 + # SPDX-License-Identifier: GPL-2.0-only 2 + config MTK_NET_PHYLIB 3 + tristate 4 + 5 + config MEDIATEK_GE_PHY 6 + tristate "MediaTek Gigabit Ethernet PHYs" 7 + select MTK_NET_PHYLIB 8 + help 9 + Supports the MediaTek non-built-in Gigabit Ethernet PHYs. 10 + 11 + Non-built-in Gigabit Ethernet PHYs include mt7530/mt7531. 12 + You may find mt7530 inside mt7621. This driver shares some 13 + common operations with MediaTek SoC built-in Gigabit 14 + Ethernet PHYs. 15 + 16 + config MEDIATEK_GE_SOC_PHY 17 + tristate "MediaTek SoC Ethernet PHYs" 18 + depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST 19 + depends on NVMEM_MTK_EFUSE 20 + select MTK_NET_PHYLIB 21 + help 22 + Supports MediaTek SoC built-in Gigabit Ethernet PHYs. 23 + 24 + Include support for built-in Ethernet PHYs which are present in 25 + the MT7981 and MT7988 SoCs. These PHYs need calibration data 26 + present in the SoCs efuse and will dynamically calibrate VCM 27 + (common-mode voltage) during startup.

+4

drivers/net/phy/mediatek/Makefile

··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + obj-$(CONFIG_MTK_NET_PHYLIB) += mtk-phy-lib.o 3 + obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o 4 + obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mtk-ge-soc.o

+270

drivers/net/phy/mediatek/mtk-phy-lib.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + #include <linux/phy.h> 3 + #include <linux/module.h> 4 + 5 + #include <linux/netdevice.h> 6 + 7 + #include "mtk.h" 8 + 9 + int mtk_phy_read_page(struct phy_device *phydev) 10 + { 11 + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); 12 + } 13 + EXPORT_SYMBOL_GPL(mtk_phy_read_page); 14 + 15 + int mtk_phy_write_page(struct phy_device *phydev, int page) 16 + { 17 + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); 18 + } 19 + EXPORT_SYMBOL_GPL(mtk_phy_write_page); 20 + 21 + int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, 22 + unsigned long rules, 23 + unsigned long supported_triggers) 24 + { 25 + if (index > 1) 26 + return -EINVAL; 27 + 28 + /* All combinations of the supported triggers are allowed */ 29 + if (rules & ~supported_triggers) 30 + return -EOPNOTSUPP; 31 + 32 + return 0; 33 + } 34 + EXPORT_SYMBOL_GPL(mtk_phy_led_hw_is_supported); 35 + 36 + int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index, 37 + unsigned long *rules, u16 on_set, 38 + u16 rx_blink_set, u16 tx_blink_set) 39 + { 40 + unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + 41 + (index ? 16 : 0); 42 + unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); 43 + unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); 44 + struct mtk_socphy_priv *priv = phydev->priv; 45 + int on, blink; 46 + 47 + if (index > 1) 48 + return -EINVAL; 49 + 50 + on = phy_read_mmd(phydev, MDIO_MMD_VEND2, 51 + index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); 52 + 53 + if (on < 0) 54 + return -EIO; 55 + 56 + blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, 57 + index ? MTK_PHY_LED1_BLINK_CTRL : 58 + MTK_PHY_LED0_BLINK_CTRL); 59 + if (blink < 0) 60 + return -EIO; 61 + 62 + if ((on & (on_set | MTK_PHY_LED_ON_FDX | 63 + MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) || 64 + (blink & (rx_blink_set | tx_blink_set))) 65 + set_bit(bit_netdev, &priv->led_state); 66 + else 67 + clear_bit(bit_netdev, &priv->led_state); 68 + 69 + if (on & MTK_PHY_LED_ON_FORCE_ON) 70 + set_bit(bit_on, &priv->led_state); 71 + else 72 + clear_bit(bit_on, &priv->led_state); 73 + 74 + if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) 75 + set_bit(bit_blink, &priv->led_state); 76 + else 77 + clear_bit(bit_blink, &priv->led_state); 78 + 79 + if (!rules) 80 + return 0; 81 + 82 + if (on & on_set) 83 + *rules |= BIT(TRIGGER_NETDEV_LINK); 84 + 85 + if (on & MTK_PHY_LED_ON_LINK10) 86 + *rules |= BIT(TRIGGER_NETDEV_LINK_10); 87 + 88 + if (on & MTK_PHY_LED_ON_LINK100) 89 + *rules |= BIT(TRIGGER_NETDEV_LINK_100); 90 + 91 + if (on & MTK_PHY_LED_ON_LINK1000) 92 + *rules |= BIT(TRIGGER_NETDEV_LINK_1000); 93 + 94 + if (on & MTK_PHY_LED_ON_LINK2500) 95 + *rules |= BIT(TRIGGER_NETDEV_LINK_2500); 96 + 97 + if (on & MTK_PHY_LED_ON_FDX) 98 + *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX); 99 + 100 + if (on & MTK_PHY_LED_ON_HDX) 101 + *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX); 102 + 103 + if (blink & rx_blink_set) 104 + *rules |= BIT(TRIGGER_NETDEV_RX); 105 + 106 + if (blink & tx_blink_set) 107 + *rules |= BIT(TRIGGER_NETDEV_TX); 108 + 109 + return 0; 110 + } 111 + EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_get); 112 + 113 + int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index, 114 + unsigned long rules, u16 on_set, 115 + u16 rx_blink_set, u16 tx_blink_set) 116 + { 117 + unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); 118 + struct mtk_socphy_priv *priv = phydev->priv; 119 + u16 on = 0, blink = 0; 120 + int ret; 121 + 122 + if (index > 1) 123 + return -EINVAL; 124 + 125 + if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) 126 + on |= MTK_PHY_LED_ON_FDX; 127 + 128 + if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) 129 + on |= MTK_PHY_LED_ON_HDX; 130 + 131 + if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) 132 + on |= MTK_PHY_LED_ON_LINK10; 133 + 134 + if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) 135 + on |= MTK_PHY_LED_ON_LINK100; 136 + 137 + if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) 138 + on |= MTK_PHY_LED_ON_LINK1000; 139 + 140 + if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) 141 + on |= MTK_PHY_LED_ON_LINK2500; 142 + 143 + if (rules & BIT(TRIGGER_NETDEV_RX)) { 144 + if (on & on_set) { 145 + if (on & MTK_PHY_LED_ON_LINK10) 146 + blink |= MTK_PHY_LED_BLINK_10RX; 147 + if (on & MTK_PHY_LED_ON_LINK100) 148 + blink |= MTK_PHY_LED_BLINK_100RX; 149 + if (on & MTK_PHY_LED_ON_LINK1000) 150 + blink |= MTK_PHY_LED_BLINK_1000RX; 151 + if (on & MTK_PHY_LED_ON_LINK2500) 152 + blink |= MTK_PHY_LED_BLINK_2500RX; 153 + } else { 154 + blink |= rx_blink_set; 155 + } 156 + } 157 + 158 + if (rules & BIT(TRIGGER_NETDEV_TX)) { 159 + if (on & on_set) { 160 + if (on & MTK_PHY_LED_ON_LINK10) 161 + blink |= MTK_PHY_LED_BLINK_10TX; 162 + if (on & MTK_PHY_LED_ON_LINK100) 163 + blink |= MTK_PHY_LED_BLINK_100TX; 164 + if (on & MTK_PHY_LED_ON_LINK1000) 165 + blink |= MTK_PHY_LED_BLINK_1000TX; 166 + if (on & MTK_PHY_LED_ON_LINK2500) 167 + blink |= MTK_PHY_LED_BLINK_2500TX; 168 + } else { 169 + blink |= tx_blink_set; 170 + } 171 + } 172 + 173 + if (blink || on) 174 + set_bit(bit_netdev, &priv->led_state); 175 + else 176 + clear_bit(bit_netdev, &priv->led_state); 177 + 178 + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 179 + MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, 180 + MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX | on_set, 181 + on); 182 + 183 + if (ret) 184 + return ret; 185 + 186 + return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? 187 + MTK_PHY_LED1_BLINK_CTRL : 188 + MTK_PHY_LED0_BLINK_CTRL, blink); 189 + } 190 + EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_set); 191 + 192 + int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on, 193 + unsigned long *delay_off, bool *blinking) 194 + { 195 + if (index > 1) 196 + return -EINVAL; 197 + 198 + if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { 199 + *blinking = true; 200 + *delay_on = 50; 201 + *delay_off = 50; 202 + } 203 + 204 + return 0; 205 + } 206 + EXPORT_SYMBOL_GPL(mtk_phy_led_num_dly_cfg); 207 + 208 + int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index, 209 + u16 led_on_mask, bool on) 210 + { 211 + unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); 212 + struct mtk_socphy_priv *priv = phydev->priv; 213 + bool changed; 214 + 215 + if (on) 216 + changed = !test_and_set_bit(bit_on, &priv->led_state); 217 + else 218 + changed = !!test_and_clear_bit(bit_on, &priv->led_state); 219 + 220 + changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + 221 + (index ? 16 : 0), &priv->led_state); 222 + if (changed) 223 + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 224 + MTK_PHY_LED1_ON_CTRL : 225 + MTK_PHY_LED0_ON_CTRL, 226 + led_on_mask, 227 + on ? MTK_PHY_LED_ON_FORCE_ON : 0); 228 + else 229 + return 0; 230 + } 231 + EXPORT_SYMBOL_GPL(mtk_phy_hw_led_on_set); 232 + 233 + int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, bool blinking) 234 + { 235 + unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + 236 + (index ? 16 : 0); 237 + struct mtk_socphy_priv *priv = phydev->priv; 238 + bool changed; 239 + 240 + if (blinking) 241 + changed = !test_and_set_bit(bit_blink, &priv->led_state); 242 + else 243 + changed = !!test_and_clear_bit(bit_blink, &priv->led_state); 244 + 245 + changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV + 246 + (index ? 16 : 0), &priv->led_state); 247 + if (changed) 248 + return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? 249 + MTK_PHY_LED1_BLINK_CTRL : 250 + MTK_PHY_LED0_BLINK_CTRL, 251 + blinking ? 252 + MTK_PHY_LED_BLINK_FORCE_BLINK : 0); 253 + else 254 + return 0; 255 + } 256 + EXPORT_SYMBOL_GPL(mtk_phy_hw_led_blink_set); 257 + 258 + void mtk_phy_leds_state_init(struct phy_device *phydev) 259 + { 260 + int i; 261 + 262 + for (i = 0; i < 2; ++i) 263 + phydev->drv->led_hw_control_get(phydev, i, NULL); 264 + } 265 + EXPORT_SYMBOL_GPL(mtk_phy_leds_state_init); 266 + 267 + MODULE_DESCRIPTION("MediaTek Ethernet PHY driver common"); 268 + MODULE_AUTHOR("Sky Huang <SkyLake.Huang@mediatek.com>"); 269 + MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); 270 + MODULE_LICENSE("GPL");

+89

drivers/net/phy/mediatek/mtk.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 2 + * 3 + * Common definition for Mediatek Ethernet PHYs 4 + * Author: SkyLake Huang <SkyLake.Huang@mediatek.com> 5 + * Copyright (c) 2024 MediaTek Inc. 6 + */ 7 + 8 + #ifndef _MTK_EPHY_H_ 9 + #define _MTK_EPHY_H_ 10 + 11 + #define MTK_EXT_PAGE_ACCESS 0x1f 12 + 13 + /* Registers on MDIO_MMD_VEND2 */ 14 + #define MTK_PHY_LED0_ON_CTRL 0x24 15 + #define MTK_PHY_LED1_ON_CTRL 0x26 16 + #define MTK_GPHY_LED_ON_MASK GENMASK(6, 0) 17 + #define MTK_2P5GPHY_LED_ON_MASK GENMASK(7, 0) 18 + #define MTK_PHY_LED_ON_LINK1000 BIT(0) 19 + #define MTK_PHY_LED_ON_LINK100 BIT(1) 20 + #define MTK_PHY_LED_ON_LINK10 BIT(2) 21 + #define MTK_PHY_LED_ON_LINKDOWN BIT(3) 22 + #define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ 23 + #define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ 24 + #define MTK_PHY_LED_ON_FORCE_ON BIT(6) 25 + #define MTK_PHY_LED_ON_LINK2500 BIT(7) 26 + #define MTK_PHY_LED_ON_POLARITY BIT(14) 27 + #define MTK_PHY_LED_ON_ENABLE BIT(15) 28 + 29 + #define MTK_PHY_LED0_BLINK_CTRL 0x25 30 + #define MTK_PHY_LED1_BLINK_CTRL 0x27 31 + #define MTK_PHY_LED_BLINK_1000TX BIT(0) 32 + #define MTK_PHY_LED_BLINK_1000RX BIT(1) 33 + #define MTK_PHY_LED_BLINK_100TX BIT(2) 34 + #define MTK_PHY_LED_BLINK_100RX BIT(3) 35 + #define MTK_PHY_LED_BLINK_10TX BIT(4) 36 + #define MTK_PHY_LED_BLINK_10RX BIT(5) 37 + #define MTK_PHY_LED_BLINK_COLLISION BIT(6) 38 + #define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) 39 + #define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) 40 + #define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) 41 + #define MTK_PHY_LED_BLINK_2500TX BIT(10) 42 + #define MTK_PHY_LED_BLINK_2500RX BIT(11) 43 + 44 + #define MTK_GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK1000 | \ 45 + MTK_PHY_LED_ON_LINK100 | \ 46 + MTK_PHY_LED_ON_LINK10) 47 + #define MTK_GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \ 48 + MTK_PHY_LED_BLINK_100RX | \ 49 + MTK_PHY_LED_BLINK_10RX) 50 + #define MTK_GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \ 51 + MTK_PHY_LED_BLINK_100RX | \ 52 + MTK_PHY_LED_BLINK_10RX) 53 + 54 + #define MTK_2P5GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK2500 | \ 55 + MTK_GPHY_LED_ON_SET) 56 + #define MTK_2P5GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \ 57 + MTK_GPHY_LED_RX_BLINK_SET) 58 + #define MTK_2P5GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \ 59 + MTK_GPHY_LED_TX_BLINK_SET) 60 + 61 + #define MTK_PHY_LED_STATE_FORCE_ON 0 62 + #define MTK_PHY_LED_STATE_FORCE_BLINK 1 63 + #define MTK_PHY_LED_STATE_NETDEV 2 64 + 65 + struct mtk_socphy_priv { 66 + unsigned long led_state; 67 + }; 68 + 69 + int mtk_phy_read_page(struct phy_device *phydev); 70 + int mtk_phy_write_page(struct phy_device *phydev, int page); 71 + 72 + int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, 73 + unsigned long rules, 74 + unsigned long supported_triggers); 75 + int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index, 76 + unsigned long rules, u16 on_set, 77 + u16 rx_blink_set, u16 tx_blink_set); 78 + int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index, 79 + unsigned long *rules, u16 on_set, 80 + u16 rx_blink_set, u16 tx_blink_set); 81 + int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on, 82 + unsigned long *delay_off, bool *blinking); 83 + int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index, 84 + u16 led_on_mask, bool on); 85 + int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, 86 + bool blinking); 87 + void mtk_phy_leds_state_init(struct phy_device *phydev); 88 + 89 + #endif /* _MTK_EPHY_H_ */

Configure Feed

Configure Feed