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drm/msm/dpu: add missing ubwc_swizzle setting to catalog

Use the values from the vendor DTs to set ubwc_swizzle in the catalog.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/519662/
Link: https://lore.kernel.org/r/20230123062415.3027743-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

+5
+5
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
··· 582 582 .base = 0x0, .len = 0x494, 583 583 .features = 0, 584 584 .highest_bank_bit = 0x1, 585 + .ubwc_swizzle = 0x7, 585 586 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 586 587 .reg_off = 0x2ac, .bit_off = 0}, 587 588 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { ··· 596 595 .base = 0x0, .len = 0x494, 597 596 .features = 0, 598 597 .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 598 + .ubwc_swizzle = 0x6, 599 599 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 600 600 .reg_off = 0x2AC, .bit_off = 0}, 601 601 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { ··· 653 651 .base = 0x0, .len = 0x494, 654 652 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 655 653 .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 654 + .ubwc_swizzle = 0x6, 656 655 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 657 656 .reg_off = 0x2AC, .bit_off = 0}, 658 657 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { ··· 680 677 .name = "top_0", .id = MDP_TOP, 681 678 .base = 0x0, .len = 0x2014, 682 679 .highest_bank_bit = 0x1, 680 + .ubwc_swizzle = 0x6, 683 681 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 684 682 .reg_off = 0x2AC, .bit_off = 0}, 685 683 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { ··· 717 713 .base = 0, .len = 0x494, 718 714 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 719 715 .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 716 + .ubwc_swizzle = 0x6, 720 717 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 721 718 .reg_off = 0x4330, .bit_off = 0}, 722 719 .clk_ctrls[DPU_CLK_CTRL_VIG1] = {