Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'renesas-dts-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.17 (take two)
- Add support for the Renesas Gray Hawk Single board with R-Car
V4M-7 (R8A779H2),
- Add eMMC and microSD expansion board support for the RZ/V2H and
RZ/V2N EVK development boards,
- Add GPIO keys and Ethernet support for the RZ/G3E SoM and SMARC
Carrier-II EVK development board,
- Add QSPI FLASH support for the RZ/V2H and RZ/V2N SoCs and their EVK
development boards,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable serial NOR FLASH
arm64: dts: renesas: r9a09g057: Add XSPI node
arm64: dts: renesas: r9a09g056: Add XSPI node
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Fix pinctrl node name for GBETH1
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Fix pinctrl node name for GBETH1
arm64: dts: renesas: r8a779g3-sparrow-hawk-fan-pwm: Add missing install target
arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys
arm64: dts: renesas: Add CN15 eMMC and SD overlays for RZ/V2H and RZ/V2N EVKs
arm64: dts: renesas: r8a779h2: Add Gray Hawk Single support
arm64: dts: renesas: Add Renesas R8A779H2 SoC support
arm64: dts: renesas: Factor out Gray Hawk Single board support
dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
Link: https://lore.kernel.org/r/cover.1752090401.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+1383
-856
+15
arch/arm64/boot/dts/renesas/Makefile
+15
arch/arm64/boot/dts/renesas/Makefile
···
96
96
97
97
DTC_FLAGS_r8a779g3-sparrow-hawk += -Wno-spi_bus_bridge
98
98
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk.dtb
99
+
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtbo
99
100
r8a779g3-sparrow-hawk-fan-pwm-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-pwm.dtbo
100
101
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtb
101
102
···
105
104
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single-ard-audio-da7212.dtb
106
105
107
106
dtb-$(CONFIG_ARCH_R8A779H0) += r8a779h0-gray-hawk-single.dtb
107
+
108
+
dtb-$(CONFIG_ARCH_R8A779H0) += r8a779h2-gray-hawk-single.dtb
108
109
109
110
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb
110
111
r8a779m1-salvator-xs-panel-aa104xd12-dtbs := r8a779m1-salvator-xs.dtb salvator-panel-aa104xd12.dtbo
···
164
161
dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-cru-csi-ov5645.dtb
165
162
166
163
dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk.dtb
164
+
dtb-$(CONFIG_ARCH_R9A09G056) += rzv2-evk-cn15-emmc.dtbo
165
+
r9a09g056n48-rzv2n-evk-cn15-emmc-dtbs := r9a09g056n48-rzv2n-evk.dtb rzv2-evk-cn15-emmc.dtbo
166
+
dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk-cn15-emmc.dtb
167
+
dtb-$(CONFIG_ARCH_R9A09G056) += rzv2-evk-cn15-sd.dtbo
168
+
r9a09g056n48-rzv2n-evk-cn15-sd-dtbs := r9a09g056n48-rzv2n-evk.dtb rzv2-evk-cn15-sd.dtbo
169
+
dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk-cn15-sd.dtb
167
170
168
171
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb
172
+
dtb-$(CONFIG_ARCH_R9A09G057) += rzv2-evk-cn15-emmc.dtbo
173
+
r9a09g057h44-rzv2h-evk-cn15-emmc-dtbs := r9a09g057h44-rzv2h-evk.dtb rzv2-evk-cn15-emmc.dtbo
174
+
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk-cn15-emmc.dtb
175
+
dtb-$(CONFIG_ARCH_R9A09G057) += rzv2-evk-cn15-sd.dtbo
176
+
r9a09g057h44-rzv2h-evk-cn15-sd-dtbs := r9a09g057h44-rzv2h-evk.dtb rzv2-evk-cn15-sd.dtbo
177
+
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk-cn15-sd.dtb
169
178
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb
170
179
171
180
dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
+866
arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi
+866
arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Source for the Gray Hawk Single board
4
+
*
5
+
* Copyright (C) 2023 Renesas Electronics Corp.
6
+
* Copyright (C) 2024-2025 Glider bv
7
+
*/
8
+
/*
9
+
* [How to use Sound]
10
+
*
11
+
* Because R-Car V4M has only 1 SSI, it cannot handle both Playback/Capture
12
+
* at the same time. You need to switch the direction which is controlled
13
+
* by the GP0_01 pin via amixer.
14
+
*
15
+
* Playback (CN9500)
16
+
* > amixer set "MUX" "Playback" // for GP0_01
17
+
* > amixer set "DAC 1" 85%
18
+
* > aplay xxx.wav
19
+
*
20
+
* Capture (CN9501)
21
+
* > amixer set "MUX" "Capture" // for GP0_01
22
+
* > amixer set "Mic 1" 80%
23
+
* > amixer set "ADC 1" on
24
+
* > amixer set 'ADC 1' 80%
25
+
* > arecord xxx hoge.wav
26
+
*/
27
+
28
+
#include <dt-bindings/gpio/gpio.h>
29
+
#include <dt-bindings/input/input.h>
30
+
#include <dt-bindings/leds/common.h>
31
+
#include <dt-bindings/media/video-interfaces.h>
32
+
33
+
/ {
34
+
model = "Renesas Gray Hawk Single board";
35
+
compatible = "renesas,gray-hawk-single";
36
+
37
+
aliases {
38
+
i2c0 = &i2c0;
39
+
i2c1 = &i2c1;
40
+
i2c2 = &i2c2;
41
+
i2c3 = &i2c3;
42
+
serial0 = &hscif0;
43
+
serial1 = &hscif2;
44
+
ethernet0 = &avb0;
45
+
ethernet1 = &avb1;
46
+
ethernet2 = &avb2;
47
+
};
48
+
49
+
can_transceiver0: can-phy0 {
50
+
compatible = "nxp,tjr1443";
51
+
#phy-cells = <0>;
52
+
enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
53
+
max-bitrate = <5000000>;
54
+
};
55
+
56
+
chosen {
57
+
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
58
+
stdout-path = "serial0:921600n8";
59
+
};
60
+
61
+
sn65dsi86_refclk: clk-x6 {
62
+
compatible = "fixed-clock";
63
+
#clock-cells = <0>;
64
+
clock-frequency = <38400000>;
65
+
};
66
+
67
+
keys {
68
+
compatible = "gpio-keys";
69
+
70
+
pinctrl-0 = <&keys_pins>;
71
+
pinctrl-names = "default";
72
+
73
+
key-1 {
74
+
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
75
+
linux,code = <KEY_1>;
76
+
label = "SW47";
77
+
wakeup-source;
78
+
debounce-interval = <20>;
79
+
};
80
+
81
+
key-2 {
82
+
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
83
+
linux,code = <KEY_2>;
84
+
label = "SW48";
85
+
wakeup-source;
86
+
debounce-interval = <20>;
87
+
};
88
+
89
+
key-3 {
90
+
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
91
+
linux,code = <KEY_3>;
92
+
label = "SW49";
93
+
wakeup-source;
94
+
debounce-interval = <20>;
95
+
};
96
+
};
97
+
98
+
leds {
99
+
compatible = "gpio-leds";
100
+
101
+
led-1 {
102
+
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
103
+
color = <LED_COLOR_ID_GREEN>;
104
+
function = LED_FUNCTION_INDICATOR;
105
+
function-enumerator = <1>;
106
+
};
107
+
108
+
led-2 {
109
+
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
110
+
color = <LED_COLOR_ID_GREEN>;
111
+
function = LED_FUNCTION_INDICATOR;
112
+
function-enumerator = <2>;
113
+
};
114
+
115
+
led-3 {
116
+
gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
117
+
color = <LED_COLOR_ID_GREEN>;
118
+
function = LED_FUNCTION_INDICATOR;
119
+
function-enumerator = <3>;
120
+
};
121
+
};
122
+
123
+
memory@48000000 {
124
+
device_type = "memory";
125
+
/* first 128MB is reserved for secure area. */
126
+
reg = <0x0 0x48000000 0x0 0x78000000>;
127
+
};
128
+
129
+
memory@480000000 {
130
+
device_type = "memory";
131
+
reg = <0x4 0x80000000 0x1 0x80000000>;
132
+
};
133
+
134
+
pcie_clk: clk-9fgv0841-pci {
135
+
compatible = "fixed-clock";
136
+
clock-frequency = <100000000>;
137
+
#clock-cells = <0>;
138
+
};
139
+
140
+
mini-dp-con {
141
+
compatible = "dp-connector";
142
+
label = "CN5";
143
+
type = "mini";
144
+
145
+
port {
146
+
mini_dp_con_in: endpoint {
147
+
remote-endpoint = <&sn65dsi86_out0>;
148
+
};
149
+
};
150
+
};
151
+
152
+
reg_1p2v: regulator-1p2v {
153
+
compatible = "regulator-fixed";
154
+
regulator-name = "fixed-1.2V";
155
+
regulator-min-microvolt = <1200000>;
156
+
regulator-max-microvolt = <1200000>;
157
+
regulator-boot-on;
158
+
regulator-always-on;
159
+
};
160
+
161
+
reg_1p8v: regulator-1p8v {
162
+
compatible = "regulator-fixed";
163
+
regulator-name = "fixed-1.8V";
164
+
regulator-min-microvolt = <1800000>;
165
+
regulator-max-microvolt = <1800000>;
166
+
regulator-boot-on;
167
+
regulator-always-on;
168
+
};
169
+
170
+
reg_3p3v: regulator-3p3v {
171
+
compatible = "regulator-fixed";
172
+
regulator-name = "fixed-3.3V";
173
+
regulator-min-microvolt = <3300000>;
174
+
regulator-max-microvolt = <3300000>;
175
+
regulator-boot-on;
176
+
regulator-always-on;
177
+
};
178
+
179
+
sound_mux: sound-mux {
180
+
compatible = "simple-audio-mux";
181
+
mux-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
182
+
state-labels = "Playback", "Capture";
183
+
};
184
+
185
+
sound_card: sound {
186
+
compatible = "audio-graph-card2";
187
+
label = "rcar-sound";
188
+
aux-devs = <&sound_mux>; // for GP0_01
189
+
190
+
links = <&rsnd_port>; // AK4619 Audio Codec
191
+
};
192
+
};
193
+
194
+
&audio_clkin {
195
+
clock-frequency = <24576000>;
196
+
};
197
+
198
+
&avb0 {
199
+
pinctrl-0 = <&avb0_pins>;
200
+
pinctrl-names = "default";
201
+
phy-handle = <&avb0_phy>;
202
+
tx-internal-delay-ps = <2000>;
203
+
status = "okay";
204
+
205
+
mdio {
206
+
#address-cells = <1>;
207
+
#size-cells = <0>;
208
+
209
+
avb0_phy: ethernet-phy@0 {
210
+
compatible = "ethernet-phy-id0022.1622",
211
+
"ethernet-phy-ieee802.3-c22";
212
+
rxc-skew-ps = <1500>;
213
+
reg = <0>;
214
+
interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>;
215
+
reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
216
+
};
217
+
};
218
+
};
219
+
220
+
&avb1 {
221
+
pinctrl-0 = <&avb1_pins>;
222
+
pinctrl-names = "default";
223
+
phy-handle = <&avb1_phy>;
224
+
status = "okay";
225
+
226
+
mdio {
227
+
#address-cells = <1>;
228
+
#size-cells = <0>;
229
+
230
+
reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>;
231
+
reset-post-delay-us = <4000>;
232
+
233
+
avb1_phy: ethernet-phy@0 {
234
+
compatible = "ethernet-phy-ieee802.3-c45";
235
+
reg = <0>;
236
+
interrupts-extended = <&gpio6 3 IRQ_TYPE_LEVEL_LOW>;
237
+
};
238
+
};
239
+
};
240
+
241
+
&avb2 {
242
+
pinctrl-0 = <&avb2_pins>;
243
+
pinctrl-names = "default";
244
+
phy-handle = <&avb2_phy>;
245
+
status = "okay";
246
+
247
+
mdio {
248
+
#address-cells = <1>;
249
+
#size-cells = <0>;
250
+
251
+
reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
252
+
reset-post-delay-us = <4000>;
253
+
254
+
avb2_phy: ethernet-phy@0 {
255
+
compatible = "ethernet-phy-ieee802.3-c45";
256
+
reg = <0>;
257
+
interrupts-extended = <&gpio5 4 IRQ_TYPE_LEVEL_LOW>;
258
+
};
259
+
};
260
+
};
261
+
262
+
&can_clk {
263
+
clock-frequency = <40000000>;
264
+
};
265
+
266
+
&canfd {
267
+
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
268
+
pinctrl-names = "default";
269
+
status = "okay";
270
+
271
+
channel0 {
272
+
status = "okay";
273
+
phys = <&can_transceiver0>;
274
+
};
275
+
276
+
channel1 {
277
+
status = "okay";
278
+
};
279
+
};
280
+
281
+
&csi40 {
282
+
status = "okay";
283
+
284
+
ports {
285
+
#address-cells = <1>;
286
+
#size-cells = <0>;
287
+
288
+
port@0 {
289
+
reg = <0>;
290
+
291
+
csi40_in: endpoint {
292
+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
293
+
clock-lanes = <0>;
294
+
data-lanes = <1 2 3 4>;
295
+
remote-endpoint = <&max96724_out0>;
296
+
};
297
+
};
298
+
};
299
+
};
300
+
301
+
&csi41 {
302
+
status = "okay";
303
+
304
+
ports {
305
+
#address-cells = <1>;
306
+
#size-cells = <0>;
307
+
308
+
port@0 {
309
+
reg = <0>;
310
+
311
+
csi41_in: endpoint {
312
+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
313
+
clock-lanes = <0>;
314
+
data-lanes = <1 2 3 4>;
315
+
remote-endpoint = <&max96724_out1>;
316
+
};
317
+
};
318
+
};
319
+
};
320
+
321
+
&dsi0 {
322
+
status = "okay";
323
+
324
+
ports {
325
+
port@1 {
326
+
reg = <1>;
327
+
328
+
dsi0_out: endpoint {
329
+
remote-endpoint = <&sn65dsi86_in0>;
330
+
data-lanes = <1 2 3 4>;
331
+
};
332
+
};
333
+
};
334
+
};
335
+
336
+
&du {
337
+
status = "okay";
338
+
};
339
+
340
+
&extal_clk {
341
+
clock-frequency = <16666666>;
342
+
};
343
+
344
+
&extalr_clk {
345
+
clock-frequency = <32768>;
346
+
};
347
+
348
+
&gpio1 {
349
+
audio-power-hog {
350
+
gpio-hog;
351
+
gpios = <8 GPIO_ACTIVE_HIGH>;
352
+
output-high;
353
+
line-name = "Audio-Power";
354
+
};
355
+
};
356
+
357
+
&hscif0 {
358
+
pinctrl-0 = <&hscif0_pins>;
359
+
pinctrl-names = "default";
360
+
bootph-all;
361
+
362
+
uart-has-rtscts;
363
+
status = "okay";
364
+
};
365
+
366
+
&hscif2 {
367
+
pinctrl-0 = <&hscif2_pins>;
368
+
pinctrl-names = "default";
369
+
370
+
uart-has-rtscts;
371
+
status = "okay";
372
+
};
373
+
374
+
&i2c0 {
375
+
pinctrl-0 = <&i2c0_pins>;
376
+
pinctrl-names = "default";
377
+
378
+
status = "okay";
379
+
clock-frequency = <400000>;
380
+
381
+
io_expander_a: gpio@20 {
382
+
compatible = "onnn,pca9654";
383
+
reg = <0x20>;
384
+
interrupts-extended = <&gpio0 0 IRQ_TYPE_LEVEL_LOW>;
385
+
gpio-controller;
386
+
#gpio-cells = <2>;
387
+
interrupt-controller;
388
+
#interrupt-cells = <2>;
389
+
};
390
+
391
+
io_expander_b: gpio@21 {
392
+
compatible = "onnn,pca9654";
393
+
reg = <0x21>;
394
+
gpio-controller;
395
+
#gpio-cells = <2>;
396
+
};
397
+
398
+
io_expander_c: gpio@22 {
399
+
compatible = "onnn,pca9654";
400
+
reg = <0x22>;
401
+
gpio-controller;
402
+
#gpio-cells = <2>;
403
+
};
404
+
405
+
eeprom@50 {
406
+
compatible = "rohm,br24g01", "atmel,24c01";
407
+
label = "cpu-board";
408
+
reg = <0x50>;
409
+
pagesize = <8>;
410
+
};
411
+
412
+
eeprom@51 {
413
+
compatible = "rohm,br24g01", "atmel,24c01";
414
+
label = "breakout-board";
415
+
reg = <0x51>;
416
+
pagesize = <8>;
417
+
};
418
+
419
+
eeprom@52 {
420
+
compatible = "rohm,br24g01", "atmel,24c01";
421
+
label = "csi-dsi-sub-board-id";
422
+
reg = <0x52>;
423
+
pagesize = <8>;
424
+
};
425
+
426
+
eeprom@53 {
427
+
compatible = "rohm,br24g01", "atmel,24c01";
428
+
label = "ethernet-sub-board-id";
429
+
reg = <0x53>;
430
+
pagesize = <8>;
431
+
};
432
+
};
433
+
434
+
&i2c1 {
435
+
pinctrl-0 = <&i2c1_pins>;
436
+
pinctrl-names = "default";
437
+
438
+
status = "okay";
439
+
clock-frequency = <400000>;
440
+
441
+
bridge@2c {
442
+
pinctrl-0 = <&irq0_pins>;
443
+
pinctrl-names = "default";
444
+
445
+
compatible = "ti,sn65dsi86";
446
+
reg = <0x2c>;
447
+
448
+
clocks = <&sn65dsi86_refclk>;
449
+
clock-names = "refclk";
450
+
451
+
interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>;
452
+
453
+
enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
454
+
455
+
vccio-supply = <®_1p8v>;
456
+
vpll-supply = <®_1p8v>;
457
+
vcca-supply = <®_1p2v>;
458
+
vcc-supply = <®_1p2v>;
459
+
460
+
ports {
461
+
#address-cells = <1>;
462
+
#size-cells = <0>;
463
+
464
+
port@0 {
465
+
reg = <0>;
466
+
467
+
sn65dsi86_in0: endpoint {
468
+
remote-endpoint = <&dsi0_out>;
469
+
};
470
+
};
471
+
472
+
port@1 {
473
+
reg = <1>;
474
+
475
+
sn65dsi86_out0: endpoint {
476
+
remote-endpoint = <&mini_dp_con_in>;
477
+
};
478
+
};
479
+
};
480
+
};
481
+
482
+
gmsl0: gmsl-deserializer@4e {
483
+
compatible = "maxim,max96724";
484
+
reg = <0x4e>;
485
+
enable-gpios = <&io_expander_b 0 GPIO_ACTIVE_HIGH>;
486
+
487
+
ports {
488
+
#address-cells = <1>;
489
+
#size-cells = <0>;
490
+
491
+
port@4 {
492
+
reg = <4>;
493
+
max96724_out0: endpoint {
494
+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
495
+
clock-lanes = <0>;
496
+
data-lanes = <1 2 3 4>;
497
+
remote-endpoint = <&csi40_in>;
498
+
};
499
+
};
500
+
};
501
+
};
502
+
503
+
gmsl1: gmsl-deserializer@4f {
504
+
compatible = "maxim,max96724";
505
+
reg = <0x4f>;
506
+
enable-gpios = <&io_expander_c 0 GPIO_ACTIVE_HIGH>;
507
+
508
+
ports {
509
+
#address-cells = <1>;
510
+
#size-cells = <0>;
511
+
512
+
port@4 {
513
+
reg = <4>;
514
+
max96724_out1: endpoint {
515
+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
516
+
clock-lanes = <0>;
517
+
data-lanes = <1 2 3 4>;
518
+
remote-endpoint = <&csi41_in>;
519
+
};
520
+
};
521
+
};
522
+
};
523
+
};
524
+
525
+
&i2c3 {
526
+
pinctrl-0 = <&i2c3_pins>;
527
+
pinctrl-names = "default";
528
+
529
+
status = "okay";
530
+
clock-frequency = <400000>;
531
+
532
+
codec@10 {
533
+
compatible = "asahi-kasei,ak4619";
534
+
reg = <0x10>;
535
+
536
+
clocks = <&rcar_sound>;
537
+
clock-names = "mclk";
538
+
539
+
#sound-dai-cells = <0>;
540
+
port {
541
+
ak4619_endpoint: endpoint {
542
+
remote-endpoint = <&rsnd_endpoint>;
543
+
};
544
+
};
545
+
};
546
+
};
547
+
548
+
&isp0 {
549
+
status = "okay";
550
+
};
551
+
552
+
&isp1 {
553
+
status = "okay";
554
+
};
555
+
556
+
&mmc0 {
557
+
pinctrl-0 = <&mmc_pins>;
558
+
pinctrl-1 = <&mmc_pins>;
559
+
pinctrl-names = "default", "state_uhs";
560
+
561
+
vmmc-supply = <®_3p3v>;
562
+
vqmmc-supply = <®_1p8v>;
563
+
mmc-hs200-1_8v;
564
+
mmc-hs400-1_8v;
565
+
bus-width = <8>;
566
+
no-sd;
567
+
no-sdio;
568
+
non-removable;
569
+
full-pwr-cycle-in-suspend;
570
+
status = "okay";
571
+
};
572
+
573
+
&pcie0_clkref {
574
+
compatible = "gpio-gate-clock";
575
+
clocks = <&pcie_clk>;
576
+
enable-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
577
+
/delete-property/ clock-frequency;
578
+
};
579
+
580
+
&pciec0 {
581
+
reset-gpios = <&io_expander_a 0 GPIO_ACTIVE_LOW>;
582
+
status = "okay";
583
+
};
584
+
585
+
&pfc {
586
+
pinctrl-0 = <&scif_clk_pins>, <&scif_clk2_pins>;
587
+
pinctrl-names = "default";
588
+
589
+
avb0_pins: avb0 {
590
+
mux {
591
+
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
592
+
"avb0_txcrefclk";
593
+
function = "avb0";
594
+
};
595
+
596
+
pins_mdio {
597
+
groups = "avb0_mdio";
598
+
drive-strength = <21>;
599
+
};
600
+
601
+
pins_mii {
602
+
groups = "avb0_rgmii";
603
+
drive-strength = <21>;
604
+
};
605
+
};
606
+
607
+
avb1_pins: avb1 {
608
+
mux {
609
+
groups = "avb1_link", "avb1_mdio", "avb1_rgmii",
610
+
"avb1_txcrefclk";
611
+
function = "avb1";
612
+
};
613
+
614
+
link {
615
+
groups = "avb1_link";
616
+
bias-disable;
617
+
};
618
+
619
+
mdio {
620
+
groups = "avb1_mdio";
621
+
drive-strength = <24>;
622
+
bias-disable;
623
+
};
624
+
625
+
rgmii {
626
+
groups = "avb1_rgmii";
627
+
drive-strength = <24>;
628
+
bias-disable;
629
+
};
630
+
};
631
+
632
+
avb2_pins: avb2 {
633
+
mux {
634
+
groups = "avb2_link", "avb2_mdio", "avb2_rgmii",
635
+
"avb2_txcrefclk";
636
+
function = "avb2";
637
+
};
638
+
639
+
link {
640
+
groups = "avb2_link";
641
+
bias-disable;
642
+
};
643
+
644
+
mdio {
645
+
groups = "avb2_mdio";
646
+
drive-strength = <24>;
647
+
bias-disable;
648
+
};
649
+
650
+
rgmii {
651
+
groups = "avb2_rgmii";
652
+
drive-strength = <24>;
653
+
bias-disable;
654
+
};
655
+
};
656
+
657
+
can_clk_pins: can-clk {
658
+
groups = "can_clk";
659
+
function = "can_clk";
660
+
};
661
+
662
+
canfd0_pins: canfd0 {
663
+
groups = "canfd0_data";
664
+
function = "canfd0";
665
+
};
666
+
667
+
canfd1_pins: canfd1 {
668
+
groups = "canfd1_data";
669
+
function = "canfd1";
670
+
};
671
+
672
+
hscif0_pins: hscif0 {
673
+
groups = "hscif0_data", "hscif0_ctrl";
674
+
function = "hscif0";
675
+
};
676
+
677
+
hscif2_pins: hscif2 {
678
+
groups = "hscif2_data", "hscif2_ctrl";
679
+
function = "hscif2";
680
+
};
681
+
682
+
i2c0_pins: i2c0 {
683
+
groups = "i2c0";
684
+
function = "i2c0";
685
+
};
686
+
687
+
i2c1_pins: i2c1 {
688
+
groups = "i2c1";
689
+
function = "i2c1";
690
+
};
691
+
692
+
i2c3_pins: i2c3 {
693
+
groups = "i2c3";
694
+
function = "i2c3";
695
+
};
696
+
697
+
irq0_pins: irq0_pins {
698
+
groups = "intc_ex_irq0_a";
699
+
function = "intc_ex";
700
+
};
701
+
702
+
keys_pins: keys {
703
+
pins = "GP_5_0", "GP_5_1", "GP_5_2";
704
+
bias-pull-up;
705
+
};
706
+
707
+
mmc_pins: mmc {
708
+
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
709
+
function = "mmc";
710
+
power-source = <1800>;
711
+
};
712
+
713
+
qspi0_pins: qspi0 {
714
+
groups = "qspi0_ctrl", "qspi0_data4";
715
+
function = "qspi0";
716
+
};
717
+
718
+
scif_clk_pins: scif-clk {
719
+
groups = "scif_clk";
720
+
function = "scif_clk";
721
+
};
722
+
723
+
scif_clk2_pins: scif-clk2 {
724
+
groups = "scif_clk2";
725
+
function = "scif_clk2";
726
+
};
727
+
728
+
sound_clk_pins: sound_clk {
729
+
groups = "audio_clkin", "audio_clkout";
730
+
function = "audio_clk";
731
+
};
732
+
733
+
sound_pins: sound {
734
+
groups = "ssi_ctrl", "ssi_data";
735
+
function = "ssi";
736
+
};
737
+
};
738
+
739
+
&rcar_sound {
740
+
pinctrl-0 = <&sound_clk_pins>, <&sound_pins>;
741
+
pinctrl-names = "default";
742
+
743
+
status = "okay";
744
+
745
+
/* audio_clkout */
746
+
clock-frequency = <12288000>;
747
+
748
+
ports {
749
+
rsnd_port: port {
750
+
rsnd_endpoint: endpoint {
751
+
remote-endpoint = <&ak4619_endpoint>;
752
+
bitclock-master;
753
+
frame-master;
754
+
755
+
/* see above [How to use Sound] */
756
+
playback = <&ssi0>;
757
+
capture = <&ssi0>;
758
+
};
759
+
};
760
+
};
761
+
};
762
+
763
+
&rpc {
764
+
pinctrl-0 = <&qspi0_pins>;
765
+
pinctrl-names = "default";
766
+
767
+
status = "okay";
768
+
769
+
flash@0 {
770
+
compatible = "spansion,s25fs512s", "jedec,spi-nor";
771
+
reg = <0>;
772
+
spi-max-frequency = <40000000>;
773
+
spi-rx-bus-width = <4>;
774
+
775
+
partitions {
776
+
compatible = "fixed-partitions";
777
+
#address-cells = <1>;
778
+
#size-cells = <1>;
779
+
780
+
boot@0 {
781
+
reg = <0x0 0x1200000>;
782
+
read-only;
783
+
};
784
+
user@1200000 {
785
+
reg = <0x1200000 0x2e00000>;
786
+
};
787
+
};
788
+
};
789
+
};
790
+
791
+
&rwdt {
792
+
timeout-sec = <60>;
793
+
status = "okay";
794
+
};
795
+
796
+
&scif_clk {
797
+
clock-frequency = <24000000>;
798
+
};
799
+
800
+
&scif_clk2 {
801
+
clock-frequency = <24000000>;
802
+
};
803
+
804
+
&vin00 {
805
+
status = "okay";
806
+
};
807
+
808
+
&vin01 {
809
+
status = "okay";
810
+
};
811
+
812
+
&vin02 {
813
+
status = "okay";
814
+
};
815
+
816
+
&vin03 {
817
+
status = "okay";
818
+
};
819
+
820
+
&vin04 {
821
+
status = "okay";
822
+
};
823
+
824
+
&vin05 {
825
+
status = "okay";
826
+
};
827
+
828
+
&vin06 {
829
+
status = "okay";
830
+
};
831
+
832
+
&vin07 {
833
+
status = "okay";
834
+
};
835
+
836
+
&vin08 {
837
+
status = "okay";
838
+
};
839
+
840
+
&vin09 {
841
+
status = "okay";
842
+
};
843
+
844
+
&vin10 {
845
+
status = "okay";
846
+
};
847
+
848
+
&vin11 {
849
+
status = "okay";
850
+
};
851
+
852
+
&vin12 {
853
+
status = "okay";
854
+
};
855
+
856
+
&vin13 {
857
+
status = "okay";
858
+
};
859
+
860
+
&vin14 {
861
+
status = "okay";
862
+
};
863
+
864
+
&vin15 {
865
+
status = "okay";
866
+
};
+1
-854
arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
+1
-854
arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
···
5
5
* Copyright (C) 2023 Renesas Electronics Corp.
6
6
* Copyright (C) 2024 Glider bv
7
7
*/
8
-
/*
9
-
* [How to use Sound]
10
-
*
11
-
* Because R-Car V4M has only 1 SSI, it cannot handle both Playback/Capture
12
-
* at the same time. You need to switch the direction which is controlled
13
-
* by the GP0_01 pin via amixer.
14
-
*
15
-
* Playback (CN9500)
16
-
* > amixer set "MUX" "Playback" // for GP0_01
17
-
* > amixer set "DAC 1" 85%
18
-
* > aplay xxx.wav
19
-
*
20
-
* Capture (CN9501)
21
-
* > amixer set "MUX" "Capture" // for GP0_01
22
-
* > amixer set "Mic 1" 80%
23
-
* > amixer set "ADC 1" on
24
-
* > amixer set 'ADC 1' 80%
25
-
* > arecord xxx hoge.wav
26
-
*/
27
8
28
9
/dts-v1/;
29
10
30
-
#include <dt-bindings/gpio/gpio.h>
31
-
#include <dt-bindings/input/input.h>
32
-
#include <dt-bindings/leds/common.h>
33
-
#include <dt-bindings/media/video-interfaces.h>
34
-
35
11
#include "r8a779h0.dtsi"
12
+
#include "gray-hawk-single.dtsi"
36
13
37
14
/ {
38
15
model = "Renesas Gray Hawk Single board based on r8a779h0";
39
16
compatible = "renesas,gray-hawk-single", "renesas,r8a779h0";
40
-
41
-
aliases {
42
-
i2c0 = &i2c0;
43
-
i2c1 = &i2c1;
44
-
i2c2 = &i2c2;
45
-
i2c3 = &i2c3;
46
-
serial0 = &hscif0;
47
-
serial1 = &hscif2;
48
-
ethernet0 = &avb0;
49
-
ethernet1 = &avb1;
50
-
ethernet2 = &avb2;
51
-
};
52
-
53
-
can_transceiver0: can-phy0 {
54
-
compatible = "nxp,tjr1443";
55
-
#phy-cells = <0>;
56
-
enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
57
-
max-bitrate = <5000000>;
58
-
};
59
-
60
-
chosen {
61
-
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
62
-
stdout-path = "serial0:921600n8";
63
-
};
64
-
65
-
sn65dsi86_refclk: clk-x6 {
66
-
compatible = "fixed-clock";
67
-
#clock-cells = <0>;
68
-
clock-frequency = <38400000>;
69
-
};
70
-
71
-
keys {
72
-
compatible = "gpio-keys";
73
-
74
-
pinctrl-0 = <&keys_pins>;
75
-
pinctrl-names = "default";
76
-
77
-
key-1 {
78
-
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
79
-
linux,code = <KEY_1>;
80
-
label = "SW47";
81
-
wakeup-source;
82
-
debounce-interval = <20>;
83
-
};
84
-
85
-
key-2 {
86
-
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
87
-
linux,code = <KEY_2>;
88
-
label = "SW48";
89
-
wakeup-source;
90
-
debounce-interval = <20>;
91
-
};
92
-
93
-
key-3 {
94
-
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
95
-
linux,code = <KEY_3>;
96
-
label = "SW49";
97
-
wakeup-source;
98
-
debounce-interval = <20>;
99
-
};
100
-
};
101
-
102
-
leds {
103
-
compatible = "gpio-leds";
104
-
105
-
led-1 {
106
-
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
107
-
color = <LED_COLOR_ID_GREEN>;
108
-
function = LED_FUNCTION_INDICATOR;
109
-
function-enumerator = <1>;
110
-
};
111
-
112
-
led-2 {
113
-
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
114
-
color = <LED_COLOR_ID_GREEN>;
115
-
function = LED_FUNCTION_INDICATOR;
116
-
function-enumerator = <2>;
117
-
};
118
-
119
-
led-3 {
120
-
gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
121
-
color = <LED_COLOR_ID_GREEN>;
122
-
function = LED_FUNCTION_INDICATOR;
123
-
function-enumerator = <3>;
124
-
};
125
-
};
126
-
127
-
memory@48000000 {
128
-
device_type = "memory";
129
-
/* first 128MB is reserved for secure area. */
130
-
reg = <0x0 0x48000000 0x0 0x78000000>;
131
-
};
132
-
133
-
memory@480000000 {
134
-
device_type = "memory";
135
-
reg = <0x4 0x80000000 0x1 0x80000000>;
136
-
};
137
-
138
-
pcie_clk: clk-9fgv0841-pci {
139
-
compatible = "fixed-clock";
140
-
clock-frequency = <100000000>;
141
-
#clock-cells = <0>;
142
-
};
143
-
144
-
mini-dp-con {
145
-
compatible = "dp-connector";
146
-
label = "CN5";
147
-
type = "mini";
148
-
149
-
port {
150
-
mini_dp_con_in: endpoint {
151
-
remote-endpoint = <&sn65dsi86_out0>;
152
-
};
153
-
};
154
-
};
155
-
156
-
reg_1p2v: regulator-1p2v {
157
-
compatible = "regulator-fixed";
158
-
regulator-name = "fixed-1.2V";
159
-
regulator-min-microvolt = <1200000>;
160
-
regulator-max-microvolt = <1200000>;
161
-
regulator-boot-on;
162
-
regulator-always-on;
163
-
};
164
-
165
-
reg_1p8v: regulator-1p8v {
166
-
compatible = "regulator-fixed";
167
-
regulator-name = "fixed-1.8V";
168
-
regulator-min-microvolt = <1800000>;
169
-
regulator-max-microvolt = <1800000>;
170
-
regulator-boot-on;
171
-
regulator-always-on;
172
-
};
173
-
174
-
reg_3p3v: regulator-3p3v {
175
-
compatible = "regulator-fixed";
176
-
regulator-name = "fixed-3.3V";
177
-
regulator-min-microvolt = <3300000>;
178
-
regulator-max-microvolt = <3300000>;
179
-
regulator-boot-on;
180
-
regulator-always-on;
181
-
};
182
-
183
-
sound_mux: sound-mux {
184
-
compatible = "simple-audio-mux";
185
-
mux-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
186
-
state-labels = "Playback", "Capture";
187
-
};
188
-
189
-
sound_card: sound {
190
-
compatible = "audio-graph-card2";
191
-
label = "rcar-sound";
192
-
aux-devs = <&sound_mux>; // for GP0_01
193
-
194
-
links = <&rsnd_port>; // AK4619 Audio Codec
195
-
};
196
-
};
197
-
198
-
&audio_clkin {
199
-
clock-frequency = <24576000>;
200
-
};
201
-
202
-
&avb0 {
203
-
pinctrl-0 = <&avb0_pins>;
204
-
pinctrl-names = "default";
205
-
phy-handle = <&avb0_phy>;
206
-
tx-internal-delay-ps = <2000>;
207
-
status = "okay";
208
-
209
-
mdio {
210
-
#address-cells = <1>;
211
-
#size-cells = <0>;
212
-
213
-
avb0_phy: ethernet-phy@0 {
214
-
compatible = "ethernet-phy-id0022.1622",
215
-
"ethernet-phy-ieee802.3-c22";
216
-
rxc-skew-ps = <1500>;
217
-
reg = <0>;
218
-
interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>;
219
-
reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
220
-
};
221
-
};
222
-
};
223
-
224
-
&avb1 {
225
-
pinctrl-0 = <&avb1_pins>;
226
-
pinctrl-names = "default";
227
-
phy-handle = <&avb1_phy>;
228
-
status = "okay";
229
-
230
-
mdio {
231
-
#address-cells = <1>;
232
-
#size-cells = <0>;
233
-
234
-
reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>;
235
-
reset-post-delay-us = <4000>;
236
-
237
-
avb1_phy: ethernet-phy@0 {
238
-
compatible = "ethernet-phy-ieee802.3-c45";
239
-
reg = <0>;
240
-
interrupts-extended = <&gpio6 3 IRQ_TYPE_LEVEL_LOW>;
241
-
};
242
-
};
243
-
};
244
-
245
-
&avb2 {
246
-
pinctrl-0 = <&avb2_pins>;
247
-
pinctrl-names = "default";
248
-
phy-handle = <&avb2_phy>;
249
-
status = "okay";
250
-
251
-
mdio {
252
-
#address-cells = <1>;
253
-
#size-cells = <0>;
254
-
255
-
reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
256
-
reset-post-delay-us = <4000>;
257
-
258
-
avb2_phy: ethernet-phy@0 {
259
-
compatible = "ethernet-phy-ieee802.3-c45";
260
-
reg = <0>;
261
-
interrupts-extended = <&gpio5 4 IRQ_TYPE_LEVEL_LOW>;
262
-
};
263
-
};
264
-
};
265
-
266
-
&can_clk {
267
-
clock-frequency = <40000000>;
268
-
};
269
-
270
-
&canfd {
271
-
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
272
-
pinctrl-names = "default";
273
-
status = "okay";
274
-
275
-
channel0 {
276
-
status = "okay";
277
-
phys = <&can_transceiver0>;
278
-
};
279
-
280
-
channel1 {
281
-
status = "okay";
282
-
};
283
-
};
284
-
285
-
&csi40 {
286
-
status = "okay";
287
-
288
-
ports {
289
-
#address-cells = <1>;
290
-
#size-cells = <0>;
291
-
292
-
port@0 {
293
-
reg = <0>;
294
-
295
-
csi40_in: endpoint {
296
-
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
297
-
clock-lanes = <0>;
298
-
data-lanes = <1 2 3 4>;
299
-
remote-endpoint = <&max96724_out0>;
300
-
};
301
-
};
302
-
};
303
-
};
304
-
305
-
&csi41 {
306
-
status = "okay";
307
-
308
-
ports {
309
-
#address-cells = <1>;
310
-
#size-cells = <0>;
311
-
312
-
port@0 {
313
-
reg = <0>;
314
-
315
-
csi41_in: endpoint {
316
-
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
317
-
clock-lanes = <0>;
318
-
data-lanes = <1 2 3 4>;
319
-
remote-endpoint = <&max96724_out1>;
320
-
};
321
-
};
322
-
};
323
-
};
324
-
325
-
&dsi0 {
326
-
status = "okay";
327
-
328
-
ports {
329
-
port@1 {
330
-
reg = <1>;
331
-
332
-
dsi0_out: endpoint {
333
-
remote-endpoint = <&sn65dsi86_in0>;
334
-
data-lanes = <1 2 3 4>;
335
-
};
336
-
};
337
-
};
338
-
};
339
-
340
-
&du {
341
-
status = "okay";
342
-
};
343
-
344
-
&extal_clk {
345
-
clock-frequency = <16666666>;
346
-
};
347
-
348
-
&extalr_clk {
349
-
clock-frequency = <32768>;
350
-
};
351
-
352
-
&gpio1 {
353
-
audio-power-hog {
354
-
gpio-hog;
355
-
gpios = <8 GPIO_ACTIVE_HIGH>;
356
-
output-high;
357
-
line-name = "Audio-Power";
358
-
};
359
-
};
360
-
361
-
&hscif0 {
362
-
pinctrl-0 = <&hscif0_pins>;
363
-
pinctrl-names = "default";
364
-
bootph-all;
365
-
366
-
uart-has-rtscts;
367
-
status = "okay";
368
-
};
369
-
370
-
&hscif2 {
371
-
pinctrl-0 = <&hscif2_pins>;
372
-
pinctrl-names = "default";
373
-
374
-
uart-has-rtscts;
375
-
status = "okay";
376
-
};
377
-
378
-
&i2c0 {
379
-
pinctrl-0 = <&i2c0_pins>;
380
-
pinctrl-names = "default";
381
-
382
-
status = "okay";
383
-
clock-frequency = <400000>;
384
-
385
-
io_expander_a: gpio@20 {
386
-
compatible = "onnn,pca9654";
387
-
reg = <0x20>;
388
-
interrupts-extended = <&gpio0 0 IRQ_TYPE_LEVEL_LOW>;
389
-
gpio-controller;
390
-
#gpio-cells = <2>;
391
-
interrupt-controller;
392
-
#interrupt-cells = <2>;
393
-
};
394
-
395
-
io_expander_b: gpio@21 {
396
-
compatible = "onnn,pca9654";
397
-
reg = <0x21>;
398
-
gpio-controller;
399
-
#gpio-cells = <2>;
400
-
};
401
-
402
-
io_expander_c: gpio@22 {
403
-
compatible = "onnn,pca9654";
404
-
reg = <0x22>;
405
-
gpio-controller;
406
-
#gpio-cells = <2>;
407
-
};
408
-
409
-
eeprom@50 {
410
-
compatible = "rohm,br24g01", "atmel,24c01";
411
-
label = "cpu-board";
412
-
reg = <0x50>;
413
-
pagesize = <8>;
414
-
};
415
-
416
-
eeprom@51 {
417
-
compatible = "rohm,br24g01", "atmel,24c01";
418
-
label = "breakout-board";
419
-
reg = <0x51>;
420
-
pagesize = <8>;
421
-
};
422
-
423
-
eeprom@52 {
424
-
compatible = "rohm,br24g01", "atmel,24c01";
425
-
label = "csi-dsi-sub-board-id";
426
-
reg = <0x52>;
427
-
pagesize = <8>;
428
-
};
429
-
430
-
eeprom@53 {
431
-
compatible = "rohm,br24g01", "atmel,24c01";
432
-
label = "ethernet-sub-board-id";
433
-
reg = <0x53>;
434
-
pagesize = <8>;
435
-
};
436
-
};
437
-
438
-
&i2c1 {
439
-
pinctrl-0 = <&i2c1_pins>;
440
-
pinctrl-names = "default";
441
-
442
-
status = "okay";
443
-
clock-frequency = <400000>;
444
-
445
-
bridge@2c {
446
-
pinctrl-0 = <&irq0_pins>;
447
-
pinctrl-names = "default";
448
-
449
-
compatible = "ti,sn65dsi86";
450
-
reg = <0x2c>;
451
-
452
-
clocks = <&sn65dsi86_refclk>;
453
-
clock-names = "refclk";
454
-
455
-
interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>;
456
-
457
-
enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
458
-
459
-
vccio-supply = <®_1p8v>;
460
-
vpll-supply = <®_1p8v>;
461
-
vcca-supply = <®_1p2v>;
462
-
vcc-supply = <®_1p2v>;
463
-
464
-
ports {
465
-
#address-cells = <1>;
466
-
#size-cells = <0>;
467
-
468
-
port@0 {
469
-
reg = <0>;
470
-
471
-
sn65dsi86_in0: endpoint {
472
-
remote-endpoint = <&dsi0_out>;
473
-
};
474
-
};
475
-
476
-
port@1 {
477
-
reg = <1>;
478
-
479
-
sn65dsi86_out0: endpoint {
480
-
remote-endpoint = <&mini_dp_con_in>;
481
-
};
482
-
};
483
-
};
484
-
};
485
-
486
-
gmsl0: gmsl-deserializer@4e {
487
-
compatible = "maxim,max96724";
488
-
reg = <0x4e>;
489
-
enable-gpios = <&io_expander_b 0 GPIO_ACTIVE_HIGH>;
490
-
491
-
ports {
492
-
#address-cells = <1>;
493
-
#size-cells = <0>;
494
-
495
-
port@4 {
496
-
reg = <4>;
497
-
max96724_out0: endpoint {
498
-
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
499
-
clock-lanes = <0>;
500
-
data-lanes = <1 2 3 4>;
501
-
remote-endpoint = <&csi40_in>;
502
-
};
503
-
};
504
-
};
505
-
};
506
-
507
-
gmsl1: gmsl-deserializer@4f {
508
-
compatible = "maxim,max96724";
509
-
reg = <0x4f>;
510
-
enable-gpios = <&io_expander_c 0 GPIO_ACTIVE_HIGH>;
511
-
512
-
ports {
513
-
#address-cells = <1>;
514
-
#size-cells = <0>;
515
-
516
-
port@4 {
517
-
reg = <4>;
518
-
max96724_out1: endpoint {
519
-
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
520
-
clock-lanes = <0>;
521
-
data-lanes = <1 2 3 4>;
522
-
remote-endpoint = <&csi41_in>;
523
-
};
524
-
};
525
-
};
526
-
};
527
-
};
528
-
529
-
&i2c3 {
530
-
pinctrl-0 = <&i2c3_pins>;
531
-
pinctrl-names = "default";
532
-
533
-
status = "okay";
534
-
clock-frequency = <400000>;
535
-
536
-
codec@10 {
537
-
compatible = "asahi-kasei,ak4619";
538
-
reg = <0x10>;
539
-
540
-
clocks = <&rcar_sound>;
541
-
clock-names = "mclk";
542
-
543
-
#sound-dai-cells = <0>;
544
-
port {
545
-
ak4619_endpoint: endpoint {
546
-
remote-endpoint = <&rsnd_endpoint>;
547
-
};
548
-
};
549
-
};
550
-
};
551
-
552
-
&isp0 {
553
-
status = "okay";
554
-
};
555
-
556
-
&isp1 {
557
-
status = "okay";
558
-
};
559
-
560
-
&mmc0 {
561
-
pinctrl-0 = <&mmc_pins>;
562
-
pinctrl-1 = <&mmc_pins>;
563
-
pinctrl-names = "default", "state_uhs";
564
-
565
-
vmmc-supply = <®_3p3v>;
566
-
vqmmc-supply = <®_1p8v>;
567
-
mmc-hs200-1_8v;
568
-
mmc-hs400-1_8v;
569
-
bus-width = <8>;
570
-
no-sd;
571
-
no-sdio;
572
-
non-removable;
573
-
full-pwr-cycle-in-suspend;
574
-
status = "okay";
575
-
};
576
-
577
-
&pcie0_clkref {
578
-
compatible = "gpio-gate-clock";
579
-
clocks = <&pcie_clk>;
580
-
enable-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
581
-
/delete-property/ clock-frequency;
582
-
};
583
-
584
-
&pciec0 {
585
-
reset-gpios = <&io_expander_a 0 GPIO_ACTIVE_LOW>;
586
-
status = "okay";
587
-
};
588
-
589
-
&pfc {
590
-
pinctrl-0 = <&scif_clk_pins>, <&scif_clk2_pins>;
591
-
pinctrl-names = "default";
592
-
593
-
avb0_pins: avb0 {
594
-
mux {
595
-
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
596
-
"avb0_txcrefclk";
597
-
function = "avb0";
598
-
};
599
-
600
-
pins_mdio {
601
-
groups = "avb0_mdio";
602
-
drive-strength = <21>;
603
-
};
604
-
605
-
pins_mii {
606
-
groups = "avb0_rgmii";
607
-
drive-strength = <21>;
608
-
};
609
-
};
610
-
611
-
avb1_pins: avb1 {
612
-
mux {
613
-
groups = "avb1_link", "avb1_mdio", "avb1_rgmii",
614
-
"avb1_txcrefclk";
615
-
function = "avb1";
616
-
};
617
-
618
-
link {
619
-
groups = "avb1_link";
620
-
bias-disable;
621
-
};
622
-
623
-
mdio {
624
-
groups = "avb1_mdio";
625
-
drive-strength = <24>;
626
-
bias-disable;
627
-
};
628
-
629
-
rgmii {
630
-
groups = "avb1_rgmii";
631
-
drive-strength = <24>;
632
-
bias-disable;
633
-
};
634
-
};
635
-
636
-
avb2_pins: avb2 {
637
-
mux {
638
-
groups = "avb2_link", "avb2_mdio", "avb2_rgmii",
639
-
"avb2_txcrefclk";
640
-
function = "avb2";
641
-
};
642
-
643
-
link {
644
-
groups = "avb2_link";
645
-
bias-disable;
646
-
};
647
-
648
-
mdio {
649
-
groups = "avb2_mdio";
650
-
drive-strength = <24>;
651
-
bias-disable;
652
-
};
653
-
654
-
rgmii {
655
-
groups = "avb2_rgmii";
656
-
drive-strength = <24>;
657
-
bias-disable;
658
-
};
659
-
};
660
-
661
-
can_clk_pins: can-clk {
662
-
groups = "can_clk";
663
-
function = "can_clk";
664
-
};
665
-
666
-
canfd0_pins: canfd0 {
667
-
groups = "canfd0_data";
668
-
function = "canfd0";
669
-
};
670
-
671
-
canfd1_pins: canfd1 {
672
-
groups = "canfd1_data";
673
-
function = "canfd1";
674
-
};
675
-
676
-
hscif0_pins: hscif0 {
677
-
groups = "hscif0_data", "hscif0_ctrl";
678
-
function = "hscif0";
679
-
};
680
-
681
-
hscif2_pins: hscif2 {
682
-
groups = "hscif2_data", "hscif2_ctrl";
683
-
function = "hscif2";
684
-
};
685
-
686
-
i2c0_pins: i2c0 {
687
-
groups = "i2c0";
688
-
function = "i2c0";
689
-
};
690
-
691
-
i2c1_pins: i2c1 {
692
-
groups = "i2c1";
693
-
function = "i2c1";
694
-
};
695
-
696
-
i2c3_pins: i2c3 {
697
-
groups = "i2c3";
698
-
function = "i2c3";
699
-
};
700
-
701
-
irq0_pins: irq0_pins {
702
-
groups = "intc_ex_irq0_a";
703
-
function = "intc_ex";
704
-
};
705
-
706
-
keys_pins: keys {
707
-
pins = "GP_5_0", "GP_5_1", "GP_5_2";
708
-
bias-pull-up;
709
-
};
710
-
711
-
mmc_pins: mmc {
712
-
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
713
-
function = "mmc";
714
-
power-source = <1800>;
715
-
};
716
-
717
-
qspi0_pins: qspi0 {
718
-
groups = "qspi0_ctrl", "qspi0_data4";
719
-
function = "qspi0";
720
-
};
721
-
722
-
scif_clk_pins: scif-clk {
723
-
groups = "scif_clk";
724
-
function = "scif_clk";
725
-
};
726
-
727
-
scif_clk2_pins: scif-clk2 {
728
-
groups = "scif_clk2";
729
-
function = "scif_clk2";
730
-
};
731
-
732
-
sound_clk_pins: sound_clk {
733
-
groups = "audio_clkin", "audio_clkout";
734
-
function = "audio_clk";
735
-
};
736
-
737
-
sound_pins: sound {
738
-
groups = "ssi_ctrl", "ssi_data";
739
-
function = "ssi";
740
-
};
741
-
};
742
-
743
-
&rcar_sound {
744
-
pinctrl-0 = <&sound_clk_pins>, <&sound_pins>;
745
-
pinctrl-names = "default";
746
-
747
-
status = "okay";
748
-
749
-
/* audio_clkout */
750
-
clock-frequency = <12288000>;
751
-
752
-
ports {
753
-
rsnd_port: port {
754
-
rsnd_endpoint: endpoint {
755
-
remote-endpoint = <&ak4619_endpoint>;
756
-
bitclock-master;
757
-
frame-master;
758
-
759
-
/* see above [How to use Sound] */
760
-
playback = <&ssi0>;
761
-
capture = <&ssi0>;
762
-
};
763
-
};
764
-
};
765
-
};
766
-
767
-
&rpc {
768
-
pinctrl-0 = <&qspi0_pins>;
769
-
pinctrl-names = "default";
770
-
771
-
status = "okay";
772
-
773
-
flash@0 {
774
-
compatible = "spansion,s25fs512s", "jedec,spi-nor";
775
-
reg = <0>;
776
-
spi-max-frequency = <40000000>;
777
-
spi-rx-bus-width = <4>;
778
-
779
-
partitions {
780
-
compatible = "fixed-partitions";
781
-
#address-cells = <1>;
782
-
#size-cells = <1>;
783
-
784
-
boot@0 {
785
-
reg = <0x0 0x1200000>;
786
-
read-only;
787
-
};
788
-
user@1200000 {
789
-
reg = <0x1200000 0x2e00000>;
790
-
};
791
-
};
792
-
};
793
-
};
794
-
795
-
&rwdt {
796
-
timeout-sec = <60>;
797
-
status = "okay";
798
-
};
799
-
800
-
&scif_clk {
801
-
clock-frequency = <24000000>;
802
-
};
803
-
804
-
&scif_clk2 {
805
-
clock-frequency = <24000000>;
806
-
};
807
-
808
-
&vin00 {
809
-
status = "okay";
810
-
};
811
-
812
-
&vin01 {
813
-
status = "okay";
814
-
};
815
-
816
-
&vin02 {
817
-
status = "okay";
818
-
};
819
-
820
-
&vin03 {
821
-
status = "okay";
822
-
};
823
-
824
-
&vin04 {
825
-
status = "okay";
826
-
};
827
-
828
-
&vin05 {
829
-
status = "okay";
830
-
};
831
-
832
-
&vin06 {
833
-
status = "okay";
834
-
};
835
-
836
-
&vin07 {
837
-
status = "okay";
838
-
};
839
-
840
-
&vin08 {
841
-
status = "okay";
842
-
};
843
-
844
-
&vin09 {
845
-
status = "okay";
846
-
};
847
-
848
-
&vin10 {
849
-
status = "okay";
850
-
};
851
-
852
-
&vin11 {
853
-
status = "okay";
854
-
};
855
-
856
-
&vin12 {
857
-
status = "okay";
858
-
};
859
-
860
-
&vin13 {
861
-
status = "okay";
862
-
};
863
-
864
-
&vin14 {
865
-
status = "okay";
866
-
};
867
-
868
-
&vin15 {
869
-
status = "okay";
870
17
};
+17
arch/arm64/boot/dts/renesas/r8a779h2-gray-hawk-single.dts
+17
arch/arm64/boot/dts/renesas/r8a779h2-gray-hawk-single.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Source for the R-Car V4M-7 Gray Hawk Single board
4
+
*
5
+
* Copyright (C) 2025 Glider bv
6
+
*/
7
+
8
+
/dts-v1/;
9
+
10
+
#include "r8a779h2.dtsi"
11
+
#include "gray-hawk-single.dtsi"
12
+
13
+
/ {
14
+
model = "Renesas Gray Hawk Single board based on r8a779h2";
15
+
compatible = "renesas,gray-hawk-single", "renesas,r8a779h2",
16
+
"renesas,r8a779h0";
17
+
};
+12
arch/arm64/boot/dts/renesas/r8a779h2.dtsi
+12
arch/arm64/boot/dts/renesas/r8a779h2.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Source for the R-Car V4M-7 (R8A779H2) SoC
4
+
*
5
+
* Copyright (C) 2024 Renesas Electronics Corp.
6
+
*/
7
+
8
+
#include "r8a779h0.dtsi"
9
+
10
+
/ {
11
+
compatible = "renesas,r8a779h2", "renesas,r8a779h0";
12
+
};
+37
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+37
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
···
8
8
/dts-v1/;
9
9
10
10
/* Switch selection settings */
11
+
#define SW_LCD_EN 0
11
12
#define SW_GPIO8_CAN0_STB 0
12
13
#define SW_GPIO9_CAN1_STB 0
13
14
#define SW_LCD_EN 0
···
16
15
#define SW_SD0_DEV_SEL 0
17
16
#define SW_SDIO_M2E 0
18
17
18
+
#define PMOD_GPIO4 0
19
+
#define PMOD_GPIO6 0
20
+
#define PMOD_GPIO7 0
21
+
22
+
#define KEY_1_GPIO RZG3E_GPIO(3, 1)
23
+
#define KEY_2_GPIO RZG3E_GPIO(8, 4)
24
+
#define KEY_3_GPIO RZG3E_GPIO(8, 5)
25
+
19
26
#include <dt-bindings/gpio/gpio.h>
27
+
#include <dt-bindings/input/input.h>
20
28
#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
21
29
#include "r9a09g047e57.dtsi"
22
30
#include "rzg3e-smarc-som.dtsi"
···
89
79
pinctrl-names = "default";
90
80
};
91
81
82
+
&keys {
83
+
key-sleep {
84
+
pinctrl-0 = <&nmi_pins>;
85
+
pinctrl-names = "default";
86
+
87
+
interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>;
88
+
linux,code = <KEY_SLEEP>;
89
+
label = "SLEEP";
90
+
debounce-interval = <20>;
91
+
};
92
+
#if PMOD_GPIO4
93
+
/delete-node/ key-1;
94
+
#endif
95
+
96
+
#if SW_LCD_EN || PMOD_GPIO6
97
+
/delete-node/ key-2;
98
+
#endif
99
+
100
+
#if SW_LCD_EN || PMOD_GPIO7
101
+
/delete-node/ key-3;
102
+
#endif
103
+
};
104
+
92
105
&pinctrl {
93
106
canfd_pins: canfd {
94
107
can1_pins: can1 {
···
128
95
i2c0_pins: i2c0 {
129
96
pinmux = <RZG3E_PORT_PINMUX(D, 4, 4)>, /* SCL0 */
130
97
<RZG3E_PORT_PINMUX(D, 5, 4)>; /* SDA0 */
98
+
};
99
+
100
+
nmi_pins: nmi {
101
+
pinmux = <RZG3E_PORT_PINMUX(S, 0, 0)>; /* NMI */
131
102
};
132
103
133
104
scif_pins: scif {
+21
arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+21
arch/arm64/boot/dts/renesas/r9a09g056.dtsi
···
206
206
resets = <&cpg 0x30>;
207
207
};
208
208
209
+
xspi: spi@11030000 {
210
+
compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi";
211
+
reg = <0 0x11030000 0 0x10000>,
212
+
<0 0x20000000 0 0x10000000>;
213
+
reg-names = "regs", "dirmap";
214
+
interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
215
+
<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
216
+
interrupt-names = "pulse", "err_pulse";
217
+
clocks = <&cpg CPG_MOD 0x9f>,
218
+
<&cpg CPG_MOD 0xa0>,
219
+
<&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>,
220
+
<&cpg CPG_MOD 0xa1>;
221
+
clock-names = "ahb", "axi", "spi", "spix2";
222
+
resets = <&cpg 0xa3>, <&cpg 0xa4>;
223
+
reset-names = "hresetn", "aresetn";
224
+
power-domains = <&cpg>;
225
+
#address-cells = <1>;
226
+
#size-cells = <0>;
227
+
status = "disabled";
228
+
};
229
+
209
230
ostm0: timer@11800000 {
210
231
compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
211
232
reg = <0x0 0x11800000 0x0 0x1000>;
+65
-1
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
+65
-1
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
···
48
48
regulator-always-on;
49
49
};
50
50
51
+
reg_1p8v: regulator-1p8v {
52
+
compatible = "regulator-fixed";
53
+
regulator-name = "fixed-1.8V";
54
+
regulator-min-microvolt = <1800000>;
55
+
regulator-max-microvolt = <1800000>;
56
+
regulator-boot-on;
57
+
regulator-always-on;
58
+
};
59
+
51
60
reg_3p3v: regulator-3p3v {
52
61
compatible = "regulator-fixed";
53
62
regulator-name = "fixed-3.3V";
···
257
248
output-enable;
258
249
};
259
250
260
-
eth1_pins: eth0 {
251
+
eth1_pins: eth1 {
261
252
pins = "ET1_TXC_TXCLK";
262
253
output-enable;
263
254
};
···
341
332
pinmux = <RZV2N_PORT_PINMUX(9, 5, 14)>; /* VBUS */
342
333
};
343
334
};
335
+
336
+
xspi_pins: xspi0 {
337
+
ctrl {
338
+
pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP";
339
+
output-enable;
340
+
};
341
+
342
+
io {
343
+
pins = "XSPI0_IO0", "XSPI0_IO1", "XSPI0_IO2", "XSPI0_IO3";
344
+
renesas,output-impedance = <3>;
345
+
};
346
+
};
344
347
};
345
348
346
349
&qextal_clk {
···
394
373
395
374
&wdt1 {
396
375
status = "okay";
376
+
};
377
+
378
+
&xspi {
379
+
pinctrl-0 = <&xspi_pins>;
380
+
pinctrl-names = "default";
381
+
/*
382
+
* MT25QU512ABB8E12 flash chip is capable of running at 166MHz
383
+
* clock frequency. Set the clock frequency to the maximum 133MHz
384
+
* supported by the RZ/V2N SoC.
385
+
*/
386
+
assigned-clocks = <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>;
387
+
assigned-clock-rates = <133333334>;
388
+
status = "okay";
389
+
390
+
flash@0 {
391
+
compatible = "jedec,spi-nor";
392
+
reg = <0>;
393
+
vcc-supply = <®_1p8v>;
394
+
m25p,fast-read;
395
+
spi-tx-bus-width = <4>;
396
+
spi-rx-bus-width = <4>;
397
+
398
+
partitions {
399
+
compatible = "fixed-partitions";
400
+
#address-cells = <1>;
401
+
#size-cells = <1>;
402
+
403
+
partition@0 {
404
+
label = "bl2";
405
+
reg = <0x00000000 0x00060000>;
406
+
};
407
+
408
+
partition@60000 {
409
+
label = "fip";
410
+
reg = <0x00060000 0x1fa0000>;
411
+
};
412
+
413
+
partition@2000000 {
414
+
label = "user";
415
+
reg = <0x2000000 0x2000000>;
416
+
};
417
+
};
418
+
};
397
419
};
+21
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+21
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
···
280
280
resets = <&cpg 0x30>;
281
281
};
282
282
283
+
xspi: spi@11030000 {
284
+
compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi";
285
+
reg = <0 0x11030000 0 0x10000>,
286
+
<0 0x20000000 0 0x10000000>;
287
+
reg-names = "regs", "dirmap";
288
+
interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
289
+
<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
290
+
interrupt-names = "pulse", "err_pulse";
291
+
clocks = <&cpg CPG_MOD 0x9f>,
292
+
<&cpg CPG_MOD 0xa0>,
293
+
<&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>,
294
+
<&cpg CPG_MOD 0xa1>;
295
+
clock-names = "ahb", "axi", "spi", "spix2";
296
+
resets = <&cpg 0xa3>, <&cpg 0xa4>;
297
+
reset-names = "hresetn", "aresetn";
298
+
power-domains = <&cpg>;
299
+
#address-cells = <1>;
300
+
#size-cells = <0>;
301
+
status = "disabled";
302
+
};
303
+
283
304
dmac0: dma-controller@11400000 {
284
305
compatible = "renesas,r9a09g057-dmac";
285
306
reg = <0 0x11400000 0 0x10000>;
+65
-1
arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
+65
-1
arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
···
55
55
regulator-always-on;
56
56
};
57
57
58
+
reg_1p8v: regulator-1p8v {
59
+
compatible = "regulator-fixed";
60
+
regulator-name = "fixed-1.8V";
61
+
regulator-min-microvolt = <1800000>;
62
+
regulator-max-microvolt = <1800000>;
63
+
regulator-boot-on;
64
+
regulator-always-on;
65
+
};
66
+
58
67
reg_3p3v: regulator-3p3v {
59
68
compatible = "regulator-fixed";
60
69
···
280
271
output-enable;
281
272
};
282
273
283
-
eth1_pins: eth0 {
274
+
eth1_pins: eth1 {
284
275
pins = "ET1_TXC_TXCLK";
285
276
output-enable;
286
277
};
···
370
361
pinmux = <RZV2H_PORT_PINMUX(6, 6, 14)>; /* VBUS */
371
362
};
372
363
};
364
+
365
+
xspi_pins: xspi0 {
366
+
ctrl {
367
+
pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP";
368
+
output-enable;
369
+
};
370
+
371
+
io {
372
+
pins = "XSPI0_IO0", "XSPI0_IO1", "XSPI0_IO2", "XSPI0_IO3";
373
+
renesas,output-impedance = <3>;
374
+
};
375
+
};
373
376
};
374
377
375
378
&qextal_clk {
···
435
414
436
415
&wdt1 {
437
416
status = "okay";
417
+
};
418
+
419
+
&xspi {
420
+
pinctrl-0 = <&xspi_pins>;
421
+
pinctrl-names = "default";
422
+
/*
423
+
* MT25QU512ABB8E12 flash chip is capable of running at 166MHz
424
+
* clock frequency. Set the clock frequency to the maximum 133MHz
425
+
* supported by the RZ/V2H SoC.
426
+
*/
427
+
assigned-clocks = <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>;
428
+
assigned-clock-rates = <133333334>;
429
+
status = "okay";
430
+
431
+
flash@0 {
432
+
compatible = "jedec,spi-nor";
433
+
reg = <0>;
434
+
vcc-supply = <®_1p8v>;
435
+
m25p,fast-read;
436
+
spi-tx-bus-width = <4>;
437
+
spi-rx-bus-width = <4>;
438
+
439
+
partitions {
440
+
compatible = "fixed-partitions";
441
+
#address-cells = <1>;
442
+
#size-cells = <1>;
443
+
444
+
partition@0 {
445
+
label = "bl2";
446
+
reg = <0x00000000 0x00060000>;
447
+
};
448
+
449
+
partition@60000 {
450
+
label = "fip";
451
+
reg = <0x00060000 0x1fa0000>;
452
+
};
453
+
454
+
partition@2000000 {
455
+
label = "user";
456
+
reg = <0x2000000 0x2000000>;
457
+
};
458
+
};
459
+
};
438
460
};
+31
arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+31
arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
···
23
23
* SW_GPIO9_CAN1_STB:
24
24
* 0 - Connect to GPIO9 PMOD (default)
25
25
* 1 - Connect to CAN1 transceiver STB pin
26
+
*
27
+
* GPIO keys are enabled by default. Use PMOD_GPIO macros to disable them
28
+
* if needed.
26
29
*/
27
30
28
31
/ {
···
55
52
#phy-cells = <0>;
56
53
max-bitrate = <8000000>;
57
54
status = "disabled";
55
+
};
56
+
57
+
keys: keys {
58
+
compatible = "gpio-keys";
59
+
60
+
key-1 {
61
+
interrupts-extended = <&pinctrl KEY_1_GPIO IRQ_TYPE_EDGE_FALLING>;
62
+
linux,code = <KEY_1>;
63
+
label = "USER_SW1";
64
+
wakeup-source;
65
+
debounce-interval = <20>;
66
+
};
67
+
68
+
key-2 {
69
+
interrupts-extended = <&pinctrl KEY_2_GPIO IRQ_TYPE_EDGE_FALLING>;
70
+
linux,code = <KEY_2>;
71
+
label = "USER_SW2";
72
+
wakeup-source;
73
+
debounce-interval = <20>;
74
+
};
75
+
76
+
key-3 {
77
+
interrupts-extended = <&pinctrl KEY_3_GPIO IRQ_TYPE_EDGE_FALLING>;
78
+
linux,code = <KEY_3>;
79
+
label = "USER_SW3";
80
+
wakeup-source;
81
+
debounce-interval = <20>;
82
+
};
58
83
};
59
84
};
60
85
+111
arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+111
arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
···
26
26
compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
27
27
28
28
aliases {
29
+
ethernet0 = ð0;
30
+
ethernet1 = ð1;
29
31
i2c2 = &i2c2;
30
32
mmc0 = &sdhi0;
31
33
mmc2 = &sdhi2;
···
79
77
clock-frequency = <48000000>;
80
78
};
81
79
80
+
ð0 {
81
+
phy-handle = <&phy0>;
82
+
phy-mode = "rgmii-id";
83
+
84
+
pinctrl-0 = <ð0_pins>;
85
+
pinctrl-names = "default";
86
+
status = "okay";
87
+
};
88
+
89
+
ð1 {
90
+
phy-handle = <&phy1>;
91
+
phy-mode = "rgmii-id";
92
+
93
+
pinctrl-0 = <ð1_pins>;
94
+
pinctrl-names = "default";
95
+
status = "okay";
96
+
};
97
+
82
98
&gpu {
83
99
status = "okay";
84
100
mali-supply = <®_vdd0p8v_others>;
···
122
102
};
123
103
};
124
104
105
+
&mdio0 {
106
+
phy0: ethernet-phy@7 {
107
+
compatible = "ethernet-phy-id0022.1640",
108
+
"ethernet-phy-ieee802.3-c22";
109
+
reg = <7>;
110
+
interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
111
+
rxc-skew-psec = <1400>;
112
+
txc-skew-psec = <1400>;
113
+
rxdv-skew-psec = <0>;
114
+
txdv-skew-psec = <0>;
115
+
rxd0-skew-psec = <0>;
116
+
rxd1-skew-psec = <0>;
117
+
rxd2-skew-psec = <0>;
118
+
rxd3-skew-psec = <0>;
119
+
txd0-skew-psec = <0>;
120
+
txd1-skew-psec = <0>;
121
+
txd2-skew-psec = <0>;
122
+
txd3-skew-psec = <0>;
123
+
};
124
+
};
125
+
126
+
&mdio1 {
127
+
phy1: ethernet-phy@7 {
128
+
compatible = "ethernet-phy-id0022.1640",
129
+
"ethernet-phy-ieee802.3-c22";
130
+
reg = <7>;
131
+
interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
132
+
rxc-skew-psec = <1400>;
133
+
txc-skew-psec = <1400>;
134
+
rxdv-skew-psec = <0>;
135
+
txdv-skew-psec = <0>;
136
+
rxd0-skew-psec = <0>;
137
+
rxd1-skew-psec = <0>;
138
+
rxd2-skew-psec = <0>;
139
+
rxd3-skew-psec = <0>;
140
+
txd0-skew-psec = <0>;
141
+
txd1-skew-psec = <0>;
142
+
txd2-skew-psec = <0>;
143
+
txd3-skew-psec = <0>;
144
+
};
145
+
};
146
+
125
147
&pinctrl {
148
+
eth0_pins: eth0 {
149
+
clk {
150
+
pinmux = <RZG3E_PORT_PINMUX(B, 1, 1)>; /* TXC */
151
+
output-enable;
152
+
};
153
+
154
+
ctrl {
155
+
pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
156
+
<RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
157
+
<RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
158
+
<RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
159
+
<RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
160
+
<RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
161
+
<RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
162
+
<RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
163
+
<RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
164
+
<RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
165
+
<RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
166
+
<RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
167
+
<RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
168
+
<RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
169
+
};
170
+
};
171
+
172
+
eth1_pins: eth1 {
173
+
clk {
174
+
pinmux = <RZG3E_PORT_PINMUX(E, 1, 1)>; /* TXC */
175
+
output-enable;
176
+
};
177
+
178
+
ctrl {
179
+
180
+
pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
181
+
<RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
182
+
<RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
183
+
<RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
184
+
<RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
185
+
<RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
186
+
<RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
187
+
<RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
188
+
<RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
189
+
<RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
190
+
<RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
191
+
<RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
192
+
<RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
193
+
<RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
194
+
};
195
+
};
196
+
126
197
i2c2_pins: i2c {
127
198
pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
128
199
<RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
+50
arch/arm64/boot/dts/renesas/rzv2-evk-cn15-emmc.dtso
+50
arch/arm64/boot/dts/renesas/rzv2-evk-cn15-emmc.dtso
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Shared DT overlay for the eMMC Sub Board (RTK0EF0186B02000BJ), which
4
+
* is connected to the CN15 connector on the RZ/V2H and RZ/V2N EVKs.
5
+
*
6
+
* Copyright (C) 2025 Renesas Electronics Corp.
7
+
*/
8
+
9
+
/dts-v1/;
10
+
/plugin/;
11
+
12
+
#include <dt-bindings/gpio/gpio.h>
13
+
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
14
+
15
+
&{/} {
16
+
aliases {
17
+
mmc0 = "/soc/mmc@15c00000";
18
+
};
19
+
};
20
+
21
+
&pinctrl {
22
+
sdhi0_emmc_pins: emmc-pins {
23
+
sd0-clk {
24
+
pins = "SD0CLK";
25
+
renesas,output-impedance = <3>;
26
+
slew-rate = <0>;
27
+
};
28
+
29
+
sd0-dat-cmd {
30
+
pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3", "SD0DAT4",
31
+
"SD0DAT5", "SD0DAT6", "SD0DAT7", "SD0CMD";
32
+
input-enable;
33
+
renesas,output-impedance = <3>;
34
+
slew-rate = <0>;
35
+
};
36
+
};
37
+
};
38
+
39
+
&sdhi0 {
40
+
pinctrl-0 = <&sdhi0_emmc_pins>;
41
+
pinctrl-1 = <&sdhi0_emmc_pins>;
42
+
pinctrl-names = "default", "state_uhs";
43
+
vmmc-supply = <®_3p3v>;
44
+
vqmmc-supply = <®_1p8v>;
45
+
bus-width = <8>;
46
+
mmc-hs200-1_8v;
47
+
non-removable;
48
+
fixed-emmc-driver-type = <1>;
49
+
status = "okay";
50
+
};
+69
arch/arm64/boot/dts/renesas/rzv2-evk-cn15-sd.dtso
+69
arch/arm64/boot/dts/renesas/rzv2-evk-cn15-sd.dtso
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Shared DT overlay for the microSD Sub Board (RTK0EF0186B01000BJ), which
4
+
* is connected to the CN15 connector on the RZ/V2H and RZ/V2N EVKs.
5
+
*
6
+
* Copyright (C) 2025 Renesas Electronics Corp.
7
+
*/
8
+
9
+
/dts-v1/;
10
+
/plugin/;
11
+
12
+
#include <dt-bindings/gpio/gpio.h>
13
+
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
14
+
15
+
&{/} {
16
+
aliases {
17
+
mmc0 = "/soc/mmc@15c00000";
18
+
};
19
+
20
+
vqmmc_sdhi0: regulator-vqmmc-sdhi0 {
21
+
compatible = "regulator-gpio";
22
+
regulator-name = "SDHI0 VqmmC";
23
+
gpios = <&pinctrl RZG2L_GPIO(10, 0) GPIO_ACTIVE_HIGH>;
24
+
regulator-min-microvolt = <1800000>;
25
+
regulator-max-microvolt = <3300000>;
26
+
gpios-states = <0>;
27
+
states = <3300000 0>, <1800000 1>;
28
+
};
29
+
};
30
+
31
+
&pinctrl {
32
+
sdhi0-pwr-en-hog {
33
+
gpio-hog;
34
+
gpios = <RZG2L_GPIO(10, 1) GPIO_ACTIVE_HIGH>;
35
+
output-high;
36
+
line-name = "sd0_pwr_en";
37
+
};
38
+
39
+
sdhi0_pins: sd0 {
40
+
sd0-cd {
41
+
pinmux = <RZG2L_PORT_PINMUX(10, 5, 15)>; /* SD0_CD */
42
+
};
43
+
44
+
sd0-clk {
45
+
pins = "SD0CLK";
46
+
renesas,output-impedance = <3>;
47
+
slew-rate = <0>;
48
+
};
49
+
50
+
sd0-dat-cmd {
51
+
pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3", "SD0CMD";
52
+
input-enable;
53
+
renesas,output-impedance = <3>;
54
+
slew-rate = <0>;
55
+
};
56
+
};
57
+
};
58
+
59
+
&sdhi0 {
60
+
pinctrl-0 = <&sdhi0_pins>;
61
+
pinctrl-1 = <&sdhi0_pins>;
62
+
pinctrl-names = "default", "state_uhs";
63
+
vmmc-supply = <®_3p3v>;
64
+
vqmmc-supply = <&vqmmc_sdhi0>;
65
+
bus-width = <4>;
66
+
sd-uhs-sdr50;
67
+
sd-uhs-sdr104;
68
+
status = "okay";
69
+
};
+1
include/dt-bindings/clock/renesas,r9a09g056-cpg.h
+1
include/dt-bindings/clock/renesas,r9a09g056-cpg.h
+1
include/dt-bindings/clock/renesas,r9a09g057-cpg.h
+1
include/dt-bindings/clock/renesas,r9a09g057-cpg.h