Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mtd/fixes-for-6.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull mtd fixes from Miquel Raynal:
"SPI NAND fix:
- Wrong OOB layout for Winbond W25N01JW SPI NAND devices
Raw NAND fixes:
- Atmel raw NAND controller timings
- Buffer handling in stm32_fmc2 driver
- Error handling in Nuvoton's driver
MTD devices fixes:
- Wrong depends-on dependencies on the Intel DRM driver
* tag 'mtd/fixes-for-6.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
mtd: spinand: winbond: Fix oob_layout for W25N01JW
mtd: nand: raw: atmel: Respect tAR, tCLR in read setup timing
mtd: rawnand: stm32_fmc2: fix ECC overwrite
mtd: rawnand: stm32_fmc2: avoid overlapping mappings on ECC buffer
mtd: rawnand: nuvoton: Fix an error handling path in ma35_nand_chips_init()
mtd: MTD_INTEL_DG should depend on DRM_I915 or DRM_XE
+77
-30
+2
-2
drivers/mtd/devices/Kconfig
+2
-2
drivers/mtd/devices/Kconfig
···
185
185
186
186
config MTD_INTEL_DG
187
187
tristate "Intel Discrete Graphics non-volatile memory driver"
188
-
depends on AUXILIARY_BUS
189
-
depends on MTD
188
+
depends on AUXILIARY_BUS && MTD
189
+
depends on DRM_I915!=n || DRM_XE!=n || COMPILE_TEST
190
190
help
191
191
This provides an MTD device to access Intel Discrete Graphics
192
192
non-volatile memory.
+13
-3
drivers/mtd/nand/raw/atmel/nand-controller.c
+13
-3
drivers/mtd/nand/raw/atmel/nand-controller.c
···
1378
1378
return ret;
1379
1379
1380
1380
/*
1381
+
* Read setup timing depends on the operation done on the NAND:
1382
+
*
1383
+
* NRD_SETUP = max(tAR, tCLR)
1384
+
*/
1385
+
timeps = max(conf->timings.sdr.tAR_min, conf->timings.sdr.tCLR_min);
1386
+
ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1387
+
totalcycles += ncycles;
1388
+
ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NRD_SHIFT, ncycles);
1389
+
if (ret)
1390
+
return ret;
1391
+
1392
+
/*
1381
1393
* The read cycle timing is directly matching tRC, but is also
1382
1394
* dependent on the setup and hold timings we calculated earlier,
1383
1395
* which gives:
1384
1396
*
1385
-
* NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1386
-
*
1387
-
* NRD_SETUP is always 0.
1397
+
* NRD_CYCLE = max(tRC, NRD_SETUP + NRD_PULSE + NRD_HOLD)
1388
1398
*/
1389
1399
ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1390
1400
ncycles = max(totalcycles, ncycles);
+2
-2
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
+2
-2
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
···
935
935
936
936
static int ma35_nand_chips_init(struct device *dev, struct ma35_nand_info *nand)
937
937
{
938
-
struct device_node *np = dev->of_node, *nand_np;
938
+
struct device_node *np = dev->of_node;
939
939
int ret;
940
940
941
-
for_each_child_of_node(np, nand_np) {
941
+
for_each_child_of_node_scoped(np, nand_np) {
942
942
ret = ma35_nand_chip_init(dev, nand, nand_np);
943
943
if (ret) {
944
944
ma35_chips_cleanup(nand);
+24
-22
drivers/mtd/nand/raw/stm32_fmc2_nand.c
+24
-22
drivers/mtd/nand/raw/stm32_fmc2_nand.c
···
272
272
struct sg_table dma_data_sg;
273
273
struct sg_table dma_ecc_sg;
274
274
u8 *ecc_buf;
275
+
dma_addr_t dma_ecc_addr;
275
276
int dma_ecc_len;
276
277
u32 tx_dma_max_burst;
277
278
u32 rx_dma_max_burst;
···
903
902
904
903
if (!write_data && !raw) {
905
904
/* Configure DMA ECC status */
906
-
p = nfc->ecc_buf;
907
905
for_each_sg(nfc->dma_ecc_sg.sgl, sg, eccsteps, s) {
908
-
sg_set_buf(sg, p, nfc->dma_ecc_len);
909
-
p += nfc->dma_ecc_len;
910
-
}
911
-
912
-
ret = dma_map_sg(nfc->dev, nfc->dma_ecc_sg.sgl,
913
-
eccsteps, dma_data_dir);
914
-
if (!ret) {
915
-
ret = -EIO;
916
-
goto err_unmap_data;
906
+
sg_dma_address(sg) = nfc->dma_ecc_addr +
907
+
s * nfc->dma_ecc_len;
908
+
sg_dma_len(sg) = nfc->dma_ecc_len;
917
909
}
918
910
919
911
desc_ecc = dmaengine_prep_slave_sg(nfc->dma_ecc_ch,
···
915
921
DMA_PREP_INTERRUPT);
916
922
if (!desc_ecc) {
917
923
ret = -ENOMEM;
918
-
goto err_unmap_ecc;
924
+
goto err_unmap_data;
919
925
}
920
926
921
927
reinit_completion(&nfc->dma_ecc_complete);
···
923
929
desc_ecc->callback_param = &nfc->dma_ecc_complete;
924
930
ret = dma_submit_error(dmaengine_submit(desc_ecc));
925
931
if (ret)
926
-
goto err_unmap_ecc;
932
+
goto err_unmap_data;
927
933
928
934
dma_async_issue_pending(nfc->dma_ecc_ch);
929
935
}
···
943
949
if (!write_data && !raw)
944
950
dmaengine_terminate_all(nfc->dma_ecc_ch);
945
951
ret = -ETIMEDOUT;
946
-
goto err_unmap_ecc;
952
+
goto err_unmap_data;
947
953
}
948
954
949
955
/* Wait DMA data transfer completion */
···
962
968
ret = -ETIMEDOUT;
963
969
}
964
970
}
965
-
966
-
err_unmap_ecc:
967
-
if (!write_data && !raw)
968
-
dma_unmap_sg(nfc->dev, nfc->dma_ecc_sg.sgl,
969
-
eccsteps, dma_data_dir);
970
971
971
972
err_unmap_data:
972
973
dma_unmap_sg(nfc->dev, nfc->dma_data_sg.sgl, eccsteps, dma_data_dir);
···
985
996
986
997
/* Write oob */
987
998
if (oob_required) {
988
-
ret = nand_change_write_column_op(chip, mtd->writesize,
989
-
chip->oob_poi, mtd->oobsize,
990
-
false);
999
+
unsigned int offset_in_page = mtd->writesize;
1000
+
const void *buf = chip->oob_poi;
1001
+
unsigned int len = mtd->oobsize;
1002
+
1003
+
if (!raw) {
1004
+
struct mtd_oob_region oob_free;
1005
+
1006
+
mtd_ooblayout_free(mtd, 0, &oob_free);
1007
+
offset_in_page += oob_free.offset;
1008
+
buf += oob_free.offset;
1009
+
len = oob_free.length;
1010
+
}
1011
+
1012
+
ret = nand_change_write_column_op(chip, offset_in_page,
1013
+
buf, len, false);
991
1014
if (ret)
992
1015
return ret;
993
1016
}
···
1611
1610
return ret;
1612
1611
1613
1612
/* Allocate a buffer to store ECC status registers */
1614
-
nfc->ecc_buf = devm_kzalloc(nfc->dev, FMC2_MAX_ECC_BUF_LEN, GFP_KERNEL);
1613
+
nfc->ecc_buf = dmam_alloc_coherent(nfc->dev, FMC2_MAX_ECC_BUF_LEN,
1614
+
&nfc->dma_ecc_addr, GFP_KERNEL);
1615
1615
if (!nfc->ecc_buf)
1616
1616
return -ENOMEM;
1617
1617
+36
-1
drivers/mtd/nand/spi/winbond.c
+36
-1
drivers/mtd/nand/spi/winbond.c
···
176
176
.free = w25n02kv_ooblayout_free,
177
177
};
178
178
179
+
static int w25n01jw_ooblayout_ecc(struct mtd_info *mtd, int section,
180
+
struct mtd_oob_region *region)
181
+
{
182
+
if (section > 3)
183
+
return -ERANGE;
184
+
185
+
region->offset = (16 * section) + 12;
186
+
region->length = 4;
187
+
188
+
return 0;
189
+
}
190
+
191
+
static int w25n01jw_ooblayout_free(struct mtd_info *mtd, int section,
192
+
struct mtd_oob_region *region)
193
+
{
194
+
if (section > 3)
195
+
return -ERANGE;
196
+
197
+
region->offset = (16 * section);
198
+
region->length = 12;
199
+
200
+
/* Extract BBM */
201
+
if (!section) {
202
+
region->offset += 2;
203
+
region->length -= 2;
204
+
}
205
+
206
+
return 0;
207
+
}
208
+
179
209
static int w35n01jw_ooblayout_ecc(struct mtd_info *mtd, int section,
180
210
struct mtd_oob_region *region)
181
211
{
···
235
205
236
206
return 0;
237
207
}
208
+
209
+
static const struct mtd_ooblayout_ops w25n01jw_ooblayout = {
210
+
.ecc = w25n01jw_ooblayout_ecc,
211
+
.free = w25n01jw_ooblayout_free,
212
+
};
238
213
239
214
static const struct mtd_ooblayout_ops w35n01jw_ooblayout = {
240
215
.ecc = w35n01jw_ooblayout_ecc,
···
429
394
&write_cache_variants,
430
395
&update_cache_variants),
431
396
0,
432
-
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
397
+
SPINAND_ECCINFO(&w25n01jw_ooblayout, NULL),
433
398
SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg)),
434
399
SPINAND_INFO("W25N01KV", /* 3.3V */
435
400
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),