tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

irqchip/gic-v5: Check if impl is virt capable

Now that there is support for creating a GICv5-based guest with KVM,
check that the hardware itself supports virtualisation, skipping the
setting of struct gic_kvm_info if not.

Note: If native GICv5 virt is not supported, then nor is
FEAT_GCIE_LEGACY, so we are able to skip altogether.

Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20260128175919.3828384-33-sascha.bischoff@arm.com
[maz: cosmetic changes]
Signed-off-by: Marc Zyngier <maz@kernel.org>

authored by

Sascha Bischoff and committed by
Marc Zyngier 3227c3a8 9435c1e1

+16
+2
drivers/irqchip/irq-gic-v5-irs.c
··· 743 743 * be consistent across IRSes by the architecture. 744 744 */ 745 745 if (list_empty(&irs_nodes)) { 746 + idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR0); 747 + gicv5_global_data.virt_capable = !FIELD_GET(GICV5_IRS_IDR0_VIRT, idr); 746 748 747 749 idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR1); 748 750 irs_setup_pri_bits(idr);
+10
drivers/irqchip/irq-gic-v5.c
··· 1064 1064 1065 1065 static void __init gic_of_setup_kvm_info(struct device_node *node) 1066 1066 { 1067 + /* 1068 + * If we don't have native GICv5 virtualisation support, then 1069 + * we also don't have FEAT_GCIE_LEGACY - the architecture 1070 + * forbids this combination. 1071 + */ 1072 + if (!gicv5_global_data.virt_capable) { 1073 + pr_info("GIC implementation is not virtualization capable\n"); 1074 + return; 1075 + } 1076 + 1067 1077 gic_v5_kvm_info.type = GIC_V5; 1068 1078 1069 1079 /* GIC Virtual CPU interface maintenance interrupt */
+4
include/linux/irqchip/arm-gic-v5.h
··· 43 43 /* 44 44 * IRS registers and tables structures 45 45 */ 46 + #define GICV5_IRS_IDR0 0x0000 46 47 #define GICV5_IRS_IDR1 0x0004 47 48 #define GICV5_IRS_IDR2 0x0008 48 49 #define GICV5_IRS_IDR5 0x0014 ··· 63 62 #define GICV5_IRS_IST_CFGR 0x0190 64 63 #define GICV5_IRS_IST_STATUSR 0x0194 65 64 #define GICV5_IRS_MAP_L2_ISTR 0x01c0 65 + 66 + #define GICV5_IRS_IDR0_VIRT BIT(6) 66 67 67 68 #define GICV5_IRS_IDR1_PRIORITY_BITS GENMASK(22, 20) 68 69 #define GICV5_IRS_IDR1_IAFFID_BITS GENMASK(19, 16) ··· 281 278 u8 cpuif_pri_bits; 282 279 u8 cpuif_id_bits; 283 280 u8 irs_pri_bits; 281 + bool virt_capable; 284 282 struct { 285 283 __le64 *l1ist_addr; 286 284 u32 l2_size;