tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'phy-fixes-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy fixes from Vinod Koul:
"A bunch of driver fixes:

- Freescale typec orientation switch fix, clearing register fix,
assertion of phy reset during power on

- Qualcomm pcs register clear before using

- stm one off fix

- TI runtimepm error handling, regmap leak fixes

- Rockchip gadget mode disconnection and disruption fixes

- Tegra register level fix

- Broadcom pointer cast warning fix"

* tag 'phy-fixes-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
phy: freescale: imx8m-pcie: assert phy reset during power on
phy: rockchip: inno-usb2: Fix a double free bug in rockchip_usb2phy_probe()
phy: broadcom: ns-usb3: Fix Wvoid-pointer-to-enum-cast warning (again)
phy: tegra: xusb: Explicitly configure HS_DISCON_LEVEL to 0x7
phy: rockchip: inno-usb2: fix communication disruption in gadget mode
phy: rockchip: inno-usb2: fix disconnection in gadget mode
phy: ti: gmii-sel: fix regmap leak on probe failure
phy: sparx5-serdes: make it selectable for ARCH_LAN969X
phy: ti: da8xx-usb: Handle devm_pm_runtime_enable() errors
phy: stm32-usphyc: Fix off by one in probe()
phy: qcom-qusb2: Fix NULL pointer dereference on early suspend
phy: fsl-imx8mq-usb: Clear the PCS_TX_SWING_FULL field before using it
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for qcs8300
phy: fsl-imx8mq-usb: fix typec orientation switch when built as module

Linus Torvalds 3271b25e 56bc8a18

+33 -50
+2 -15
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
··· 56 56 57 57 clocks: 58 58 minItems: 5 59 - maxItems: 7 59 + maxItems: 6 60 60 61 61 clock-names: 62 62 minItems: 5 ··· 67 67 - enum: [rchng, refgen] 68 68 - const: pipe 69 69 - const: pipediv2 70 - - const: phy_aux 71 70 72 71 power-domains: 73 72 maxItems: 1 ··· 179 180 contains: 180 181 enum: 181 182 - qcom,glymur-qmp-gen5x4-pcie-phy 183 + - qcom,qcs8300-qmp-gen4x2-pcie-phy 182 184 - qcom,sa8775p-qmp-gen4x2-pcie-phy 183 185 - qcom,sa8775p-qmp-gen4x4-pcie-phy 184 186 - qcom,sc8280xp-qmp-gen3x1-pcie-phy ··· 196 196 minItems: 6 197 197 clock-names: 198 198 minItems: 6 199 - 200 - - if: 201 - properties: 202 - compatible: 203 - contains: 204 - enum: 205 - - qcom,qcs8300-qmp-gen4x2-pcie-phy 206 - then: 207 - properties: 208 - clocks: 209 - minItems: 7 210 - clock-names: 211 - minItems: 7 212 199 213 200 - if: 214 201 properties:
+1 -1
drivers/phy/broadcom/phy-bcm-ns-usb3.c
··· 203 203 usb3->dev = dev; 204 204 usb3->mdiodev = mdiodev; 205 205 206 - usb3->family = (enum bcm_ns_family)device_get_match_data(dev); 206 + usb3->family = (unsigned long)device_get_match_data(dev); 207 207 208 208 syscon_np = of_parse_phandle(dev->of_node, "usb3-dmp-syscon", 0); 209 209 err = of_address_to_resource(syscon_np, 0, &res);
+2 -1
drivers/phy/freescale/phy-fsl-imx8m-pcie.c
··· 89 89 writel(imx8_phy->tx_deemph_gen2, 90 90 imx8_phy->base + PCIE_PHY_TRSV_REG6); 91 91 break; 92 - case IMX8MP: /* Do nothing. */ 92 + case IMX8MP: 93 + reset_control_assert(imx8_phy->reset); 93 94 break; 94 95 } 95 96
+1 -14
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
··· 126 126 static void tca_blk_orientation_set(struct tca_blk *tca, 127 127 enum typec_orientation orientation); 128 128 129 - #ifdef CONFIG_TYPEC 130 - 131 129 static int tca_blk_typec_switch_set(struct typec_switch_dev *sw, 132 130 enum typec_orientation orientation) 133 131 { ··· 172 174 { 173 175 typec_switch_unregister(sw); 174 176 } 175 - 176 - #else 177 - 178 - static struct typec_switch_dev *tca_blk_get_typec_switch(struct platform_device *pdev, 179 - struct imx8mq_usb_phy *imx_phy) 180 - { 181 - return NULL; 182 - } 183 - 184 - static void tca_blk_put_typec_switch(struct typec_switch_dev *sw) {} 185 - 186 - #endif /* CONFIG_TYPEC */ 187 177 188 178 static void tca_blk_orientation_set(struct tca_blk *tca, 189 179 enum typec_orientation orientation) ··· 490 504 491 505 if (imx_phy->pcs_tx_swing_full != PHY_TUNE_DEFAULT) { 492 506 value = readl(imx_phy->base + PHY_CTRL5); 507 + value &= ~PHY_CTRL5_PCS_TX_SWING_FULL_MASK; 493 508 value |= FIELD_PREP(PHY_CTRL5_PCS_TX_SWING_FULL_MASK, 494 509 imx_phy->pcs_tx_swing_full); 495 510 writel(value, imx_phy->base + PHY_CTRL5);
+1 -1
drivers/phy/microchip/Kconfig
··· 6 6 config PHY_SPARX5_SERDES 7 7 tristate "Microchip Sparx5 SerDes PHY driver" 8 8 select GENERIC_PHY 9 - depends on ARCH_SPARX5 || COMPILE_TEST 9 + depends on ARCH_SPARX5 || ARCH_LAN969X || COMPILE_TEST 10 10 depends on OF 11 11 depends on HAS_IOMEM 12 12 help
+8 -8
drivers/phy/qualcomm/phy-qcom-qusb2.c
··· 1093 1093 or->hsdisc_trim.override = true; 1094 1094 } 1095 1095 1096 - pm_runtime_set_active(dev); 1097 - pm_runtime_enable(dev); 1096 + dev_set_drvdata(dev, qphy); 1097 + 1098 1098 /* 1099 - * Prevent runtime pm from being ON by default. Users can enable 1100 - * it using power/control in sysfs. 1099 + * Enable runtime PM support, but forbid it by default. 1100 + * Users can allow it again via the power/control attribute in sysfs. 1101 1101 */ 1102 + pm_runtime_set_active(dev); 1102 1103 pm_runtime_forbid(dev); 1104 + ret = devm_pm_runtime_enable(dev); 1105 + if (ret) 1106 + return ret; 1103 1107 1104 1108 generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops); 1105 1109 if (IS_ERR(generic_phy)) { 1106 1110 ret = PTR_ERR(generic_phy); 1107 1111 dev_err(dev, "failed to create phy, %d\n", ret); 1108 - pm_runtime_disable(dev); 1109 1112 return ret; 1110 1113 } 1111 1114 qphy->phy = generic_phy; 1112 1115 1113 - dev_set_drvdata(dev, qphy); 1114 1116 phy_set_drvdata(generic_phy, qphy); 1115 1117 1116 1118 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1117 - if (IS_ERR(phy_provider)) 1118 - pm_runtime_disable(dev); 1119 1119 1120 1120 return PTR_ERR_OR_ZERO(phy_provider); 1121 1121 }
+9 -5
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
··· 821 821 container_of(work, struct rockchip_usb2phy_port, chg_work.work); 822 822 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 823 823 struct regmap *base = get_reg_base(rphy); 824 - bool is_dcd, tmout, vout; 824 + bool is_dcd, tmout, vout, vbus_attach; 825 825 unsigned long delay; 826 + 827 + vbus_attach = property_enabled(rphy->grf, &rport->port_cfg->utmi_bvalid); 826 828 827 829 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n", 828 830 rphy->chg_state); 829 831 switch (rphy->chg_state) { 830 832 case USB_CHG_STATE_UNDEFINED: 831 - if (!rport->suspended) 833 + if (!rport->suspended && !vbus_attach) 832 834 rockchip_usb2phy_power_off(rport->phy); 833 835 /* put the controller in non-driving mode */ 834 - property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 836 + if (!vbus_attach) 837 + property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 835 838 /* Start DCD processing stage 1 */ 836 839 rockchip_chg_enable_dcd(rphy, true); 837 840 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD; ··· 897 894 fallthrough; 898 895 case USB_CHG_STATE_DETECTED: 899 896 /* put the controller in normal mode */ 900 - property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 897 + if (!vbus_attach) 898 + property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 901 899 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); 902 900 dev_dbg(&rport->phy->dev, "charger = %s\n", 903 901 chg_to_string(rphy->chg_type)); ··· 1495 1491 rphy); 1496 1492 if (ret) { 1497 1493 dev_err_probe(rphy->dev, ret, "failed to request usb2phy irq handle\n"); 1498 - goto put_child; 1494 + return ret; 1499 1495 } 1500 1496 } 1501 1497
+1 -1
drivers/phy/st/phy-stm32-usbphyc.c
··· 712 712 } 713 713 714 714 ret = of_property_read_u32(child, "reg", &index); 715 - if (ret || index > usbphyc->nphys) { 715 + if (ret || index >= usbphyc->nphys) { 716 716 dev_err(&phy->dev, "invalid reg property: %d\n", ret); 717 717 if (!ret) 718 718 ret = -EINVAL;
+3
drivers/phy/tegra/xusb-tegra186.c
··· 84 84 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284 85 85 #define BIAS_PAD_PD BIT(11) 86 86 #define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0) 87 + #define HS_DISCON_LEVEL(x) (((x) & 0x7) << 3) 87 88 88 89 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288 89 90 #define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12) ··· 624 623 value &= ~BIAS_PAD_PD; 625 624 value &= ~HS_SQUELCH_LEVEL(~0); 626 625 value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch); 626 + value &= ~HS_DISCON_LEVEL(~0); 627 + value |= HS_DISCON_LEVEL(0x7); 627 628 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 628 629 629 630 udelay(1);
+4 -3
drivers/phy/ti/phy-da8xx-usb.c
··· 180 180 struct da8xx_usb_phy_platform_data *pdata = dev->platform_data; 181 181 struct device_node *node = dev->of_node; 182 182 struct da8xx_usb_phy *d_phy; 183 + int ret; 183 184 184 185 d_phy = devm_kzalloc(dev, sizeof(*d_phy), GFP_KERNEL); 185 186 if (!d_phy) ··· 234 233 return PTR_ERR(d_phy->phy_provider); 235 234 } 236 235 } else { 237 - int ret; 238 - 239 236 ret = phy_create_lookup(d_phy->usb11_phy, "usb-phy", 240 237 "ohci-da8xx"); 241 238 if (ret) ··· 248 249 PHY_INIT_BITS, PHY_INIT_BITS); 249 250 250 251 pm_runtime_set_active(dev); 251 - devm_pm_runtime_enable(dev); 252 + ret = devm_pm_runtime_enable(dev); 253 + if (ret) 254 + return ret; 252 255 /* 253 256 * Prevent runtime pm from being ON by default. Users can enable 254 257 * it using power/control in sysfs.
+1 -1
drivers/phy/ti/phy-gmii-sel.c
··· 512 512 return dev_err_probe(dev, PTR_ERR(base), 513 513 "failed to get base memory resource\n"); 514 514 515 - priv->regmap = regmap_init_mmio(dev, base, &phy_gmii_sel_regmap_cfg); 515 + priv->regmap = devm_regmap_init_mmio(dev, base, &phy_gmii_sel_regmap_cfg); 516 516 if (IS_ERR(priv->regmap)) 517 517 return dev_err_probe(dev, PTR_ERR(priv->regmap), 518 518 "Failed to get syscon\n");