Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Thomas Gleixner:
"A couple of small fixes to x86 perf drivers:
- Measure L2 for HW_CACHE* events on AMD
- Fix the address filter handling in the intel/pt driver
- Handle the BTS disabling at the proper place"
* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2
perf/x86/intel/pt: Do validate the size of a kernel address filter
perf/x86/intel/pt: Fix kernel address filter's offset validation
perf/x86/intel/pt: Fix an off-by-one in address filter configuration
perf/x86/intel: Don't disable "intel_bts" around "intel" event batching
+26
-15
+2
-2
arch/x86/events/amd/core.c
+2
-2
arch/x86/events/amd/core.c
···
119
119
{
120
120
[PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
121
121
[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
122
-
[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080,
123
-
[PERF_COUNT_HW_CACHE_MISSES] = 0x0081,
122
+
[PERF_COUNT_HW_CACHE_REFERENCES] = 0x077d,
123
+
[PERF_COUNT_HW_CACHE_MISSES] = 0x077e,
124
124
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
125
125
[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
126
126
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */
+8
-7
arch/x86/events/intel/core.c
+8
-7
arch/x86/events/intel/core.c
···
1730
1730
* disabled state if called consecutively.
1731
1731
*
1732
1732
* During consecutive calls, the same disable value will be written to related
1733
-
* registers, so the PMU state remains unchanged. hw.state in
1734
-
* intel_bts_disable_local will remain PERF_HES_STOPPED too in consecutive
1735
-
* calls.
1733
+
* registers, so the PMU state remains unchanged.
1734
+
*
1735
+
* intel_bts events don't coexist with intel PMU's BTS events because of
1736
+
* x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
1737
+
* disabled around intel PMU's event batching etc, only inside the PMI handler.
1736
1738
*/
1737
1739
static void __intel_pmu_disable_all(void)
1738
1740
{
···
1744
1742
1745
1743
if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1746
1744
intel_pmu_disable_bts();
1747
-
else
1748
-
intel_bts_disable_local();
1749
1745
1750
1746
intel_pmu_pebs_disable_all();
1751
1747
}
···
1771
1771
return;
1772
1772
1773
1773
intel_pmu_enable_bts(event->hw.config);
1774
-
} else
1775
-
intel_bts_enable_local();
1774
+
}
1776
1775
}
1777
1776
1778
1777
static void intel_pmu_enable_all(int added)
···
2072
2073
*/
2073
2074
if (!x86_pmu.late_ack)
2074
2075
apic_write(APIC_LVTPC, APIC_DM_NMI);
2076
+
intel_bts_disable_local();
2075
2077
__intel_pmu_disable_all();
2076
2078
handled = intel_pmu_drain_bts_buffer();
2077
2079
handled += intel_bts_interrupt();
···
2172
2172
/* Only restore PMU state when it's active. See x86_pmu_disable(). */
2173
2173
if (cpuc->enabled)
2174
2174
__intel_pmu_enable_all(0, true);
2175
+
intel_bts_enable_local();
2175
2176
2176
2177
/*
2177
2178
* Only unmask the NMI after the overflow counters
+14
-4
arch/x86/events/intel/pt.c
+14
-4
arch/x86/events/intel/pt.c
···
1074
1074
event->hw.addr_filters = NULL;
1075
1075
}
1076
1076
1077
+
static inline bool valid_kernel_ip(unsigned long ip)
1078
+
{
1079
+
return virt_addr_valid(ip) && kernel_ip(ip);
1080
+
}
1081
+
1077
1082
static int pt_event_addr_filters_validate(struct list_head *filters)
1078
1083
{
1079
1084
struct perf_addr_filter *filter;
···
1086
1081
1087
1082
list_for_each_entry(filter, filters, entry) {
1088
1083
/* PT doesn't support single address triggers */
1089
-
if (!filter->range)
1084
+
if (!filter->range || !filter->size)
1090
1085
return -EOPNOTSUPP;
1091
1086
1092
-
if (!filter->inode && !kernel_ip(filter->offset))
1093
-
return -EINVAL;
1087
+
if (!filter->inode) {
1088
+
if (!valid_kernel_ip(filter->offset))
1089
+
return -EINVAL;
1090
+
1091
+
if (!valid_kernel_ip(filter->offset + filter->size))
1092
+
return -EINVAL;
1093
+
}
1094
1094
1095
1095
if (++range > pt_cap_get(PT_CAP_num_address_ranges))
1096
1096
return -EOPNOTSUPP;
···
1121
1111
} else {
1122
1112
/* apply the offset */
1123
1113
msr_a = filter->offset + offs[range];
1124
-
msr_b = filter->size + msr_a;
1114
+
msr_b = filter->size + msr_a - 1;
1125
1115
}
1126
1116
1127
1117
filters->filter[range].msr_a = msr_a;
+2
-2
arch/x86/kvm/pmu_amd.c
+2
-2
arch/x86/kvm/pmu_amd.c
···
23
23
static struct kvm_event_hw_type_mapping amd_event_mapping[] = {
24
24
[0] = { 0x76, 0x00, PERF_COUNT_HW_CPU_CYCLES },
25
25
[1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
26
-
[2] = { 0x80, 0x00, PERF_COUNT_HW_CACHE_REFERENCES },
27
-
[3] = { 0x81, 0x00, PERF_COUNT_HW_CACHE_MISSES },
26
+
[2] = { 0x7d, 0x07, PERF_COUNT_HW_CACHE_REFERENCES },
27
+
[3] = { 0x7e, 0x07, PERF_COUNT_HW_CACHE_MISSES },
28
28
[4] = { 0xc2, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
29
29
[5] = { 0xc3, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
30
30
[6] = { 0xd0, 0x00, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND },