clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()

Create helper function fsl_sai_clk_register() to set up and register
SAI clock. Rename BCLK specific struct fsl_sai_clk members with bclk_
prefix. Use of_node_full_name(dev->of_node) and clock name to register
uniquely named clock. This is done in preparation for the follow up
patch, which adds MCLK support.

Signed-off-by: Marek Vasut <marex@nabladev.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Marek Vasut and committed by

Stephen Boyd 3 weeks ago 32b0c7aa f293f885

+62 -26

1 changed file

expand all

drivers

clk

clk-fsl-sai.c

+62 -26

drivers/clk/clk-fsl-sai.c

··· 26 26 }; 27 27 28 28 struct fsl_sai_clk { 29 - struct clk_divider div; 30 - struct clk_gate gate; 29 + struct clk_divider bclk_div; 30 + struct clk_gate bclk_gate; 31 + struct clk_hw *bclk_hw; 31 32 spinlock_t lock; 32 33 }; 34 + 35 + static struct clk_hw * 36 + fsl_sai_of_clk_get(struct of_phandle_args *clkspec, void *data) 37 + { 38 + struct fsl_sai_clk *sai_clk = data; 39 + 40 + return sai_clk->bclk_hw; 41 + } 42 + 43 + static int fsl_sai_clk_register(struct device *dev, void __iomem *base, 44 + spinlock_t *lock, struct clk_divider *div, 45 + struct clk_gate *gate, struct clk_hw **hw, 46 + const int gate_bit, const int dir_bit, 47 + const int div_reg, char *name) 48 + { 49 + const struct fsl_sai_data *data = device_get_match_data(dev); 50 + struct clk_parent_data pdata = { .index = 0 }; 51 + struct clk_hw *chw; 52 + char *cname; 53 + 54 + gate->reg = base + data->offset + I2S_CSR; 55 + gate->bit_idx = gate_bit; 56 + gate->lock = lock; 57 + 58 + div->reg = base + div_reg; 59 + div->shift = CR2_DIV_SHIFT; 60 + div->width = CR2_DIV_WIDTH; 61 + div->lock = lock; 62 + 63 + cname = devm_kasprintf(dev, GFP_KERNEL, "%s.%s", 64 + of_node_full_name(dev->of_node), name); 65 + if (!cname) 66 + return -ENOMEM; 67 + 68 + /* Set clock direction */ 69 + writel(dir_bit, base + div_reg); 70 + 71 + chw = devm_clk_hw_register_composite_pdata(dev, cname, 72 + &pdata, 1, NULL, NULL, 73 + &div->hw, 74 + &clk_divider_ops, 75 + &gate->hw, 76 + &clk_gate_ops, 77 + CLK_SET_RATE_GATE); 78 + if (IS_ERR(chw)) 79 + return PTR_ERR(chw); 80 + 81 + *hw = chw; 82 + 83 + return 0; 84 + } 33 85 34 86 static int fsl_sai_clk_probe(struct platform_device *pdev) 35 87 { 36 88 struct device *dev = &pdev->dev; 37 89 const struct fsl_sai_data *data = device_get_match_data(dev); 38 90 struct fsl_sai_clk *sai_clk; 39 - struct clk_parent_data pdata = { .index = 0 }; 40 91 struct clk *clk_bus; 41 92 void __iomem *base; 42 - struct clk_hw *hw; 93 + int ret; 43 94 44 95 sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL); 45 96 if (!sai_clk) ··· 106 55 107 56 spin_lock_init(&sai_clk->lock); 108 57 109 - sai_clk->gate.reg = base + data->offset + I2S_CSR; 110 - sai_clk->gate.bit_idx = CSR_BCE_BIT; 111 - sai_clk->gate.lock = &sai_clk->lock; 58 + ret = fsl_sai_clk_register(dev, base, &sai_clk->lock, 59 + &sai_clk->bclk_div, &sai_clk->bclk_gate, 60 + &sai_clk->bclk_hw, CSR_BCE_BIT, CR2_BCD, 61 + data->offset + I2S_CR2, "BCLK"); 62 + if (ret) 63 + return ret; 112 64 113 - sai_clk->div.reg = base + data->offset + I2S_CR2; 114 - sai_clk->div.shift = CR2_DIV_SHIFT; 115 - sai_clk->div.width = CR2_DIV_WIDTH; 116 - sai_clk->div.lock = &sai_clk->lock; 117 - 118 - /* set clock direction, we are the BCLK master */ 119 - writel(CR2_BCD, base + data->offset + I2S_CR2); 120 - 121 - hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name, 122 - &pdata, 1, NULL, NULL, 123 - &sai_clk->div.hw, 124 - &clk_divider_ops, 125 - &sai_clk->gate.hw, 126 - &clk_gate_ops, 127 - CLK_SET_RATE_GATE); 128 - if (IS_ERR(hw)) 129 - return PTR_ERR(hw); 130 - 131 - return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 65 + return devm_of_clk_add_hw_provider(dev, fsl_sai_of_clk_get, sai_clk); 132 66 } 133 67 134 68 static const struct fsl_sai_data fsl_sai_vf610_data = {

Configure Feed

Configure Feed