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pwm: meson: Use mul_u64_u64_div_u64() for frequency calculating

While calculating frequency for the given period u64 numbers are
multiplied before division what can lead to overflow in theory so use
secure mul_u64_u64_div_u64() which handles overflow correctly.

Fixes: 329db102a26d ("pwm: meson: make full use of common clock framework")
Suggested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: George Stark <gnstark@salutedevices.com>
Link: https://lore.kernel.org/r/20240425171253.2752877-4-gnstark@salutedevices.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

authored by

George Stark and committed by
Uwe Kleine-König
32c44e1f 3e551115

+2 -2
+2 -2
drivers/pwm/pwm-meson.c
··· 176 176 177 177 dev_dbg(pwmchip_parent(chip), "fin_freq: %ld Hz\n", fin_freq); 178 178 179 - cnt = div_u64(fin_freq * period, NSEC_PER_SEC); 179 + cnt = mul_u64_u64_div_u64(fin_freq, period, NSEC_PER_SEC); 180 180 if (cnt > 0xffff) { 181 181 dev_err(pwmchip_parent(chip), "unable to get period cnt\n"); 182 182 return -EINVAL; ··· 191 191 channel->hi = 0; 192 192 channel->lo = cnt; 193 193 } else { 194 - duty_cnt = div_u64(fin_freq * duty, NSEC_PER_SEC); 194 + duty_cnt = mul_u64_u64_div_u64(fin_freq, duty, NSEC_PER_SEC); 195 195 196 196 dev_dbg(pwmchip_parent(chip), "duty=%llu duty_cnt=%u\n", duty, duty_cnt); 197 197