tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 fixes from Thomas Gleixner:
"A set of small fixes for 4.15:

- Fix vmapped stack synchronization on systems with 4-level paging
and a large amount of memory caused by a missing 5-level folding
which made the pgd synchronization logic to fail and causing double
faults.

- Add a missing sanity check in the vmalloc_fault() logic on 5-level
paging systems.

- Bring back protection against accessing a freed initrd in the
microcode loader which was lost by a wrong merge conflict
resolution.

- Extend the Broadwell micro code loading sanity check.

- Add a missing ENDPROC annotation in ftrace assembly code which
makes ORC unhappy.

- Prevent loading the AMD power module on !AMD platforms. The load
itself is uncritical, but an unload attempt results in a kernel
crash.

- Update Peter Anvins role in the MAINTAINERS file"

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/ftrace: Add one more ENDPROC annotation
x86: Mark hpa as a "Designated Reviewer" for the time being
x86/mm/64: Tighten up vmalloc_fault() sanity checks on 5-level kernels
x86/mm/64: Fix vmapped stack syncing on very-large-memory 4-level systems
x86/microcode: Fix again accessing initrd after having been freed
x86/microcode/intel: Extend BDW late-loading further with LLC size check
perf/x86/amd/power: Do not load AMD power module on !AMD platforms

Linus Torvalds 32c6cdf7 07b0137c

+60 -34
+1 -11
MAINTAINERS
··· 6617 6617 S: Maintained 6618 6618 F: drivers/i2c/i2c-stub.c 6619 6619 6620 - i386 BOOT CODE 6621 - M: "H. Peter Anvin" <hpa@zytor.com> 6622 - S: Maintained 6623 - F: arch/x86/boot/ 6624 - 6625 - i386 SETUP CODE / CPU ERRATA WORKAROUNDS 6626 - M: "H. Peter Anvin" <hpa@zytor.com> 6627 - T: git git://git.kernel.org/pub/scm/linux/kernel/git/hpa/linux-2.6-x86setup.git 6628 - S: Maintained 6629 - 6630 6620 IA64 (Itanium) PLATFORM 6631 6621 M: Tony Luck <tony.luck@intel.com> 6632 6622 M: Fenghua Yu <fenghua.yu@intel.com> ··· 14856 14866 X86 ARCHITECTURE (32-BIT AND 64-BIT) 14857 14867 M: Thomas Gleixner <tglx@linutronix.de> 14858 14868 M: Ingo Molnar <mingo@redhat.com> 14859 - M: "H. Peter Anvin" <hpa@zytor.com> 14869 + R: "H. Peter Anvin" <hpa@zytor.com> 14860 14870 M: x86@kernel.org 14861 14871 L: linux-kernel@vger.kernel.org 14862 14872 T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core
+1 -1
arch/x86/events/amd/power.c
··· 277 277 int ret; 278 278 279 279 if (!x86_match_cpu(cpu_match)) 280 - return 0; 280 + return -ENODEV; 281 281 282 282 if (!boot_cpu_has(X86_FEATURE_ACC_POWER)) 283 283 return -ENODEV;
+1 -1
arch/x86/kernel/cpu/microcode/core.c
··· 239 239 break; 240 240 case X86_VENDOR_AMD: 241 241 if (c->x86 >= 0x10) 242 - return save_microcode_in_initrd_amd(cpuid_eax(1)); 242 + ret = save_microcode_in_initrd_amd(cpuid_eax(1)); 243 243 break; 244 244 default: 245 245 break;
+18 -2
arch/x86/kernel/cpu/microcode/intel.c
··· 45 45 /* Current microcode patch used in early patching on the APs. */ 46 46 static struct microcode_intel *intel_ucode_patch; 47 47 48 + /* last level cache size per core */ 49 + static int llc_size_per_core; 50 + 48 51 static inline bool cpu_signatures_match(unsigned int s1, unsigned int p1, 49 52 unsigned int s2, unsigned int p2) 50 53 { ··· 915 912 916 913 /* 917 914 * Late loading on model 79 with microcode revision less than 0x0b000021 918 - * may result in a system hang. This behavior is documented in item 919 - * BDF90, #334165 (Intel Xeon Processor E7-8800/4800 v4 Product Family). 915 + * and LLC size per core bigger than 2.5MB may result in a system hang. 916 + * This behavior is documented in item BDF90, #334165 (Intel Xeon 917 + * Processor E7-8800/4800 v4 Product Family). 920 918 */ 921 919 if (c->x86 == 6 && 922 920 c->x86_model == INTEL_FAM6_BROADWELL_X && 923 921 c->x86_mask == 0x01 && 922 + llc_size_per_core > 2621440 && 924 923 c->microcode < 0x0b000021) { 925 924 pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode); 926 925 pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); ··· 980 975 .apply_microcode = apply_microcode_intel, 981 976 }; 982 977 978 + static int __init calc_llc_size_per_core(struct cpuinfo_x86 *c) 979 + { 980 + u64 llc_size = c->x86_cache_size * 1024; 981 + 982 + do_div(llc_size, c->x86_max_cores); 983 + 984 + return (int)llc_size; 985 + } 986 + 983 987 struct microcode_ops * __init init_intel_microcode(void) 984 988 { 985 989 struct cpuinfo_x86 *c = &boot_cpu_data; ··· 998 984 pr_err("Intel CPU family 0x%x not supported\n", c->x86); 999 985 return NULL; 1000 986 } 987 + 988 + llc_size_per_core = calc_llc_size_per_core(c); 1001 989 1002 990 return &microcode_intel_ops; 1003 991 }
+1 -1
arch/x86/kernel/ftrace_64.S
··· 295 295 restore_mcount_regs 296 296 297 297 jmp fgraph_trace 298 - END(function_hook) 298 + ENDPROC(function_hook) 299 299 #endif /* CONFIG_DYNAMIC_FTRACE */ 300 300 301 301 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
+9 -13
arch/x86/mm/fault.c
··· 439 439 if (pgd_none(*pgd_ref)) 440 440 return -1; 441 441 442 - if (pgd_none(*pgd)) { 443 - set_pgd(pgd, *pgd_ref); 444 - arch_flush_lazy_mmu_mode(); 445 - } else if (CONFIG_PGTABLE_LEVELS > 4) { 446 - /* 447 - * With folded p4d, pgd_none() is always false, so the pgd may 448 - * point to an empty page table entry and pgd_page_vaddr() 449 - * will return garbage. 450 - * 451 - * We will do the correct sanity check on the p4d level. 452 - */ 453 - BUG_ON(pgd_page_vaddr(*pgd) != pgd_page_vaddr(*pgd_ref)); 442 + if (CONFIG_PGTABLE_LEVELS > 4) { 443 + if (pgd_none(*pgd)) { 444 + set_pgd(pgd, *pgd_ref); 445 + arch_flush_lazy_mmu_mode(); 446 + } else { 447 + BUG_ON(pgd_page_vaddr(*pgd) != pgd_page_vaddr(*pgd_ref)); 448 + } 454 449 } 455 450 456 451 /* With 4-level paging, copying happens on the p4d level. */ ··· 454 459 if (p4d_none(*p4d_ref)) 455 460 return -1; 456 461 457 - if (p4d_none(*p4d)) { 462 + if (p4d_none(*p4d) && CONFIG_PGTABLE_LEVELS == 4) { 458 463 set_p4d(p4d, *p4d_ref); 459 464 arch_flush_lazy_mmu_mode(); 460 465 } else { ··· 465 470 * Below here mismatches are bugs because these lower tables 466 471 * are shared: 467 472 */ 473 + BUILD_BUG_ON(CONFIG_PGTABLE_LEVELS < 4); 468 474 469 475 pud = pud_offset(p4d, address); 470 476 pud_ref = pud_offset(p4d_ref, address);
+29 -5
arch/x86/mm/tlb.c
··· 151 151 local_irq_restore(flags); 152 152 } 153 153 154 + static void sync_current_stack_to_mm(struct mm_struct *mm) 155 + { 156 + unsigned long sp = current_stack_pointer; 157 + pgd_t *pgd = pgd_offset(mm, sp); 158 + 159 + if (CONFIG_PGTABLE_LEVELS > 4) { 160 + if (unlikely(pgd_none(*pgd))) { 161 + pgd_t *pgd_ref = pgd_offset_k(sp); 162 + 163 + set_pgd(pgd, *pgd_ref); 164 + } 165 + } else { 166 + /* 167 + * "pgd" is faked. The top level entries are "p4d"s, so sync 168 + * the p4d. This compiles to approximately the same code as 169 + * the 5-level case. 170 + */ 171 + p4d_t *p4d = p4d_offset(pgd, sp); 172 + 173 + if (unlikely(p4d_none(*p4d))) { 174 + pgd_t *pgd_ref = pgd_offset_k(sp); 175 + p4d_t *p4d_ref = p4d_offset(pgd_ref, sp); 176 + 177 + set_p4d(p4d, *p4d_ref); 178 + } 179 + } 180 + } 181 + 154 182 void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, 155 183 struct task_struct *tsk) 156 184 { ··· 254 226 * mapped in the new pgd, we'll double-fault. Forcibly 255 227 * map it. 256 228 */ 257 - unsigned int index = pgd_index(current_stack_pointer); 258 - pgd_t *pgd = next->pgd + index; 259 - 260 - if (unlikely(pgd_none(*pgd))) 261 - set_pgd(pgd, init_mm.pgd[index]); 229 + sync_current_stack_to_mm(next); 262 230 } 263 231 264 232 /* Stop remote flushes for the previous mm */