tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm-soc-fixes-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM DT and driver fixes from Arnd Bergmann:
"For the devicetree files, there are a total of 20 patches, almost
entirely for 32-bit machines:

- The Allwinner/sun9i r40 SoC dtsi file contains a number of issues,
both for correctness and for style that are addressed in separate
patches. This causes most of the changed lines of the DT updates
this time.

- More Allwinner updates fixing the identification of the security
system on sun8i/A33, a recent regression of the A83t ethernet, and
a few board specific issues on the TBS-A711 macine.

- Several bug fixes for OMAP dts files, most notably fixing the
timings for the NAND flash on the Nokia N900 that regressed a while
ago after the move to configuring them from DT. Some other OMAPs
now set the correct dma limits on the L3 bus, and a regression fix
addresses lost Ethernet on dm814x

- One incorrect setting in the newly added Raspberry Pi Zero W that
may cause issues with the SD card controller.

- A missing property on the bcm2835 firmware node caused incorrect
DMA settings.

- An old bug on the oxnas platform causing spurious interrupts is
finally addressed.

- A regression on the Exynos Midas board broke the OLED panel power
supply.

- The i.MX6 phycore SoM specified the wrong voltage for the SoC, this
is now set to the values from the datasheet.

- Some 64-bit machines use a deprecated string to identify the PSCI
firmware.

There are also several small code fixes addressing mostly serious
issues:

- Fix the sunxi rsb bus access to no longer return incorrect data
when mixing 8 and 16 bit I/O.

- Fix a suspend/resume regression on the OMAP2+ lcdc from a missing
quirk in the ti-sysc driver

- Fix a NULL pointer access from a race in the fsl dpio driver

- Fix a v5.5 regression in the exynos-chipid driver that caused an
invalid error code probing the device on non-exynos platforms

- Fix an out-of-bounds access in the AMD TEE driver"

* tag 'arm-soc-fixes-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (24 commits)
soc: samsung: chipid: Fix return value on non-Exynos platforms
arm64: dts: Fix leftover entry-methods for PSCI
ARM: dts: exynos: Fix regulator node aliasing on Midas-based boards
ARM: dts: oxnas: Fix clear-mask property
ARM: dts: bcm283x: Fix vc4's firmware bus DMA limitations
ARM: dts: omap5: Add bus_dma_limit for L3 bus
ARM: dts: omap4-droid4: Fix lost touchscreen interrupts
ARM: dts: dra7: Add bus_dma_limit for L3 bus
ARM: bcm2835-rpi-zero-w: Add missing pinctrl name
ARM: dts: sun8i: a33: add the new SS compatible
dt-bindings: crypto: add new compatible for A33 SS
ARM: dts: sun8i: r40: Move SPI device nodes based on address order
ARM: dts: sun8i: r40: Fix register base address for SPI2 and SPI3
ARM: dts: sun8i: r40: Move AHCI device node based on address order
ARM: dts: imx6: phycore-som: fix arm and soc minimum voltage
soc: fsl: dpio: register dpio irq handlers after dpio create
tee: amdtee: out of bounds read in find_session()
ARM: dts: N900: fix onenand timings
bus: ti-sysc: Fix quirk flags for lcdc on am335x
ARM: dts: Fix dm814x Ethernet by changing to use rgmii-id mode
...

Linus Torvalds 32db9f10 823846c3

+133 -111
+2
Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml
··· 23 23 - items: 24 24 - const: allwinner,sun7i-a20-crypto 25 25 - const: allwinner,sun4i-a10-crypto 26 + - items: 27 + - const: allwinner,sun8i-a33-crypto 26 28 27 29 reg: 28 30 maxItems: 1
+1
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
··· 112 112 &sdhci { 113 113 #address-cells = <1>; 114 114 #size-cells = <0>; 115 + pinctrl-names = "default"; 115 116 pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; 116 117 bus-width = <4>; 117 118 mmc-pwrseq = <&wifi_pwrseq>;
+1
arch/arm/boot/dts/bcm2835-rpi.dtsi
··· 15 15 firmware: firmware { 16 16 compatible = "raspberrypi,bcm2835-firmware", "simple-bus"; 17 17 mboxes = <&mailbox>; 18 + dma-ranges; 18 19 }; 19 20 20 21 power: power {
+2 -2
arch/arm/boot/dts/dm8148-evm.dts
··· 24 24 25 25 &cpsw_emac0 { 26 26 phy-handle = <&ethphy0>; 27 - phy-mode = "rgmii"; 27 + phy-mode = "rgmii-id"; 28 28 }; 29 29 30 30 &cpsw_emac1 { 31 31 phy-handle = <&ethphy1>; 32 - phy-mode = "rgmii"; 32 + phy-mode = "rgmii-id"; 33 33 }; 34 34 35 35 &davinci_mdio {
+2 -2
arch/arm/boot/dts/dm8148-t410.dts
··· 33 33 34 34 &cpsw_emac0 { 35 35 phy-handle = <&ethphy0>; 36 - phy-mode = "rgmii"; 36 + phy-mode = "rgmii-id"; 37 37 }; 38 38 39 39 &cpsw_emac1 { 40 40 phy-handle = <&ethphy1>; 41 - phy-mode = "rgmii"; 41 + phy-mode = "rgmii-id"; 42 42 }; 43 43 44 44 &davinci_mdio {
+2 -2
arch/arm/boot/dts/dra62x-j5eco-evm.dts
··· 24 24 25 25 &cpsw_emac0 { 26 26 phy-handle = <&ethphy0>; 27 - phy-mode = "rgmii"; 27 + phy-mode = "rgmii-id"; 28 28 }; 29 29 30 30 &cpsw_emac1 { 31 31 phy-handle = <&ethphy1>; 32 - phy-mode = "rgmii"; 32 + phy-mode = "rgmii-id"; 33 33 }; 34 34 35 35 &davinci_mdio {
+1
arch/arm/boot/dts/dra7.dtsi
··· 148 148 #address-cells = <1>; 149 149 #size-cells = <1>; 150 150 ranges = <0x0 0x0 0x0 0xc0000000>; 151 + dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; 151 152 ti,hwmods = "l3_main_1", "l3_main_2"; 152 153 reg = <0x0 0x44000000 0x0 0x1000000>, 153 154 <0x0 0x45000000 0x0 0x1000>;
+2 -2
arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
··· 33 33 }; 34 34 }; 35 35 36 - lcd_vdd3_reg: voltage-regulator-6 { 36 + lcd_vdd3_reg: voltage-regulator-7 { 37 37 compatible = "regulator-fixed"; 38 38 regulator-name = "LCD_VDD_2.2V"; 39 39 regulator-min-microvolt = <2200000>; ··· 42 42 enable-active-high; 43 43 }; 44 44 45 - ps_als_reg: voltage-regulator-7 { 45 + ps_als_reg: voltage-regulator-8 { 46 46 compatible = "regulator-fixed"; 47 47 regulator-name = "LED_A_3.0V"; 48 48 regulator-min-microvolt = <3000000>;
+1 -1
arch/arm/boot/dts/exynos4412-n710x.dts
··· 13 13 14 14 /* bootargs are passed in by bootloader */ 15 15 16 - cam_vdda_reg: voltage-regulator-6 { 16 + cam_vdda_reg: voltage-regulator-7 { 17 17 compatible = "regulator-fixed"; 18 18 regulator-name = "CAM_SENSOR_CORE_1.2V"; 19 19 regulator-min-microvolt = <1200000>;
+2 -2
arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
··· 112 112 regulators { 113 113 vdd_arm: buck1 { 114 114 regulator-name = "vdd_arm"; 115 - regulator-min-microvolt = <730000>; 115 + regulator-min-microvolt = <925000>; 116 116 regulator-max-microvolt = <1380000>; 117 117 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; 118 118 regulator-always-on; ··· 120 120 121 121 vdd_soc: buck2 { 122 122 regulator-name = "vdd_soc"; 123 - regulator-min-microvolt = <730000>; 123 + regulator-min-microvolt = <1150000>; 124 124 regulator-max-microvolt = <1380000>; 125 125 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; 126 126 regulator-always-on;
+1 -1
arch/arm/boot/dts/motorola-mapphone-common.dtsi
··· 429 429 reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */ 430 430 431 431 /* gpio_183 with sys_nirq2 pad as wakeup */ 432 - interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING>, 432 + interrupts-extended = <&gpio6 23 IRQ_TYPE_LEVEL_LOW>, 433 433 <&omap4_pmx_core 0x160>; 434 434 interrupt-names = "irq", "wakeup"; 435 435 wakeup-source;
+28 -16
arch/arm/boot/dts/omap3-n900.dts
··· 854 854 compatible = "ti,omap2-onenand"; 855 855 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ 856 856 857 + /* 858 + * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported 859 + * bootloader set values when booted with v5.1 860 + * (OneNAND Manufacturer: Samsung): 861 + * 862 + * cs0 GPMC_CS_CONFIG1: 0xfb001202 863 + * cs0 GPMC_CS_CONFIG2: 0x00111100 864 + * cs0 GPMC_CS_CONFIG3: 0x00020200 865 + * cs0 GPMC_CS_CONFIG4: 0x11001102 866 + * cs0 GPMC_CS_CONFIG5: 0x03101616 867 + * cs0 GPMC_CS_CONFIG6: 0x90060000 868 + */ 857 869 gpmc,sync-read; 858 870 gpmc,sync-write; 859 871 gpmc,burst-length = <16>; 860 872 gpmc,burst-read; 861 873 gpmc,burst-wrap; 862 874 gpmc,burst-write; 863 - gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ 864 - gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ 875 + gpmc,device-width = <2>; 876 + gpmc,mux-add-data = <2>; 865 877 gpmc,cs-on-ns = <0>; 866 - gpmc,cs-rd-off-ns = <87>; 867 - gpmc,cs-wr-off-ns = <87>; 878 + gpmc,cs-rd-off-ns = <102>; 879 + gpmc,cs-wr-off-ns = <102>; 868 880 gpmc,adv-on-ns = <0>; 869 - gpmc,adv-rd-off-ns = <10>; 870 - gpmc,adv-wr-off-ns = <10>; 871 - gpmc,oe-on-ns = <15>; 872 - gpmc,oe-off-ns = <87>; 881 + gpmc,adv-rd-off-ns = <12>; 882 + gpmc,adv-wr-off-ns = <12>; 883 + gpmc,oe-on-ns = <12>; 884 + gpmc,oe-off-ns = <102>; 873 885 gpmc,we-on-ns = <0>; 874 - gpmc,we-off-ns = <87>; 875 - gpmc,rd-cycle-ns = <112>; 876 - gpmc,wr-cycle-ns = <112>; 877 - gpmc,access-ns = <81>; 878 - gpmc,page-burst-access-ns = <15>; 886 + gpmc,we-off-ns = <102>; 887 + gpmc,rd-cycle-ns = <132>; 888 + gpmc,wr-cycle-ns = <132>; 889 + gpmc,access-ns = <96>; 890 + gpmc,page-burst-access-ns = <18>; 879 891 gpmc,bus-turnaround-ns = <0>; 880 892 gpmc,cycle2cycle-delay-ns = <0>; 881 893 gpmc,wait-monitoring-ns = <0>; 882 - gpmc,clk-activation-ns = <5>; 883 - gpmc,wr-data-mux-bus-ns = <30>; 884 - gpmc,wr-access-ns = <81>; 894 + gpmc,clk-activation-ns = <6>; 895 + gpmc,wr-data-mux-bus-ns = <36>; 896 + gpmc,wr-access-ns = <96>; 885 897 gpmc,sync-clk-ps = <15000>; 886 898 887 899 /*
+1
arch/arm/boot/dts/omap5.dtsi
··· 143 143 #address-cells = <1>; 144 144 #size-cells = <1>; 145 145 ranges = <0 0 0 0xc0000000>; 146 + dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; 146 147 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 147 148 reg = <0 0x44000000 0 0x2000>, 148 149 <0 0x44800000 0 0x3000>,
+2 -2
arch/arm/boot/dts/ox810se.dtsi
··· 323 323 interrupt-controller; 324 324 reg = <0 0x200>; 325 325 #interrupt-cells = <1>; 326 - valid-mask = <0xFFFFFFFF>; 327 - clear-mask = <0>; 326 + valid-mask = <0xffffffff>; 327 + clear-mask = <0xffffffff>; 328 328 }; 329 329 330 330 timer0: timer@200 {
+2 -2
arch/arm/boot/dts/ox820.dtsi
··· 240 240 reg = <0 0x200>; 241 241 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 242 242 #interrupt-cells = <1>; 243 - valid-mask = <0xFFFFFFFF>; 244 - clear-mask = <0>; 243 + valid-mask = <0xffffffff>; 244 + clear-mask = <0xffffffff>; 245 245 }; 246 246 247 247 timer0: timer@200 {
+1 -1
arch/arm/boot/dts/sun8i-a33.dtsi
··· 215 215 }; 216 216 217 217 crypto: crypto-engine@1c15000 { 218 - compatible = "allwinner,sun4i-a10-crypto"; 218 + compatible = "allwinner,sun8i-a33-crypto"; 219 219 reg = <0x01c15000 0x1000>; 220 220 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 221 221 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
+4 -3
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
··· 374 374 }; 375 375 376 376 &reg_dldo3 { 377 - regulator-min-microvolt = <2800000>; 378 - regulator-max-microvolt = <2800000>; 377 + regulator-min-microvolt = <1800000>; 378 + regulator-max-microvolt = <1800000>; 379 379 regulator-name = "vdd-csi"; 380 380 }; 381 381 ··· 498 498 }; 499 499 500 500 &usbphy { 501 - usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ 501 + usb0_id_det-gpios = <&pio 7 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH11 */ 502 + usb0_vbus_power-supply = <&usb_power_supply>; 502 503 usb0_vbus-supply = <&reg_drivevbus>; 503 504 usb1_vbus-supply = <&reg_vmain>; 504 505 usb2_vbus-supply = <&reg_vmain>;
+3 -3
arch/arm/boot/dts/sun8i-a83t.dtsi
··· 1006 1006 reg = <0x01c30000 0x104>; 1007 1007 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1008 1008 interrupt-names = "macirq"; 1009 - resets = <&ccu CLK_BUS_EMAC>; 1010 - reset-names = "stmmaceth"; 1011 - clocks = <&ccu RST_BUS_EMAC>; 1009 + clocks = <&ccu CLK_BUS_EMAC>; 1012 1010 clock-names = "stmmaceth"; 1011 + resets = <&ccu RST_BUS_EMAC>; 1012 + reset-names = "stmmaceth"; 1013 1013 status = "disabled"; 1014 1014 1015 1015 mdio: mdio {
+62 -63
arch/arm/boot/dts/sun8i-r40.dtsi
··· 181 181 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 182 182 }; 183 183 184 + spi0: spi@1c05000 { 185 + compatible = "allwinner,sun8i-r40-spi", 186 + "allwinner,sun8i-h3-spi"; 187 + reg = <0x01c05000 0x1000>; 188 + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 189 + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 190 + clock-names = "ahb", "mod"; 191 + resets = <&ccu RST_BUS_SPI0>; 192 + status = "disabled"; 193 + #address-cells = <1>; 194 + #size-cells = <0>; 195 + }; 196 + 197 + spi1: spi@1c06000 { 198 + compatible = "allwinner,sun8i-r40-spi", 199 + "allwinner,sun8i-h3-spi"; 200 + reg = <0x01c06000 0x1000>; 201 + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 202 + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 203 + clock-names = "ahb", "mod"; 204 + resets = <&ccu RST_BUS_SPI1>; 205 + status = "disabled"; 206 + #address-cells = <1>; 207 + #size-cells = <0>; 208 + }; 209 + 184 210 csi0: csi@1c09000 { 185 211 compatible = "allwinner,sun8i-r40-csi0", 186 212 "allwinner,sun7i-a20-csi0"; ··· 316 290 resets = <&ccu RST_BUS_CE>; 317 291 }; 318 292 293 + spi2: spi@1c17000 { 294 + compatible = "allwinner,sun8i-r40-spi", 295 + "allwinner,sun8i-h3-spi"; 296 + reg = <0x01c17000 0x1000>; 297 + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 298 + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; 299 + clock-names = "ahb", "mod"; 300 + resets = <&ccu RST_BUS_SPI2>; 301 + status = "disabled"; 302 + #address-cells = <1>; 303 + #size-cells = <0>; 304 + }; 305 + 306 + ahci: sata@1c18000 { 307 + compatible = "allwinner,sun8i-r40-ahci"; 308 + reg = <0x01c18000 0x1000>; 309 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 310 + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; 311 + resets = <&ccu RST_BUS_SATA>; 312 + reset-names = "ahci"; 313 + status = "disabled"; 314 + }; 315 + 319 316 ehci1: usb@1c19000 { 320 317 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; 321 318 reg = <0x01c19000 0x100>; ··· 383 334 phys = <&usbphy 2>; 384 335 phy-names = "usb"; 385 336 status = "disabled"; 337 + }; 338 + 339 + spi3: spi@1c1f000 { 340 + compatible = "allwinner,sun8i-r40-spi", 341 + "allwinner,sun8i-h3-spi"; 342 + reg = <0x01c1f000 0x1000>; 343 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 344 + clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; 345 + clock-names = "ahb", "mod"; 346 + resets = <&ccu RST_BUS_SPI3>; 347 + status = "disabled"; 348 + #address-cells = <1>; 349 + #size-cells = <0>; 386 350 }; 387 351 388 352 ccu: clock@1c20000 { ··· 713 651 status = "disabled"; 714 652 #address-cells = <1>; 715 653 #size-cells = <0>; 716 - }; 717 - 718 - spi0: spi@1c05000 { 719 - compatible = "allwinner,sun8i-r40-spi", 720 - "allwinner,sun8i-h3-spi"; 721 - reg = <0x01c05000 0x1000>; 722 - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 723 - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 724 - clock-names = "ahb", "mod"; 725 - resets = <&ccu RST_BUS_SPI0>; 726 - status = "disabled"; 727 - #address-cells = <1>; 728 - #size-cells = <0>; 729 - }; 730 - 731 - spi1: spi@1c06000 { 732 - compatible = "allwinner,sun8i-r40-spi", 733 - "allwinner,sun8i-h3-spi"; 734 - reg = <0x01c06000 0x1000>; 735 - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 736 - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 737 - clock-names = "ahb", "mod"; 738 - resets = <&ccu RST_BUS_SPI1>; 739 - status = "disabled"; 740 - #address-cells = <1>; 741 - #size-cells = <0>; 742 - }; 743 - 744 - spi2: spi@1c07000 { 745 - compatible = "allwinner,sun8i-r40-spi", 746 - "allwinner,sun8i-h3-spi"; 747 - reg = <0x01c07000 0x1000>; 748 - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 749 - clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; 750 - clock-names = "ahb", "mod"; 751 - resets = <&ccu RST_BUS_SPI2>; 752 - status = "disabled"; 753 - #address-cells = <1>; 754 - #size-cells = <0>; 755 - }; 756 - 757 - spi3: spi@1c0f000 { 758 - compatible = "allwinner,sun8i-r40-spi", 759 - "allwinner,sun8i-h3-spi"; 760 - reg = <0x01c0f000 0x1000>; 761 - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 762 - clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; 763 - clock-names = "ahb", "mod"; 764 - resets = <&ccu RST_BUS_SPI3>; 765 - status = "disabled"; 766 - #address-cells = <1>; 767 - #size-cells = <0>; 768 - }; 769 - 770 - ahci: sata@1c18000 { 771 - compatible = "allwinner,sun8i-r40-ahci"; 772 - reg = <0x01c18000 0x1000>; 773 - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 774 - clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; 775 - resets = <&ccu RST_BUS_SATA>; 776 - reset-names = "ahci"; 777 - status = "disabled"; 778 - 779 654 }; 780 655 781 656 gmac: ethernet@1c50000 {
+1 -1
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
··· 53 53 * PSCI node is not added default, U-boot will add missing 54 54 * parts if it determines to use PSCI. 55 55 */ 56 - entry-method = "arm,psci"; 56 + entry-method = "psci"; 57 57 58 58 CPU_PW20: cpu-pw20 { 59 59 compatible = "arm,idle-state";
+1 -1
arch/arm64/boot/dts/sprd/sc9863a.dtsi
··· 108 108 }; 109 109 110 110 idle-states { 111 - entry-method = "arm,psci"; 111 + entry-method = "psci"; 112 112 CORE_PD: core-pd { 113 113 compatible = "arm,idle-state"; 114 114 entry-latency-us = <4000>;
+1 -1
drivers/bus/sunxi-rsb.c
··· 345 345 if (ret) 346 346 goto unlock; 347 347 348 - *buf = readl(rsb->regs + RSB_DATA); 348 + *buf = readl(rsb->regs + RSB_DATA) & GENMASK(len * 8 - 1, 0); 349 349 350 350 unlock: 351 351 mutex_unlock(&rsb->lock);
+2 -1
drivers/bus/ti-sysc.c
··· 1266 1266 SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0), 1267 1267 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 1268 1268 SYSC_MODULE_QUIRK_SGX), 1269 + SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 1270 + SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1269 1271 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, 1270 1272 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1271 1273 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -1, 0x4ea2080d, 0xffffffff, ··· 1296 1294 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 0), 1297 1295 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), 1298 1296 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0), 1299 - SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0), 1300 1297 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0), 1301 1298 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0), 1302 1299 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
+4 -4
drivers/soc/fsl/dpio/dpio-driver.c
··· 233 233 goto err_allocate_irqs; 234 234 } 235 235 236 - err = register_dpio_irq_handlers(dpio_dev, desc.cpu); 237 - if (err) 238 - goto err_register_dpio_irq; 239 - 240 236 priv->io = dpaa2_io_create(&desc, dev); 241 237 if (!priv->io) { 242 238 dev_err(dev, "dpaa2_io_create failed\n"); 243 239 err = -ENOMEM; 244 240 goto err_dpaa2_io_create; 245 241 } 242 + 243 + err = register_dpio_irq_handlers(dpio_dev, desc.cpu); 244 + if (err) 245 + goto err_register_dpio_irq; 246 246 247 247 dev_info(dev, "probed\n"); 248 248 dev_dbg(dev, " receives_notifications = %d\n",
+1 -1
drivers/soc/samsung/exynos-chipid.c
··· 59 59 syscon = of_find_compatible_node(NULL, NULL, 60 60 "samsung,exynos4210-chipid"); 61 61 if (!syscon) 62 - return ENODEV; 62 + return -ENODEV; 63 63 64 64 regmap = device_node_to_regmap(syscon); 65 65 of_node_put(syscon);
+3
drivers/tee/amdtee/core.c
··· 139 139 u32 index = get_session_index(session); 140 140 struct amdtee_session *sess; 141 141 142 + if (index >= TEE_NUM_SESSIONS) 143 + return NULL; 144 + 142 145 list_for_each_entry(sess, &ctxdata->sess_list, list_node) 143 146 if (ta_handle == sess->ta_handle && 144 147 test_bit(index, sess->sess_mask))